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78e9aa70fe
Now that all the targets are utilizing CPU_PC_{FETCH,STORE}, and the
cpu state is multicore, and the STATE_CPU defines match, we can move
it all to the common code.
121 lines
3.8 KiB
Makefile
121 lines
3.8 KiB
Makefile
# Makefile template for Configure for the mn10300 sim library.
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# Copyright (C) 1996-2015 Free Software Foundation, Inc.
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# Written by Cygnus Support.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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## COMMON_PRE_CONFIG_FRAG
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MN10300_OBJS = \
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itable.o semantics.o idecode.o icache.o engine.o irun.o support.o \
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$(SIM_NEW_COMMON_OBJS) \
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op_utils.o \
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sim-hload.o \
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sim-resume.o \
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sim-reason.o \
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sim-stop.o
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SIM_OBJS = $(MN10300_OBJS) interp.o
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SIM_EXTRA_CLEAN = clean-igen
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# Extra dependencies for "sim-main.h"
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SIM_EXTRA_DEPS = mn10300_sim.h itable.h idecode.h
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# Select mn10300 support in nltvals.def.
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NL_TARGET = -DNL_TARGET_mn10300
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INCLUDE = mn10300_sim.h $(srcdir)/../../include/gdb/callback.h
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# List of extra flags to always pass to $(CC).
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SIM_EXTRA_CFLAGS = -DPOLL_QUIT_INTERVAL=0x20
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## COMMON_POST_CONFIG_FRAG
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idecode.o op_utils.o semantics.o: targ-vals.h
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BUILT_SRC_FROM_IGEN = \
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icache.h \
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icache.c \
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idecode.h \
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idecode.c \
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semantics.h \
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semantics.c \
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model.h \
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model.c \
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support.h \
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support.c \
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itable.h \
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itable.c \
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engine.h \
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engine.c \
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irun.c
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$(BUILT_SRC_FROM_IGEN): tmp-igen
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.PHONY: clean-igen
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clean-igen:
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rm -f $(BUILT_SRC_FROM_IGEN)
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rm -f tmp-igen tmp-insns
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../igen/igen:
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cd ../igen && $(MAKE)
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IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
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IGEN_INSN=$(srcdir)/mn10300.igen $(srcdir)/am33.igen $(srcdir)/am33-2.igen
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IGEN_DC=$(srcdir)/mn10300.dc
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tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen
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cd ../igen && $(MAKE)
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../igen/igen \
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$(IGEN_TRACE) \
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-G gen-direct-access \
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-M mn10300,am33 -G gen-multi-sim=am33 \
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-M am33_2 \
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-I $(srcdir) \
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-i $(IGEN_INSN) \
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-o $(IGEN_DC) \
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-x \
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-n icache.h -hc tmp-icache.h \
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-n icache.c -c tmp-icache.c \
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-n semantics.h -hs tmp-semantics.h \
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-n semantics.c -s tmp-semantics.c \
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-n idecode.h -hd tmp-idecode.h \
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-n idecode.c -d tmp-idecode.c \
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-n model.h -hm tmp-model.h \
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-n model.c -m tmp-model.c \
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-n support.h -hf tmp-support.h \
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-n support.c -f tmp-support.c \
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-n itable.h -ht tmp-itable.h \
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-n itable.c -t tmp-itable.c \
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-n engine.h -he tmp-engine.h \
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-n engine.c -e tmp-engine.c \
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-n irun.c -r tmp-irun.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h icache.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c icache.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h idecode.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c idecode.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h semantics.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c semantics.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-model.h model.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-model.c model.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-support.h support.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-support.c support.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-engine.h engine.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-engine.c engine.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-irun.c irun.c
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touch tmp-igen
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interp.o: interp.c $(INCLUDE)
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