Jeff Law 37d6ee9350 Fix right shifts in mcore simulator on 64 bit hosts. ... If the value to be shifted has the sign bit set, the sign bit would get copied into bits 32..63 of the temporary. Those would then be right shifted into the final value giving an incorrect final result. This was observed with upcoming GCC improvements which eliminate unnecessary extensions.		2023-12-01 07:19:50 -07:00
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ChangeLog-2021	sim: rename ChangeLog files to ChangeLog-2021	2021-08-17 20:27:36 -04:00
interp.c	Fix right shifts in mcore simulator on 64 bit hosts.	2023-12-01 07:19:50 -07:00
local.mk	sim: modules.c: fix generation after recent refactors	2023-01-15 20:55:48 -05:00
mcore-sim.h	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
sim-main.h	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00