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binutils-gdb/sim/example-synacor
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Mike Frysinger 36bb57e40c sim: drop configure scripts for simple ports 
These ports only use the pieces that have been unified, so we can
merge them into the common configure script and get rid of their
unique one entirely.

We still compile & link separate run programs, and have dedicated
subdir Makefiles, but the configure script portion is merged.
2021-06-22 19:26:13 -04:00
..
ChangeLog sim: drop configure scripts for simple ports 2021-06-22 19:26:13 -04:00
interp.c sim: overhaul & unify endian settings management 2021-06-17 23:20:13 -04:00
Makefile.in
README
README.arch-spec
sim-main.c sim: split sim-signal.h include out 2021-06-18 00:50:14 -04:00
sim-main.h sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00

README 

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.