mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-28 04:25:10 +08:00
1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
558 lines
12 KiB
C
558 lines
12 KiB
C
/* This file is part of the program GDB, the GNU debugger.
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Copyright (C) 1998-2024 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This must come before any other includes. */
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#include "defs.h"
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#include "sim-main.h"
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#include "hw-main.h"
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/* DEVICE
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mn103iop - mn103002 I/O ports 0-3.
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DESCRIPTION
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Implements the mn103002 i/o ports as described in the mn103002 user guide.
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PROPERTIES
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reg = <ioport-addr> <ioport-size> ...
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BUGS
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*/
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/* The I/O ports' registers' address block */
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struct mn103iop_block {
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unsigned_word base;
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unsigned_word bound;
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};
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enum io_port_register_types {
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P0OUT,
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P1OUT,
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P2OUT,
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P3OUT,
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P0MD,
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P1MD,
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P2MD,
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P3MD,
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P2SS,
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P4SS,
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P0DIR,
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P1DIR,
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P2DIR,
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P3DIR,
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P0IN,
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P1IN,
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P2IN,
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P3IN,
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};
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#define NR_PORTS 4
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enum {
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OUTPUT_BLOCK,
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MODE_BLOCK,
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DED_CTRL_BLOCK,
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CTRL_BLOCK,
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PIN_BLOCK,
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NR_BLOCKS
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};
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typedef struct _mn10300_ioport {
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uint8_t output, output_mode, control, pin;
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struct hw_event *event;
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} mn10300_ioport;
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struct mn103iop {
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struct mn103iop_block block[NR_BLOCKS];
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mn10300_ioport port[NR_PORTS];
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uint8_t p2ss, p4ss;
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};
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/* Finish off the partially created hw device. Attach our local
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callbacks. Wire up our port names etc */
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static hw_io_read_buffer_method mn103iop_io_read_buffer;
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static hw_io_write_buffer_method mn103iop_io_write_buffer;
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static void
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attach_mn103iop_regs (struct hw *me,
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struct mn103iop *io_port)
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{
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int i;
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unsigned_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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for (i=0; i < NR_BLOCKS; ++i )
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{
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if (!hw_find_reg_array_property (me, "reg", i, ®))
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hw_abort (me, "\"reg\" property must contain five addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space,
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&attach_address,
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me);
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io_port->block[i].base = attach_address;
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hw_unit_size_to_attach_size (hw_parent (me),
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®.size,
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&attach_size, me);
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io_port->block[i].bound = attach_address + (attach_size - 1);
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hw_attach_address (hw_parent (me),
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0,
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attach_space, attach_address, attach_size,
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me);
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}
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}
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static void
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mn103iop_finish (struct hw *me)
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{
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struct mn103iop *io_port;
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int i;
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io_port = HW_ZALLOC (me, struct mn103iop);
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set_hw_data (me, io_port);
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set_hw_io_read_buffer (me, mn103iop_io_read_buffer);
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set_hw_io_write_buffer (me, mn103iop_io_write_buffer);
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/* Attach ourself to our parent bus */
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attach_mn103iop_regs (me, io_port);
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/* Initialize the i/o port registers. */
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for ( i=0; i<NR_PORTS; ++i )
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{
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io_port->port[i].output = 0;
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io_port->port[i].output_mode = 0;
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io_port->port[i].control = 0;
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io_port->port[i].pin = 0;
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}
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io_port->port[2].output_mode = 0xff;
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io_port->p2ss = 0;
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io_port->p4ss = 0x0f;
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}
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/* read and write */
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static int
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decode_addr (struct hw *me,
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struct mn103iop *io_port,
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unsigned_word address)
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{
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unsigned_word offset;
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offset = address - io_port->block[0].base;
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switch (offset)
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{
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case 0x00: return P0OUT;
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case 0x01: return P1OUT;
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case 0x04: return P2OUT;
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case 0x05: return P3OUT;
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case 0x20: return P0MD;
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case 0x21: return P1MD;
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case 0x24: return P2MD;
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case 0x25: return P3MD;
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case 0x44: return P2SS;
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case 0x48: return P4SS;
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case 0x60: return P0DIR;
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case 0x61: return P1DIR;
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case 0x64: return P2DIR;
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case 0x65: return P3DIR;
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case 0x80: return P0IN;
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case 0x81: return P1IN;
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case 0x84: return P2IN;
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case 0x85: return P3IN;
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default:
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{
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hw_abort (me, "bad address");
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return -1;
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}
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}
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}
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static void
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read_output_reg (struct hw *me,
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struct mn103iop *io_port,
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unsigned_word io_port_reg,
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const void *dest,
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unsigned nr_bytes)
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{
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if ( nr_bytes == 1 )
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{
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*(uint8_t *)dest = io_port->port[io_port_reg].output;
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}
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else
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{
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hw_abort (me, "bad read size of %d bytes from P%dOUT.", nr_bytes,
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io_port_reg);
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}
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}
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static void
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read_output_mode_reg (struct hw *me,
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struct mn103iop *io_port,
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unsigned_word io_port_reg,
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const void *dest,
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unsigned nr_bytes)
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{
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if ( nr_bytes == 1 )
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{
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/* check if there are fields which can't be written and
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take appropriate action depending what bits are set */
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*(uint8_t *)dest = io_port->port[io_port_reg].output_mode;
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}
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else
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{
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hw_abort (me, "bad read size of %d bytes to P%dMD.", nr_bytes,
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io_port_reg);
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}
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}
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static void
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read_control_reg (struct hw *me,
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struct mn103iop *io_port,
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unsigned_word io_port_reg,
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const void *dest,
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unsigned nr_bytes)
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{
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if ( nr_bytes == 1 )
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{
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*(uint8_t *)dest = io_port->port[io_port_reg].control;
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}
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else
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{
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hw_abort (me, "bad read size of %d bytes to P%dDIR.", nr_bytes,
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io_port_reg);
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}
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}
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static void
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read_pin_reg (struct hw *me,
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struct mn103iop *io_port,
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unsigned_word io_port_reg,
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const void *dest,
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unsigned nr_bytes)
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{
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if ( nr_bytes == 1 )
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{
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*(uint8_t *)dest = io_port->port[io_port_reg].pin;
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}
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else
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{
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hw_abort (me, "bad read size of %d bytes to P%dIN.", nr_bytes,
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io_port_reg);
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}
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}
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static void
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read_dedicated_control_reg (struct hw *me,
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struct mn103iop *io_port,
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unsigned_word io_port_reg,
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const void *dest,
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unsigned nr_bytes)
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{
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if ( nr_bytes == 1 )
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{
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/* select on io_port_reg: */
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if ( io_port_reg == P2SS )
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{
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*(uint8_t *)dest = io_port->p2ss;
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}
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else
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{
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*(uint8_t *)dest = io_port->p4ss;
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}
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}
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else
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{
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hw_abort (me, "bad read size of %d bytes to PSS.", nr_bytes);
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}
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}
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static unsigned
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mn103iop_io_read_buffer (struct hw *me,
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void *dest,
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int space,
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unsigned_word base,
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unsigned nr_bytes)
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{
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struct mn103iop *io_port = hw_data (me);
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enum io_port_register_types io_port_reg;
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HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
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io_port_reg = decode_addr (me, io_port, base);
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switch (io_port_reg)
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{
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/* Port output registers */
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case P0OUT:
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case P1OUT:
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case P2OUT:
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case P3OUT:
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read_output_reg(me, io_port, io_port_reg-P0OUT, dest, nr_bytes);
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break;
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/* Port output mode registers */
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case P0MD:
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case P1MD:
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case P2MD:
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case P3MD:
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read_output_mode_reg(me, io_port, io_port_reg-P0MD, dest, nr_bytes);
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break;
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/* Port control registers */
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case P0DIR:
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case P1DIR:
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case P2DIR:
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case P3DIR:
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read_control_reg(me, io_port, io_port_reg-P0DIR, dest, nr_bytes);
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break;
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/* Port pin registers */
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case P0IN:
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case P1IN:
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case P2IN:
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read_pin_reg(me, io_port, io_port_reg-P0IN, dest, nr_bytes);
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break;
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case P2SS:
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case P4SS:
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read_dedicated_control_reg(me, io_port, io_port_reg, dest, nr_bytes);
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break;
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default:
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hw_abort(me, "invalid address");
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}
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return nr_bytes;
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}
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static void
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write_output_reg (struct hw *me,
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struct mn103iop *io_port,
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unsigned_word io_port_reg,
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const void *source,
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unsigned nr_bytes)
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{
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uint8_t buf = *(uint8_t *)source;
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if ( nr_bytes == 1 )
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{
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if ( io_port_reg == 3 && (buf & 0xfc) != 0 )
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{
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hw_abort(me, "Cannot write to read-only bits of P3OUT.");
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}
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else
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{
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io_port->port[io_port_reg].output = buf;
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}
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}
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else
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{
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hw_abort (me, "bad read size of %d bytes from P%dOUT.", nr_bytes,
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io_port_reg);
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}
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}
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static void
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write_output_mode_reg (struct hw *me,
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struct mn103iop *io_port,
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unsigned_word io_port_reg,
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const void *source,
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unsigned nr_bytes)
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{
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uint8_t buf = *(uint8_t *)source;
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if ( nr_bytes == 1 )
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{
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/* check if there are fields which can't be written and
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take appropriate action depending what bits are set */
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if ( ( io_port_reg == 3 && (buf & 0xfc) != 0 )
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|| ( (io_port_reg == 0 || io_port_reg == 1) && (buf & 0xfe) != 0 ) )
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{
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hw_abort(me, "Cannot write to read-only bits of output mode register.");
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}
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else
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{
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io_port->port[io_port_reg].output_mode = buf;
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}
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}
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else
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{
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hw_abort (me, "bad write size of %d bytes to P%dMD.", nr_bytes,
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io_port_reg);
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}
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}
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static void
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write_control_reg (struct hw *me,
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struct mn103iop *io_port,
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unsigned_word io_port_reg,
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const void *source,
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unsigned nr_bytes)
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{
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uint8_t buf = *(uint8_t *)source;
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if ( nr_bytes == 1 )
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{
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if ( io_port_reg == 3 && (buf & 0xfc) != 0 )
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{
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hw_abort(me, "Cannot write to read-only bits of P3DIR.");
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}
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else
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{
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io_port->port[io_port_reg].control = buf;
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}
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}
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else
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{
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hw_abort (me, "bad write size of %d bytes to P%dDIR.", nr_bytes,
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io_port_reg);
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}
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}
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static void
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write_dedicated_control_reg (struct hw *me,
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struct mn103iop *io_port,
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unsigned_word io_port_reg,
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const void *source,
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unsigned nr_bytes)
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{
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uint8_t buf = *(uint8_t *)source;
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if ( nr_bytes == 1 )
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{
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/* select on io_port_reg: */
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if ( io_port_reg == P2SS )
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{
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if ( (buf & 0xfc) != 0 )
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{
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hw_abort(me, "Cannot write to read-only bits in p2ss.");
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}
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else
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{
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io_port->p2ss = buf;
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}
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}
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else
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{
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if ( (buf & 0xf0) != 0 )
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{
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hw_abort(me, "Cannot write to read-only bits in p4ss.");
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}
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else
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{
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io_port->p4ss = buf;
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}
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}
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}
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else
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{
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hw_abort (me, "bad write size of %d bytes to PSS.", nr_bytes);
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}
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}
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static unsigned
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mn103iop_io_write_buffer (struct hw *me,
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const void *source,
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int space,
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unsigned_word base,
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unsigned nr_bytes)
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{
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struct mn103iop *io_port = hw_data (me);
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enum io_port_register_types io_port_reg;
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HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
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io_port_reg = decode_addr (me, io_port, base);
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switch (io_port_reg)
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{
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/* Port output registers */
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case P0OUT:
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case P1OUT:
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case P2OUT:
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case P3OUT:
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write_output_reg(me, io_port, io_port_reg-P0OUT, source, nr_bytes);
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break;
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/* Port output mode registers */
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case P0MD:
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case P1MD:
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case P2MD:
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case P3MD:
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write_output_mode_reg(me, io_port, io_port_reg-P0MD, source, nr_bytes);
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break;
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/* Port control registers */
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case P0DIR:
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case P1DIR:
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case P2DIR:
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case P3DIR:
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write_control_reg(me, io_port, io_port_reg-P0DIR, source, nr_bytes);
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break;
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/* Port pin registers */
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case P0IN:
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case P1IN:
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case P2IN:
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hw_abort(me, "Cannot write to pin register.");
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break;
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case P2SS:
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case P4SS:
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write_dedicated_control_reg(me, io_port, io_port_reg, source, nr_bytes);
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break;
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default:
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hw_abort(me, "invalid address");
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}
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return nr_bytes;
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}
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const struct hw_descriptor dv_mn103iop_descriptor[] = {
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{ "mn103iop", mn103iop_finish, },
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{ NULL },
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};
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