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fd67aa1129
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
276 lines
16 KiB
C
276 lines
16 KiB
C
/* Opcode table for PDP-11.
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Copyright (C) 2001-2024 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "opcode/pdp11.h"
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const struct pdp11_opcode pdp11_opcodes[] =
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{
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/* name, pattern, mask, opcode type, insn type, alias */
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{ "halt", 0x0000, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "wait", 0x0001, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "rti", 0x0002, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "bpt", 0x0003, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "iot", 0x0004, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "reset", 0x0005, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "rtt", 0x0006, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_LEIS },
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{ "mfpt", 0x0007, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_MFPT },
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{ "jmp", 0x0040, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "rts", 0x0080, 0xfff8, PDP11_OPCODE_REG, PDP11_BASIC },
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{ "", 0x0088, 0xfff8, PDP11_OPCODE_ILLEGAL, PDP11_NONE },
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{ "", 0x0090, 0xfff8, PDP11_OPCODE_ILLEGAL, PDP11_NONE },
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{ "spl", 0x0098, 0xfff8, PDP11_OPCODE_IMM3, PDP11_SPL },
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{ "nop", 0x00a0, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "clc", 0x00a1, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "clv", 0x00a2, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "cl_3", 0x00a3, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "clz", 0x00a4, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "cl_5", 0x00a5, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "cl_6", 0x00a6, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "cl_7", 0x00a7, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "cln", 0x00a8, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "cl_9", 0x00a9, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "cl_a", 0x00aa, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "cl_b", 0x00ab, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "cl_c", 0x00ac, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "cl_d", 0x00ad, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "cl_e", 0x00ae, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "ccc", 0x00af, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "se_0", 0x00b0, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "sec", 0x00b1, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "sev", 0x00b2, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "se_3", 0x00b3, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "sez", 0x00b4, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "se_5", 0x00b5, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "se_6", 0x00b6, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "se_7", 0x00b7, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "sen", 0x00b8, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "se_9", 0x00b9, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "se_a", 0x00ba, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "se_b", 0x00bb, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "se_c", 0x00bc, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "se_d", 0x00bd, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "se_e", 0x00be, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "scc", 0x00bf, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC },
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{ "swab", 0x00c0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "br", 0x0100, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "bne", 0x0200, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "beq", 0x0300, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "bge", 0x0400, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "blt", 0x0500, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "bgt", 0x0600, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "ble", 0x0700, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "jsr", 0x0800, 0xfe00, PDP11_OPCODE_REG_OP, PDP11_BASIC },
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{ "clr", 0x0a00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "com", 0x0a40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "inc", 0x0a80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "dec", 0x0ac0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "neg", 0x0b00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "adc", 0x0b40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "sbc", 0x0b80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "tst", 0x0bc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "ror", 0x0c00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "rol", 0x0c40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "asr", 0x0c80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "asl", 0x0cc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "mark", 0x0d00, 0xffc0, PDP11_OPCODE_IMM6, PDP11_LEIS },
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{ "mfpi", 0x0d40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "mtpi", 0x0d80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "sxt", 0x0dc0, 0xffc0, PDP11_OPCODE_OP, PDP11_LEIS },
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{ "csm", 0x0e00, 0xffc0, PDP11_OPCODE_OP, PDP11_CSM },
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{ "tstset", 0x0e40, 0xffc0, PDP11_OPCODE_OP, PDP11_MPROC },
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{ "wrtlck", 0x0e80, 0xffc0, PDP11_OPCODE_OP, PDP11_MPROC },
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/*{ "", 0x0ec0, 0xffe0, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/
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{ "mov", 0x1000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC },
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{ "cmp", 0x2000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC },
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{ "bit", 0x3000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC },
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{ "bic", 0x4000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC },
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{ "bis", 0x5000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC },
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{ "add", 0x6000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC },
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{ "mul", 0x7000, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS },
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{ "div", 0x7200, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS },
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{ "ash", 0x7400, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS },
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{ "ashc", 0x7600, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS },
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{ "xor", 0x7800, 0xfe00, PDP11_OPCODE_REG_OP, PDP11_LEIS },
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{ "fadd", 0x7a00, 0xfff8, PDP11_OPCODE_REG, PDP11_FIS },
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{ "fsub", 0x7a08, 0xfff8, PDP11_OPCODE_REG, PDP11_FIS },
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{ "fmul", 0x7a10, 0xfff8, PDP11_OPCODE_REG, PDP11_FIS },
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{ "fdiv", 0x7a18, 0xfff8, PDP11_OPCODE_REG, PDP11_FIS },
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/*{ "", 0x7a20, 0xffe0, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/
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/*{ "", 0x7a40, 0xffc0, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/
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/*{ "", 0x7a80, 0xff80, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/
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/*{ "", 0x7b00, 0xffe0, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/
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{ "l2dr", 0x7c10, 0xfff8, PDP11_OPCODE_REG, PDP11_CIS },/*l2d*/
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{ "movc", 0x7c18, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "movrc", 0x7c19, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "movtc", 0x7c1a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "locc", 0x7c20, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "skpc", 0x7c21, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "scanc", 0x7c22, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "spanc", 0x7c23, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cmpc", 0x7c24, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "matc", 0x7c25, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "addn", 0x7c28, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "subn", 0x7c29, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cmpn", 0x7c2a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cvtnl", 0x7c2b, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cvtpn", 0x7c2c, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cvtnp", 0x7c2d, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "ashn", 0x7c2e, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cvtln", 0x7c2f, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "l3dr", 0x7c30, 0xfff8, PDP11_OPCODE_REG, PDP11_CIS },/*l3d*/
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{ "addp", 0x7c38, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "subp", 0x7c39, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cmpp", 0x7c3a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cvtpl", 0x7c3b, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "mulp", 0x7c3c, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "divp", 0x7c3d, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "ashp", 0x7c3e, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cvtlp", 0x7c3f, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "movci", 0x7c58, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "movrci", 0x7c59, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "movtci", 0x7c5a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "locci", 0x7c60, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "skpci", 0x7c61, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "scanci", 0x7c62, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "spanci", 0x7c63, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cmpci", 0x7c64, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "matci", 0x7c65, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "addni", 0x7c68, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "subni", 0x7c69, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cmpni", 0x7c6a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cvtnli", 0x7c6b, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cvtpni", 0x7c6c, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cvtnpi", 0x7c6d, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "ashni", 0x7c6e, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cvtlni", 0x7c6f, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "addpi", 0x7c78, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "subpi", 0x7c79, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cmppi", 0x7c7a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cvtpli", 0x7c7b, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "mulpi", 0x7c7c, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "divpi", 0x7c7d, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "ashpi", 0x7c7e, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "cvtlpi", 0x7c7f, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS },
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{ "med", 0x7d80, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_UCODE },
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{ "xfc", 0x7dc0, 0xffc0, PDP11_OPCODE_IMM6, PDP11_UCODE },
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{ "sob", 0x7e00, 0xfe00, PDP11_OPCODE_REG_DISPL, PDP11_LEIS },
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{ "bpl", 0x8000, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "bmi", 0x8100, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "bhi", 0x8200, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "blos", 0x8300, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "bvc", 0x8400, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "bvs", 0x8500, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "bcc", 0x8600, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },/*bhis*/
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{ "bcs", 0x8700, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },/*blo*/
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{ "emt", 0x8800, 0xff00, PDP11_OPCODE_IMM8, PDP11_BASIC },
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{ "sys", 0x8900, 0xff00, PDP11_OPCODE_IMM8, PDP11_BASIC },/*trap*/
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{ "clrb", 0x8a00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "comb", 0x8a40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "incb", 0x8a80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "decb", 0x8ac0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "negb", 0x8b00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "adcb", 0x8b40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "sbcb", 0x8b80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "tstb", 0x8bc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "rorb", 0x8c00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "rolb", 0x8c40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "asrb", 0x8c80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "aslb", 0x8cc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "mtps", 0x8d00, 0xffc0, PDP11_OPCODE_OP, PDP11_MXPS },
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{ "mfpd", 0x8d40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "mtpd", 0x8d80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC },
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{ "mfps", 0x8dc0, 0xffc0, PDP11_OPCODE_OP, PDP11_MXPS },
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{ "movb", 0x9000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC },
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{ "cmpb", 0xa000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC },
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{ "bitb", 0xb000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC },
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{ "bicb", 0xc000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC },
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{ "bisb", 0xd000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC },
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{ "sub", 0xe000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC },
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{ "cfcc", 0xf000, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP },
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{ "setf", 0xf001, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP },
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{ "seti", 0xf002, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP },
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{ "ldub", 0xf003, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_UCODE },
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/* fpp trap 0xf004..0xf008 */
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{ "setd", 0xf009, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP },
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{ "setl", 0xf00a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP },
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/* fpp trap 0xf00b..0xf03f */
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{ "ldfps", 0xf040, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP },
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{ "stfps", 0xf080, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP },
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{ "stst", 0xf0c0, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP },
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{ "clrf", 0xf100, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "tstf", 0xf140, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "absf", 0xf180, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "negf", 0xf1c0, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "mulf", 0xf200, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "modf", 0xf300, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "addf", 0xf400, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "ldf", 0xf500, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/*movif*/
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{ "subf", 0xf600, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "cmpf", 0xf700, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "stf", 0xf800, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/*movfi*/
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{ "divf", 0xf900, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "stexp", 0xfa00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "stcfi", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "stcff", 0xfc00, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/* ? */
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{ "ldexp", 0xfd00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP },
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{ "ldcif", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP },
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{ "ldcff", 0xff00, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/* ? */
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/* This entry MUST be last; it is a "catch-all" entry that will match when no
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* other opcode entry matches during disassembly.
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*/
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{ "", 0x0000, 0x0000, PDP11_OPCODE_ILLEGAL, PDP11_NONE },
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};
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const struct pdp11_opcode pdp11_aliases[] =
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{
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/* name, pattern, mask, opcode type, insn type */
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{ "l2d", 0x7c10, 0xfff8, PDP11_OPCODE_REG, PDP11_CIS },
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{ "l3d", 0x7c30, 0xfff8, PDP11_OPCODE_REG, PDP11_CIS },
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{ "bhis", 0x8600, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "blo", 0x8700, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },
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{ "trap", 0x8900, 0xff00, PDP11_OPCODE_IMM8, PDP11_BASIC },
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/* fpp xxxd alternate names to xxxf opcodes */
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{ "clrd", 0xf100, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "tstd", 0xf140, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "absd", 0xf180, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "negd", 0xf1c0, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP },
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{ "muld", 0xf200, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "modd", 0xf300, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "addd", 0xf400, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "ldd", 0xf500, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/*movif*/
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{ "subd", 0xf600, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "cmpd", 0xf700, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "std", 0xf800, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/*movfi*/
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{ "divd", 0xf900, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },
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{ "stcfl", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "stcdi", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "stcdl", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP },
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{ "stcfd", 0xfc00, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/* ? */
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{ "stcdf", 0xfc00, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/* ? */
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{ "ldcid", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP },
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{ "ldclf", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP },
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{ "ldcld", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP },
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{ "ldcfd", 0xff00, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/* ? */
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{ "ldcdf", 0xff00, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/* ? */
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};
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const int pdp11_num_opcodes = sizeof pdp11_opcodes / sizeof pdp11_opcodes[0];
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const int pdp11_num_aliases = sizeof pdp11_aliases / sizeof pdp11_aliases[0];
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