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646d754d14
This commit builds on the previous series of commits to share the
target description caching code between GDB and gdbserver for
x86/Linux targets.
The objective of this commit is to move the four functions (2 each of)
i386_linux_read_description and amd64_linux_read_description into the
gdb/arch/ directory and combine them so we have just a single copy of
each. Then GDB, gdbserver, and the in-process-agent (IPA) will link
against these shared functions.
One curiosity with this patch is the function
x86_linux_post_init_tdesc. On the gdbserver side the two functions
amd64_linux_read_description and i386_linux_read_description have some
functionality that is not present on the GDB side, there is some
additional configuration that is performed as each target description
is created, to setup the expedited registers.
To support this I've added the function x86_linux_post_init_tdesc.
This function is called from the two *_linux_read_description
functions, but is implemented separately for GDB and gdbserver.
An alternative approach that avoids adding x86_linux_post_init_tdesc
would be to have x86_linux_tdesc_for_tid return a non-const target
description, then in x86_target::low_arch_setup we could inspect the
target description to figure out if it is 64-bit or not, and modify
the target description as needed. In the end I think that adding the
x86_linux_post_init_tdesc function is the simpler solution.
The contents of gdbserver/linux-x86-low.cc have moved to
gdb/arch/x86-linux-tdesc-features.c, and gdbserver/linux-x86-tdesc.h
has moved to gdb/arch/x86-linux-tdesc-features.h, this change leads to
some updates in the #includes in the gdbserver/ directory.
This commit also changes how target descriptions are cached.
Previously both GDB and gdbserver used static C-style arrays to act as
the tdesc cache. This was fine, except for two problems. Either the
C-style arrays would need to be placed in x86-linux-tdesc-features.c,
which would allow us to use the x86_linux_*_tdesc_count_1() functions
to size the arrays for us, or we'd need to hard code the array sizes
using separate #defines, which we'd then have to keep in sync with the
rest of the code in x86-linux-tdesc-features.c.
Given both of these problems I decided a better solution would be to
just switch to using a std::unordered_map to act as the cache. This
will resize automatically, and we can use the xcr0 value as the key.
At first inspection, using xcr0 might seem to be a problem; after all
the {i386,amd64}_create_target_description functions take more than
just the xcr0 value. However, this patch is only for x86/Linux
targets, and for x86/Linux all of the other flags passed to the tdesc
creation functions have constant values and so are irrelevant when we
consider tdesc caching.
For testing I've done the following:
- Built on x86-64 GNU/Linux for all targets, and just for the native
target,
- Build on i386 GNU/Linux for all targets, and just for the native
target,
- Build on a 64-bit, non-x86 GNU/Linux for all targets, just for the
native target, and for targets x86_64-*-linux and i386-*-linux.
Approved-By: Felix Willgerodt <felix.willgerodt@intel.com>
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|---|---|---|
| .. | ||
| aarch32.c | ||
| aarch32.h | ||
| aarch64-insn.c | ||
| aarch64-insn.h | ||
| aarch64-mte-linux.c | ||
| aarch64-mte-linux.h | ||
| aarch64-scalable-linux.c | ||
| aarch64-scalable-linux.h | ||
| aarch64.c | ||
| aarch64.h | ||
| amd64-linux-tdesc.c | ||
| amd64-linux-tdesc.h | ||
| amd64.c | ||
| amd64.h | ||
| arc.c | ||
| arc.h | ||
| arm-get-next-pcs.c | ||
| arm-get-next-pcs.h | ||
| arm-linux.c | ||
| arm-linux.h | ||
| arm.c | ||
| arm.h | ||
| csky.c | ||
| csky.h | ||
| i386-linux-tdesc.c | ||
| i386-linux-tdesc.h | ||
| i386.c | ||
| i386.h | ||
| loongarch.c | ||
| loongarch.h | ||
| ppc-linux-common.c | ||
| ppc-linux-common.h | ||
| ppc-linux-tdesc.h | ||
| riscv.c | ||
| riscv.h | ||
| tic6x.c | ||
| tic6x.h | ||
| x86-linux-tdesc-features.c | ||
| x86-linux-tdesc-features.h | ||
| x86-linux-tdesc.h | ||
| xtensa.h | ||