mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-19 15:23:30 +08:00
0cc7872125
Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits
in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32
in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx).
There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8
operands predated our current conventions; those instructions moved to map 3.
FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3
is very sparsely populated. Most of the FP16 instructions share opcodes and
prefix (EVEX.pp) bits with the related FP32 operations.
Intel AVX512 FP16 instructions has new displacements scaling rules, please refer
to the public software developer manual for detail information.
gas/
2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Wei Xiao <wei3.xiao@intel.com>
Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (struct Broadcast_Operation): Adjust comment.
(cpu_arch): Add .avx512_fp16.
(cpu_noarch): Add noavx512_fp16.
(pte): Add evexmap5 and evexmap6.
(build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6.
(check_VecOperations): Handle {1to32}.
(check_VecOperands): Handle CheckRegNumb.
(check_word_reg): Handle Toqword.
(i386_error): Add invalid_dest_and_src_register_set.
(match_template): Handle invalid_dest_and_src_register_set.
* doc/c-i386.texi: Document avx512_fp16, noavx512_fp16.
opcodes/
2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Wei Xiao <wei3.xiao@intel.com>
Lili Cui <lili.cui@intel.com>
* i386-dis.c (EXwScalarS): New.
(EXxh): Ditto.
(EXxhc): Ditto.
(EXxmmqh): Ditto.
(EXxmmqdh): Ditto.
(EXEvexXwb): Ditto.
(DistinctDest_Fixup): Ditto.
(enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode
and w_swap_mode.
(enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0,
PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56,
PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67,
PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11,
PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C,
PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F,
PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59,
PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1,
PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1,
PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E,
PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79,
PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C,
PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56,
PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7
(enum): Add EVEX_MAP5 and EVEX_MAP6.
(enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B,
EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0,
EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3,
EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2,
EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2,
(get_valid_dis386): Properly handle new instructions.
(intel_operand_size): Handle new modes.
(OP_E_memory): Ditto.
(OP_EX): Ditto.
* i386-dis-evex.h: Updated for AVX512_FP16.
* i386-dis-evex-mod.h: Updated for AVX512_FP16.
* i386-dis-evex-prefix.h: Updated for AVX512_FP16.
* i386-dis-evex-reg.h : Updated for AVX512_FP16.
* i386-dis-evex-w.h : Updated for AVX512_FP16.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS,
and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS
and CPU_ANY_AVX512BW_FLAGS.
(cpu_flags): Add CpuAVX512_FP16.
(opcode_modifiers): Add DistinctDest.
* i386-opc.h (enum): (AVX512_FP16): New.
(i386_opcode_modifier): Add reqdistinctreg.
(i386_cpu_flags): Add cpuavx512_fp16.
(EVEXMAP5): Defined as a macro.
(EVEXMAP6): Ditto.
* i386-opc.tbl: Add Intel AVX512_FP16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Ditto.
698 lines
15 KiB
C
698 lines
15 KiB
C
/* EVEX_W_0F10_P_1 */
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{
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{ "vmovss", { XMScalar, VexScalarR, EXd }, 0 },
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},
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/* EVEX_W_0F10_P_3 */
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{
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{ Bad_Opcode },
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{ "vmovsd", { XMScalar, VexScalarR, EXq }, 0 },
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},
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/* EVEX_W_0F11_P_1 */
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{
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{ "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
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},
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/* EVEX_W_0F11_P_3 */
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{
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{ Bad_Opcode },
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{ "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
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},
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/* EVEX_W_0F12_P_0_M_1 */
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{
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{ "vmovhlps", { XMM, Vex, EXq }, 0 },
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},
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/* EVEX_W_0F12_P_1 */
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{
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{ "vmovsldup", { XM, EXEvexXNoBcst }, 0 },
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},
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/* EVEX_W_0F12_P_3 */
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{
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{ Bad_Opcode },
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{ "vmovddup", { XM, EXymmq }, 0 },
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},
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/* EVEX_W_0F16_P_0_M_1 */
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{
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{ "vmovlhps", { XMM, Vex, EXx }, 0 },
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},
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/* EVEX_W_0F16_P_1 */
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{
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{ "vmovshdup", { XM, EXx }, 0 },
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},
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/* EVEX_W_0F51_P_1 */
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{
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{ "vsqrtss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F51_P_3 */
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{
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{ Bad_Opcode },
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{ "vsqrtsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F58_P_1 */
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{
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{ "vaddss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F58_P_3 */
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{
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{ Bad_Opcode },
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{ "vaddsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F59_P_1 */
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{
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{ "vmulss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F59_P_3 */
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{
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{ Bad_Opcode },
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{ "vmulsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F5A_P_0 */
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{
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{ "vcvtps2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
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},
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/* EVEX_W_0F5A_P_1 */
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{
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{ "vcvtss2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
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},
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/* EVEX_W_0F5A_P_2 */
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{
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{ Bad_Opcode },
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{ "vcvtpd2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F5A_P_3 */
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{
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{ Bad_Opcode },
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{ "vcvtsd2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F5B_P_0 */
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{
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{ "vcvtdq2ps", { XM, EXx, EXxEVexR }, 0 },
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{ "vcvtqq2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F5B_P_1 */
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{
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{ "vcvttps2dq", { XM, EXx, EXxEVexS }, 0 },
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},
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/* EVEX_W_0F5B_P_2 */
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{
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{ "vcvtps2dq", { XM, EXx, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F5C_P_1 */
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{
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{ "vsubss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F5C_P_3 */
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{
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{ Bad_Opcode },
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{ "vsubsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F5D_P_1 */
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{
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{ "vminss", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
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},
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/* EVEX_W_0F5D_P_3 */
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{
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{ Bad_Opcode },
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{ "vminsd", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
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},
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/* EVEX_W_0F5E_P_1 */
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{
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{ "vdivss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F5E_P_3 */
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{
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{ Bad_Opcode },
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{ "vdivsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F5F_P_1 */
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{
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{ "vmaxss", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
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},
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/* EVEX_W_0F5F_P_3 */
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{
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{ Bad_Opcode },
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{ "vmaxsd", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
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},
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/* EVEX_W_0F62 */
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{
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{ "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0F66 */
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{
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{ "vpcmpgtd", { MaskG, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0F6A */
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{
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{ "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0F6B */
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{
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{ "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0F6C */
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{
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{ Bad_Opcode },
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{ "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0F6D */
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{
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{ Bad_Opcode },
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{ "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0F6F_P_1 */
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{
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{ "vmovdqu32", { XM, EXEvexXNoBcst }, 0 },
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{ "vmovdqu64", { XM, EXEvexXNoBcst }, 0 },
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},
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/* EVEX_W_0F6F_P_2 */
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{
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{ "vmovdqa32", { XM, EXEvexXNoBcst }, 0 },
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{ "vmovdqa64", { XM, EXEvexXNoBcst }, 0 },
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},
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/* EVEX_W_0F6F_P_3 */
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{
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{ "vmovdqu8", { XM, EXx }, 0 },
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{ "vmovdqu16", { XM, EXx }, 0 },
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},
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/* EVEX_W_0F70_P_2 */
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{
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{ "vpshufd", { XM, EXx, Ib }, 0 },
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},
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/* EVEX_W_0F72_R_2 */
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{
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{ "vpsrld", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* EVEX_W_0F72_R_6 */
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{
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{ "vpslld", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* EVEX_W_0F73_R_2 */
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{
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{ Bad_Opcode },
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{ "vpsrlq", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* EVEX_W_0F73_R_6 */
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{
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{ Bad_Opcode },
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{ "vpsllq", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* EVEX_W_0F76 */
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{
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{ "vpcmpeqd", { MaskG, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0F78_P_0 */
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{
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{ "vcvttps2udq", { XM, EXx, EXxEVexS }, 0 },
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{ "vcvttpd2udq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
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},
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/* EVEX_W_0F78_P_2 */
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{
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{ "vcvttps2uqq", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
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{ "vcvttpd2uqq", { XM, EXx, EXxEVexS }, 0 },
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},
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/* EVEX_W_0F79_P_0 */
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{
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{ "vcvtps2udq", { XM, EXx, EXxEVexR }, 0 },
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{ "vcvtpd2udq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F79_P_2 */
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{
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{ "vcvtps2uqq", { XM, EXEvexHalfBcstXmmq, EXxEVexR }, 0 },
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{ "vcvtpd2uqq", { XM, EXx, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F7A_P_1 */
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{
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{ "vcvtudq2pd", { XM, EXEvexHalfBcstXmmq }, 0 },
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{ "vcvtuqq2pd", { XM, EXx, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F7A_P_2 */
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{
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{ "vcvttps2qq", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
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{ "vcvttpd2qq", { XM, EXx, EXxEVexS }, 0 },
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},
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/* EVEX_W_0F7A_P_3 */
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{
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{ "vcvtudq2ps", { XM, EXx, EXxEVexR }, 0 },
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{ "vcvtuqq2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F7B_P_2 */
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{
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{ "vcvtps2qq", { XM, EXEvexHalfBcstXmmq, EXxEVexR }, 0 },
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{ "vcvtpd2qq", { XM, EXx, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F7E_P_1 */
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{
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{ Bad_Opcode },
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{ VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
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},
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/* EVEX_W_0F7F_P_1 */
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{
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{ "vmovdqu32", { EXxS, XM }, 0 },
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{ "vmovdqu64", { EXxS, XM }, 0 },
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},
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/* EVEX_W_0F7F_P_2 */
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{
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{ "vmovdqa32", { EXxS, XM }, 0 },
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{ "vmovdqa64", { EXxS, XM }, 0 },
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},
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/* EVEX_W_0F7F_P_3 */
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{
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{ "vmovdqu8", { EXxS, XM }, 0 },
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{ "vmovdqu16", { EXxS, XM }, 0 },
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},
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/* EVEX_W_0FC2_P_1 */
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{
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{ "vcmpss", { MaskG, VexScalar, EXd, EXxEVexS, CMP }, 0 },
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},
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/* EVEX_W_0FC2_P_3 */
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{
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{ Bad_Opcode },
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{ "vcmpsd", { MaskG, VexScalar, EXq, EXxEVexS, CMP }, 0 },
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},
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/* EVEX_W_0FD2 */
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{
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{ "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
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},
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/* EVEX_W_0FD3 */
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{
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{ Bad_Opcode },
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{ "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
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},
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/* EVEX_W_0FD4 */
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{
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{ Bad_Opcode },
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{ "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0FD6 */
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{
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{ Bad_Opcode },
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{ VEX_LEN_TABLE (VEX_LEN_0FD6) },
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},
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/* EVEX_W_0FE6_P_1 */
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{
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{ "vcvtdq2pd", { XM, EXEvexHalfBcstXmmq }, 0 },
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{ "vcvtqq2pd", { XM, EXx, EXxEVexR }, 0 },
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},
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/* EVEX_W_0FE6_P_2 */
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{
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{ Bad_Opcode },
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{ "vcvttpd2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
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},
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/* EVEX_W_0FE6_P_3 */
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{
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{ Bad_Opcode },
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{ "vcvtpd2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
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},
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/* EVEX_W_0FE7 */
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{
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{ "vmovntdq", { EXEvexXNoBcst, XM }, PREFIX_DATA },
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},
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/* EVEX_W_0FF2 */
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{
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{ "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
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},
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/* EVEX_W_0FF3 */
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{
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{ Bad_Opcode },
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{ "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
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},
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/* EVEX_W_0FF4 */
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{
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{ Bad_Opcode },
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{ "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0FFA */
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{
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{ "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0FFB */
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{
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{ Bad_Opcode },
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{ "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0FFE */
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{
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{ "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0F380D */
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{
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{ Bad_Opcode },
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{ "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
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},
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/* EVEX_W_0F3810_P_1 */
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{
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{ "vpmovuswb", { EXxmmq, XM }, 0 },
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},
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/* EVEX_W_0F3810_P_2 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpsrlvw", { XM, Vex, EXx }, 0 },
|
|
},
|
|
/* EVEX_W_0F3811_P_1 */
|
|
{
|
|
{ "vpmovusdb", { EXxmmqd, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3811_P_2 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpsravw", { XM, Vex, EXx }, 0 },
|
|
},
|
|
/* EVEX_W_0F3812_P_1 */
|
|
{
|
|
{ "vpmovusqb", { EXxmmdw, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3812_P_2 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpsllvw", { XM, Vex, EXx }, 0 },
|
|
},
|
|
/* EVEX_W_0F3813_P_1 */
|
|
{
|
|
{ "vpmovusdw", { EXxmmq, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3813_P_2 */
|
|
{
|
|
{ "vcvtph2ps", { XM, EXxmmq, EXxEVexS }, 0 },
|
|
},
|
|
/* EVEX_W_0F3814_P_1 */
|
|
{
|
|
{ "vpmovusqw", { EXxmmqd, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3815_P_1 */
|
|
{
|
|
{ "vpmovusqd", { EXxmmq, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3819_L_n */
|
|
{
|
|
{ "vbroadcastf32x2", { XM, EXq }, PREFIX_DATA },
|
|
{ "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F381A_M_0_L_n */
|
|
{
|
|
{ "vbroadcastf32x4", { XM, EXxmm }, PREFIX_DATA },
|
|
{ "vbroadcastf64x2", { XM, EXxmm }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F381B_M_0_L_2 */
|
|
{
|
|
{ "vbroadcastf32x8", { XM, EXymm }, PREFIX_DATA },
|
|
{ "vbroadcastf64x4", { XM, EXymm }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F381E */
|
|
{
|
|
{ "vpabsd", { XM, EXx }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F381F */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpabsq", { XM, EXx }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3820_P_1 */
|
|
{
|
|
{ "vpmovswb", { EXxmmq, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3821_P_1 */
|
|
{
|
|
{ "vpmovsdb", { EXxmmqd, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3822_P_1 */
|
|
{
|
|
{ "vpmovsqb", { EXxmmdw, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3823_P_1 */
|
|
{
|
|
{ "vpmovsdw", { EXxmmq, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3824_P_1 */
|
|
{
|
|
{ "vpmovsqw", { EXxmmqd, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3825_P_1 */
|
|
{
|
|
{ "vpmovsqd", { EXxmmq, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3825_P_2 */
|
|
{
|
|
{ "vpmovsxdq", { XM, EXxmmq }, 0 },
|
|
},
|
|
/* EVEX_W_0F3828_P_2 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpmuldq", { XM, Vex, EXx }, 0 },
|
|
},
|
|
/* EVEX_W_0F3829_P_2 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpcmpeqq", { MaskG, Vex, EXx }, 0 },
|
|
},
|
|
/* EVEX_W_0F382A_P_1 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ MOD_TABLE (MOD_EVEX_0F382A_P_1_W_1) },
|
|
},
|
|
/* EVEX_W_0F382A_P_2 */
|
|
{
|
|
{ "vmovntdqa", { XM, EXEvexXNoBcst }, 0 },
|
|
},
|
|
/* EVEX_W_0F382B */
|
|
{
|
|
{ "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3830_P_1 */
|
|
{
|
|
{ "vpmovwb", { EXxmmq, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3831_P_1 */
|
|
{
|
|
{ "vpmovdb", { EXxmmqd, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3832_P_1 */
|
|
{
|
|
{ "vpmovqb", { EXxmmdw, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3833_P_1 */
|
|
{
|
|
{ "vpmovdw", { EXxmmq, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3834_P_1 */
|
|
{
|
|
{ "vpmovqw", { EXxmmqd, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3835_P_1 */
|
|
{
|
|
{ "vpmovqd", { EXxmmq, XM }, 0 },
|
|
},
|
|
/* EVEX_W_0F3835_P_2 */
|
|
{
|
|
{ "vpmovzxdq", { XM, EXxmmq }, 0 },
|
|
},
|
|
/* EVEX_W_0F3837 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpcmpgtq", { MaskG, Vex, EXx }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F383A_P_1 */
|
|
{
|
|
{ MOD_TABLE (MOD_EVEX_0F383A_P_1_W_0) },
|
|
},
|
|
/* EVEX_W_0F3852_P_1 */
|
|
{
|
|
{ "vdpbf16ps", { XM, Vex, EXx }, 0 },
|
|
{ Bad_Opcode },
|
|
},
|
|
/* EVEX_W_0F3859 */
|
|
{
|
|
{ "vbroadcasti32x2", { XM, EXq }, PREFIX_DATA },
|
|
{ "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F385A_M_0_L_n */
|
|
{
|
|
{ "vbroadcasti32x4", { XM, EXxmm }, PREFIX_DATA },
|
|
{ "vbroadcasti64x2", { XM, EXxmm }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F385B_M_0_L_2 */
|
|
{
|
|
{ "vbroadcasti32x8", { XM, EXymm }, PREFIX_DATA },
|
|
{ "vbroadcasti64x4", { XM, EXymm }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3870 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpshldvw", { XM, Vex, EXx }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3872_P_1 */
|
|
{
|
|
{ "vcvtneps2bf16%XY", { XMxmmq, EXx }, 0 },
|
|
{ Bad_Opcode },
|
|
},
|
|
/* EVEX_W_0F3872_P_2 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpshrdvw", { XM, Vex, EXx }, 0 },
|
|
},
|
|
/* EVEX_W_0F3872_P_3 */
|
|
{
|
|
{ "vcvtne2ps2bf16", { XM, Vex, EXx}, 0 },
|
|
{ Bad_Opcode },
|
|
},
|
|
/* EVEX_W_0F387A */
|
|
{
|
|
{ MOD_TABLE (MOD_EVEX_0F387A_W_0) },
|
|
},
|
|
/* EVEX_W_0F387B */
|
|
{
|
|
{ MOD_TABLE (MOD_EVEX_0F387B_W_0) },
|
|
},
|
|
/* EVEX_W_0F3883 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpmultishiftqb", { XM, Vex, EXx }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A05 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A08 */
|
|
{
|
|
{ PREFIX_TABLE (PREFIX_EVEX_0F3A08_W_0) },
|
|
},
|
|
/* EVEX_W_0F3A09 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vrndscalepd", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A0A */
|
|
{
|
|
{ PREFIX_TABLE (PREFIX_EVEX_0F3A0A_W_0) },
|
|
},
|
|
/* EVEX_W_0F3A0B */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vrndscalesd", { XMScalar, VexScalar, EXq, EXxEVexS, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A18_L_n */
|
|
{
|
|
{ "vinsertf32x4", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
|
|
{ "vinsertf64x2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A19_L_n */
|
|
{
|
|
{ "vextractf32x4", { EXxmm, XM, Ib }, PREFIX_DATA },
|
|
{ "vextractf64x2", { EXxmm, XM, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A1A_L_2 */
|
|
{
|
|
{ "vinsertf32x8", { XM, Vex, EXymm, Ib }, PREFIX_DATA },
|
|
{ "vinsertf64x4", { XM, Vex, EXymm, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A1B_L_2 */
|
|
{
|
|
{ "vextractf32x8", { EXymm, XM, Ib }, PREFIX_DATA },
|
|
{ "vextractf64x4", { EXymm, XM, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A21 */
|
|
{
|
|
{ VEX_LEN_TABLE (VEX_LEN_0F3A21) },
|
|
},
|
|
/* EVEX_W_0F3A23_L_n */
|
|
{
|
|
{ "vshuff32x4", { XM, Vex, EXx, Ib }, PREFIX_DATA },
|
|
{ "vshuff64x2", { XM, Vex, EXx, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A38_L_n */
|
|
{
|
|
{ "vinserti32x4", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
|
|
{ "vinserti64x2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A39_L_n */
|
|
{
|
|
{ "vextracti32x4", { EXxmm, XM, Ib }, PREFIX_DATA },
|
|
{ "vextracti64x2", { EXxmm, XM, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A3A_L_2 */
|
|
{
|
|
{ "vinserti32x8", { XM, Vex, EXymm, Ib }, PREFIX_DATA },
|
|
{ "vinserti64x4", { XM, Vex, EXymm, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A3B_L_2 */
|
|
{
|
|
{ "vextracti32x8", { EXymm, XM, Ib }, PREFIX_DATA },
|
|
{ "vextracti64x4", { EXymm, XM, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A42 */
|
|
{
|
|
{ "vdbpsadbw", { XM, Vex, EXx, Ib }, 0 },
|
|
},
|
|
/* EVEX_W_0F3A43_L_n */
|
|
{
|
|
{ "vshufi32x4", { XM, Vex, EXx, Ib }, PREFIX_DATA },
|
|
{ "vshufi64x2", { XM, Vex, EXx, Ib }, PREFIX_DATA },
|
|
},
|
|
/* EVEX_W_0F3A70 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpshldw", { XM, Vex, EXx, Ib }, 0 },
|
|
},
|
|
/* EVEX_W_0F3A72 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vpshrdw", { XM, Vex, EXx, Ib }, 0 },
|
|
},
|
|
/* EVEX_W_MAP5_5A */
|
|
{
|
|
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5A_W_0) },
|
|
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5A_W_1) },
|
|
},
|
|
/* EVEX_W_MAP5_5B */
|
|
{
|
|
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5B_W_0) },
|
|
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5B_W_1) },
|
|
},
|
|
/* EVEX_W_MAP5_78_P_0 */
|
|
{
|
|
{ "vcvttph2udq", { XM, EXxmmqh, EXxEVexS }, 0 },
|
|
},
|
|
/* EVEX_W_MAP5_78_P_2 */
|
|
{
|
|
{ "vcvttph2uqq", { XM, EXxmmqdh, EXxEVexS }, 0 },
|
|
},
|
|
/* EVEX_W_MAP5_79_P_0 */
|
|
{
|
|
{ "vcvtph2udq", { XM, EXxmmqh, EXxEVexR }, 0 },
|
|
},
|
|
/* EVEX_W_MAP5_79_P_2 */
|
|
{
|
|
{ "vcvtph2uqq", { XM, EXxmmqdh, EXxEVexR }, 0 },
|
|
},
|
|
/* EVEX_W_MAP5_7A_P_2 */
|
|
{
|
|
{ "vcvttph2qq", { XM, EXxmmqdh, EXxEVexS }, 0 },
|
|
},
|
|
/* EVEX_W_MAP5_7A_P_3 */
|
|
{
|
|
{ "vcvtudq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
|
|
{ "vcvtuqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
|
|
},
|
|
/* EVEX_W_MAP5_7B_P_2 */
|
|
{
|
|
{ "vcvtph2qq", { XM, EXxmmqdh, EXxEVexR }, 0 },
|
|
},
|
|
/* EVEX_W_MAP5_7C_P_0 */
|
|
{
|
|
{ "vcvttph2uw", { XM, EXxh, EXxEVexS }, 0 },
|
|
},
|
|
/* EVEX_W_MAP5_7C_P_2 */
|
|
{
|
|
{ "vcvttph2w", { XM, EXxh, EXxEVexS }, 0 },
|
|
},
|
|
/* EVEX_W_MAP5_7D */
|
|
{
|
|
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7D_W_0) },
|
|
},
|
|
/* EVEX_W_MAP6_13_P_0 */
|
|
{
|
|
{ "vcvtsh2ss", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
|
|
},
|
|
/* EVEX_W_MAP6_13_P_2 */
|
|
{
|
|
{ "vcvtph2psx", { XM, EXxmmqh, EXxEVexS }, 0 },
|
|
},
|