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b9249c461c
This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions. It also
covers 32-bit & 64-bit targets.
The unittest coverage is a bit weak atm, but should get better.
46 lines
1.2 KiB
C
46 lines
1.2 KiB
C
/* RISC-V simulator.
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Copyright (C) 2005-2021 Free Software Foundation, Inc.
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Contributed by Mike Frysinger.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef RISCV_SIM_MACHS_H
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#define RISCV_SIM_MACHS_H
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typedef enum model_type {
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#define M(ext) MODEL_RV32##ext,
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#include "model_list.def"
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#undef M
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#define M(ext) MODEL_RV64##ext,
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#include "model_list.def"
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#undef M
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#define M(ext) MODEL_RV128##ext,
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#include "model_list.def"
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#undef M
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MODEL_MAX
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} MODEL_TYPE;
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typedef enum mach_attr {
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MACH_BASE,
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MACH_RV32I,
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MACH_RV64I,
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MACH_RV128I,
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MACH_MAX
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} MACH_ATTR;
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#endif
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