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965b71a7f7
Some ravenscar runtimes implement lazy FPU handling. On these runtimes, the FPU is only initialized when a task tries to use it. Furthermore, the FP registers aren't automatically saved on a task switch -- instead, the save is deferred until the new task tries to use the FPU. Furthermore, each task's context area has a flag indicating whether the FPU has been initialized for this task. This patch teaches GDB to understand this implementation. When fetching or storing registers, GDB now checks to see whether the live FP registers should be used. If not, the task's saved FP registers will be used if the task has caused FPU initialization. Currently only AArch64 uses this code. bb-runtimes implements this for ARM as well, but GDB doesn't yet have an arm-ravenscar-thread.c.
83 lines
2.5 KiB
C
83 lines
2.5 KiB
C
/* Ravenscar Aarch64 target support.
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Copyright (C) 2017-2022 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "gdbcore.h"
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#include "regcache.h"
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#include "aarch64-tdep.h"
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#include "inferior.h"
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#include "ravenscar-thread.h"
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#include "aarch64-ravenscar-thread.h"
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#include "gdbarch.h"
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#define NO_OFFSET -1
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/* See aarch64-tdep.h for register numbers. */
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static const int aarch64_context_offsets[] =
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{
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/* X0 - X28 */
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, 0,
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8, 16, 24, 32,
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40, 48, 56, 64,
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72,
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/* FP, LR, SP, PC, CPSR */
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/* Note that as task switch is synchronous, PC is in fact the LR here */
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80, 88, 96, 88,
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NO_OFFSET,
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/* V0 - V31 */
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128, 144, 160, 176,
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192, 208, 224, 240,
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256, 272, 288, 304,
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320, 336, 352, 368,
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384, 400, 416, 432,
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448, 464, 480, 496,
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512, 528, 544, 560,
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576, 592, 608, 624,
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/* FPSR, FPCR */
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112, 116,
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};
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#define V_INIT_OFFSET 640
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/* The ravenscar_arch_ops vector for most Aarch64 targets. */
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static struct ravenscar_arch_ops aarch64_ravenscar_ops
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(aarch64_context_offsets,
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-1, -1,
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V_INIT_OFFSET,
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/* The FPU context buffer starts with the FPSR register. */
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aarch64_context_offsets[AARCH64_FPSR_REGNUM],
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AARCH64_V0_REGNUM, AARCH64_FPCR_REGNUM);
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/* Register aarch64_ravenscar_ops in GDBARCH. */
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void
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register_aarch64_ravenscar_ops (struct gdbarch *gdbarch)
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{
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set_gdbarch_ravenscar_ops (gdbarch, &aarch64_ravenscar_ops);
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}
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