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https://sourceware.org/git/binutils-gdb.git
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617126bc8a
This adds fp reg support similar to the existing general reg support. This fixes one gdb testsuite failure FAIL: gdb.base/gcore.exp: corefile restored system registers which fails without the patch because fcsr was missing. Otherwise, no regressions with riscv64-linux native testsuite run. gdb/ * riscv-linux-tdep.c (riscv_linux_fregmap): New. (riscv_linux_fregset): New. (riscv_linux_iterate_over_regset_sections): Call cb for .reg2 section.
194 lines
5.9 KiB
C
194 lines
5.9 KiB
C
/* Target-dependent code for GNU/Linux on RISC-V processors.
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Copyright (C) 2018-2019 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "riscv-tdep.h"
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#include "osabi.h"
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#include "glibc-tdep.h"
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#include "linux-tdep.h"
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#include "solib-svr4.h"
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#include "regset.h"
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#include "tramp-frame.h"
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#include "trad-frame.h"
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/* Define the general register mapping. The kernel puts the PC at offset 0,
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gdb puts it at offset 32. Register x0 is always 0 and can be ignored.
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Registers x1 to x31 are in the same place. */
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static const struct regcache_map_entry riscv_linux_gregmap[] =
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{
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{ 1, RISCV_PC_REGNUM, 0 },
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{ 31, RISCV_RA_REGNUM, 0 }, /* x1 to x31 */
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{ 0 }
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};
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/* Define the FP register mapping. The kernel puts the 32 FP regs first, and
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then FCSR. */
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static const struct regcache_map_entry riscv_linux_fregmap[] =
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{
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{ 32, RISCV_FIRST_FP_REGNUM, 0 },
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{ 1, RISCV_CSR_FCSR_REGNUM, 0 },
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{ 0 }
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};
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/* Define the general register regset. */
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static const struct regset riscv_linux_gregset =
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{
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riscv_linux_gregmap, regcache_supply_regset, regcache_collect_regset
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};
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/* Define the FP register regset. */
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static const struct regset riscv_linux_fregset =
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{
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riscv_linux_fregmap, regcache_supply_regset, regcache_collect_regset
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};
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/* Define hook for core file support. */
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static void
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riscv_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
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iterate_over_regset_sections_cb *cb,
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void *cb_data,
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const struct regcache *regcache)
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{
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cb (".reg", (32 * riscv_isa_xlen (gdbarch)), (32 * riscv_isa_xlen (gdbarch)),
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&riscv_linux_gregset, NULL, cb_data);
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/* The kernel is adding 8 bytes for FCSR. */
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cb (".reg2", (32 * riscv_isa_flen (gdbarch)) + 8,
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(32 * riscv_isa_flen (gdbarch)) + 8,
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&riscv_linux_fregset, NULL, cb_data);
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}
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/* Signal trampoline support. */
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static void riscv_linux_sigframe_init (const struct tramp_frame *self,
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struct frame_info *this_frame,
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struct trad_frame_cache *this_cache,
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CORE_ADDR func);
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#define RISCV_INST_LI_A7_SIGRETURN 0x08b00893
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#define RISCV_INST_ECALL 0x00000073
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static const struct tramp_frame riscv_linux_sigframe = {
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SIGTRAMP_FRAME,
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4,
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{
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{ RISCV_INST_LI_A7_SIGRETURN, ULONGEST_MAX },
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{ RISCV_INST_ECALL, ULONGEST_MAX },
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{ TRAMP_SENTINEL_INSN }
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},
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riscv_linux_sigframe_init,
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NULL
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};
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/* Runtime signal frames look like this:
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struct rt_sigframe {
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struct siginfo info;
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struct ucontext uc;
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};
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struct ucontext {
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unsigned long __uc_flags;
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struct ucontext *uclink;
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stack_t uc_stack;
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sigset_t uc_sigmask;
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char __glibc_reserved[1024 / 8 - sizeof (sigset_t)];
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mcontext_t uc_mcontext;
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}; */
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#define SIGFRAME_SIGINFO_SIZE 128
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#define UCONTEXT_MCONTEXT_OFFSET 176
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static void
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riscv_linux_sigframe_init (const struct tramp_frame *self,
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struct frame_info *this_frame,
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struct trad_frame_cache *this_cache,
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CORE_ADDR func)
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{
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struct gdbarch *gdbarch = get_frame_arch (this_frame);
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int xlen = riscv_isa_xlen (gdbarch);
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int flen = riscv_isa_flen (gdbarch);
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CORE_ADDR frame_sp = get_frame_sp (this_frame);
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CORE_ADDR mcontext_base;
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CORE_ADDR regs_base;
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mcontext_base = frame_sp + SIGFRAME_SIGINFO_SIZE + UCONTEXT_MCONTEXT_OFFSET;
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/* Handle the integer registers. The first one is PC, followed by x1
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through x31. */
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regs_base = mcontext_base;
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trad_frame_set_reg_addr (this_cache, RISCV_PC_REGNUM, regs_base);
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for (int i = 1; i < 32; i++)
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trad_frame_set_reg_addr (this_cache, RISCV_ZERO_REGNUM + i,
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regs_base + (i * xlen));
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/* Handle the FP registers. First comes the 32 FP registers, followed by
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fcsr. */
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regs_base += 32 * xlen;
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for (int i = 0; i < 32; i++)
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trad_frame_set_reg_addr (this_cache, RISCV_FIRST_FP_REGNUM + i,
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regs_base + (i * flen));
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regs_base += 32 * flen;
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trad_frame_set_reg_addr (this_cache, RISCV_CSR_FCSR_REGNUM, regs_base);
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/* Choice of the bottom of the sigframe is somewhat arbitrary. */
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trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
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}
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/* Initialize RISC-V Linux ABI info. */
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static void
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riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
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{
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linux_init_abi (info, gdbarch);
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set_gdbarch_software_single_step (gdbarch, riscv_software_single_step);
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set_solib_svr4_fetch_link_map_offsets (gdbarch,
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(riscv_isa_xlen (gdbarch) == 4
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? svr4_ilp32_fetch_link_map_offsets
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: svr4_lp64_fetch_link_map_offsets));
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/* GNU/Linux uses SVR4-style shared libraries. */
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set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
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/* GNU/Linux uses the dynamic linker included in the GNU C Library. */
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set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
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/* Enable TLS support. */
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set_gdbarch_fetch_tls_load_module_address (gdbarch,
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svr4_fetch_objfile_link_map);
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set_gdbarch_iterate_over_regset_sections
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(gdbarch, riscv_linux_iterate_over_regset_sections);
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tramp_frame_prepend_unwinder (gdbarch, &riscv_linux_sigframe);
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}
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/* Initialize RISC-V Linux target support. */
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void
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_initialize_riscv_linux_tdep (void)
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{
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gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_LINUX,
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riscv_linux_init_abi);
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}
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