Dimitar Dimitrov fcd5cdd5ae sim: pru: Fix emulation of carry bit ... The PRU architecture documentation [1] was used for the initial GNU simulator implementation. But recently [2] TI confirmed the carry behaviour was wrongly documented. In reality, the PRU carry behaves like the carry in ARM processors. This patch fixes simulator to align with latest recommendations from TI. The new carry.s test was also validated to pass on real hardware - a BeaglePlay board [3]. That test is a bit long because TI still has not released official updates for the PRU documents. And I wanted to ensure simulator handles all edge cases exactly as the real hardware does. [1] https://www.ti.com/lit/pdf/spruij2 [2] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1244359/sk-am64b-am64x-pru-assembler-how-works-this-bloody-carry [3] https://www.beagleboard.org/boards/beagleplay Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>		2023-12-28 09:09:13 +02:00
..
aarch64	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
arm	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
avr	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
bfin	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
bpf	sim: bpf: do not use semicolon to begin comments	2023-11-28 15:01:18 +01:00
common	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
config	sim: testsuite: rework sim_init usage	2021-11-26 19:48:05 -05:00
cr16	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
cris	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
d10v	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
example-synacor	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
frv	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
ft32	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
h8300	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
iq2000	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
lib	sim prune_warnings	2023-08-19 12:41:32 +09:30
lm32	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
m32c	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
m32r	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
m68hc11	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
mcore	Yet another fix for mcore-sim (rotli)	2023-12-18 22:04:25 -07:00
microblaze	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
mips	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
mn10300	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
moxie	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
msp430	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
or1k	sim: or1k: Eliminate dangerous RWX load segments	2023-08-24 07:03:48 +01:00
pru	sim: pru: Fix emulation of carry bit	2023-12-28 09:09:13 +02:00
riscv	sim/riscv: fix JALR instruction simulation	2023-10-18 17:55:31 +01:00
sh	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
v850	Fix for v850e divq instruction	2022-04-06 11:10:40 -04:00
.gitignore
ChangeLog-2021	sim: rename ChangeLog files to ChangeLog-2021	2021-08-17 20:27:36 -04:00
local.mk	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00