binutils-gdb/sim/example-synacor
Mike Frysinger 109a0a7e90 sim: modules.c: fix generation after recent refactors
Add explicit arch-specific modules.c rules to keep the build from
generating an incorrect common/modules.c.  Otherwise the pattern
rules would cascade such that it'd look for $arch/modules.o which
turned into common/modules.c which triggered the gen rule.

My local testing of this code didn't catch this bug because of how
Automake manages .Po (dependency files) in incremental builds -- it
was adding extra rules that override the pattern rules which caused
the build to generate correct modules.c files.  But when building
from a cold cache, the pattern rules would force common/modules.c to
be used leading to crashes at runtime.
2023-01-15 20:55:48 -05:00
..
ChangeLog-2021 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
example-synacor-sim.h Update copyright year range in header of all files managed by GDB 2023-01-01 17:01:16 +04:00
interp.c Update copyright year range in header of all files managed by GDB 2023-01-01 17:01:16 +04:00
local.mk sim: modules.c: fix generation after recent refactors 2023-01-15 20:55:48 -05:00
README
README.arch-spec
sim-main.c Update copyright year range in header of all files managed by GDB 2023-01-01 17:01:16 +04:00
sim-main.h Update copyright year range in header of all files managed by GDB 2023-01-01 17:01:16 +04:00

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.