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213516ef31
This commit is the result of running the gdb/copyright.py script, which automated the update of the copyright year range for all source files managed by the GDB project to be updated to include year 2023.
338 lines
9.5 KiB
C
338 lines
9.5 KiB
C
/* Native-dependent code for GNU/Linux RISC-V.
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Copyright (C) 2018-2023 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "regcache.h"
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#include "gregset.h"
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#include "linux-nat.h"
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#include "riscv-tdep.h"
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#include "inferior.h"
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#include "elf/common.h"
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#include "nat/riscv-linux-tdesc.h"
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#include <sys/ptrace.h>
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/* Work around glibc header breakage causing ELF_NFPREG not to be usable. */
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#ifndef NFPREG
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# define NFPREG 33
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#endif
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/* RISC-V Linux native additions to the default linux support. */
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class riscv_linux_nat_target final : public linux_nat_target
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{
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public:
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/* Add our register access methods. */
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void fetch_registers (struct regcache *regcache, int regnum) override;
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void store_registers (struct regcache *regcache, int regnum) override;
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/* Read suitable target description. */
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const struct target_desc *read_description () override;
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};
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static riscv_linux_nat_target the_riscv_linux_nat_target;
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/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1)
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from regset GREGS into REGCACHE. */
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static void
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supply_gregset_regnum (struct regcache *regcache, const prgregset_t *gregs,
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int regnum)
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{
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int i;
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const elf_greg_t *regp = *gregs;
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if (regnum == -1)
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{
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/* We only support the integer registers and PC here. */
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for (i = RISCV_ZERO_REGNUM + 1; i < RISCV_PC_REGNUM; i++)
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regcache->raw_supply (i, regp + i);
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/* GDB stores PC in reg 32. Linux kernel stores it in reg 0. */
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regcache->raw_supply (RISCV_PC_REGNUM, regp + 0);
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/* Fill the inaccessible zero register with zero. */
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regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM);
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}
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else if (regnum == RISCV_ZERO_REGNUM)
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regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM);
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else if (regnum > RISCV_ZERO_REGNUM && regnum < RISCV_PC_REGNUM)
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regcache->raw_supply (regnum, regp + regnum);
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else if (regnum == RISCV_PC_REGNUM)
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regcache->raw_supply (RISCV_PC_REGNUM, regp + 0);
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}
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/* Copy all general purpose registers from regset GREGS into REGCACHE. */
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void
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supply_gregset (struct regcache *regcache, const prgregset_t *gregs)
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{
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supply_gregset_regnum (regcache, gregs, -1);
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}
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/* Copy floating point register REGNUM (or all fp regs if REGNUM == -1)
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from regset FPREGS into REGCACHE. */
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static void
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supply_fpregset_regnum (struct regcache *regcache, const prfpregset_t *fpregs,
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int regnum)
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{
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int flen = register_size (regcache->arch (), RISCV_FIRST_FP_REGNUM);
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union
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{
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const prfpregset_t *fpregs;
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const gdb_byte *buf;
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}
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fpbuf = { .fpregs = fpregs };
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int i;
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if (regnum == -1)
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{
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/* We only support the FP registers and FCSR here. */
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for (i = RISCV_FIRST_FP_REGNUM;
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i <= RISCV_LAST_FP_REGNUM;
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i++, fpbuf.buf += flen)
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regcache->raw_supply (i, fpbuf.buf);
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regcache->raw_supply (RISCV_CSR_FCSR_REGNUM, fpbuf.buf);
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}
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else if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
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{
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fpbuf.buf += flen * (regnum - RISCV_FIRST_FP_REGNUM);
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regcache->raw_supply (regnum, fpbuf.buf);
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}
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else if (regnum == RISCV_CSR_FCSR_REGNUM)
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{
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fpbuf.buf += flen * (RISCV_LAST_FP_REGNUM - RISCV_FIRST_FP_REGNUM + 1);
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regcache->raw_supply (RISCV_CSR_FCSR_REGNUM, fpbuf.buf);
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}
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}
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/* Copy all floating point registers from regset FPREGS into REGCACHE. */
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void
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supply_fpregset (struct regcache *regcache, const prfpregset_t *fpregs)
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{
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supply_fpregset_regnum (regcache, fpregs, -1);
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}
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/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1)
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from REGCACHE into regset GREGS. */
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void
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fill_gregset (const struct regcache *regcache, prgregset_t *gregs, int regnum)
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{
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elf_greg_t *regp = *gregs;
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if (regnum == -1)
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{
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/* We only support the integer registers and PC here. */
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for (int i = RISCV_ZERO_REGNUM + 1; i < RISCV_PC_REGNUM; i++)
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regcache->raw_collect (i, regp + i);
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regcache->raw_collect (RISCV_PC_REGNUM, regp + 0);
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}
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else if (regnum == RISCV_ZERO_REGNUM)
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/* Nothing to do here. */
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;
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else if (regnum > RISCV_ZERO_REGNUM && regnum < RISCV_PC_REGNUM)
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regcache->raw_collect (regnum, regp + regnum);
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else if (regnum == RISCV_PC_REGNUM)
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regcache->raw_collect (RISCV_PC_REGNUM, regp + 0);
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}
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/* Copy floating point register REGNUM (or all fp regs if REGNUM == -1)
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from REGCACHE into regset FPREGS. */
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void
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fill_fpregset (const struct regcache *regcache, prfpregset_t *fpregs,
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int regnum)
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{
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int flen = register_size (regcache->arch (), RISCV_FIRST_FP_REGNUM);
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union
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{
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prfpregset_t *fpregs;
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gdb_byte *buf;
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}
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fpbuf = { .fpregs = fpregs };
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int i;
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if (regnum == -1)
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{
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/* We only support the FP registers and FCSR here. */
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for (i = RISCV_FIRST_FP_REGNUM;
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i <= RISCV_LAST_FP_REGNUM;
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i++, fpbuf.buf += flen)
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regcache->raw_collect (i, fpbuf.buf);
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regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, fpbuf.buf);
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}
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else if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
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{
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fpbuf.buf += flen * (regnum - RISCV_FIRST_FP_REGNUM);
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regcache->raw_collect (regnum, fpbuf.buf);
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}
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else if (regnum == RISCV_CSR_FCSR_REGNUM)
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{
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fpbuf.buf += flen * (RISCV_LAST_FP_REGNUM - RISCV_FIRST_FP_REGNUM + 1);
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regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, fpbuf.buf);
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}
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}
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/* Return a target description for the current target. */
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const struct target_desc *
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riscv_linux_nat_target::read_description ()
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{
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const struct riscv_gdbarch_features features
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= riscv_linux_read_features (inferior_ptid.pid ());
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return riscv_lookup_target_description (features);
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}
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/* Fetch REGNUM (or all registers if REGNUM == -1) from the target
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into REGCACHE using PTRACE_GETREGSET. */
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void
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riscv_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
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{
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int tid;
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tid = get_ptrace_pid (regcache->ptid());
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if ((regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_PC_REGNUM)
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|| (regnum == -1))
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{
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struct iovec iov;
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elf_gregset_t regs;
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iov.iov_base = ®s;
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iov.iov_len = sizeof (regs);
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if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS,
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(PTRACE_TYPE_ARG3) &iov) == -1)
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perror_with_name (_("Couldn't get registers"));
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else
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supply_gregset_regnum (regcache, ®s, regnum);
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}
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if ((regnum >= RISCV_FIRST_FP_REGNUM
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&& regnum <= RISCV_LAST_FP_REGNUM)
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|| (regnum == RISCV_CSR_FCSR_REGNUM)
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|| (regnum == -1))
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{
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struct iovec iov;
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elf_fpregset_t regs;
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iov.iov_base = ®s;
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iov.iov_len = ELF_NFPREG * register_size (regcache->arch (),
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RISCV_FIRST_FP_REGNUM);
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gdb_assert (iov.iov_len <= sizeof (regs));
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if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET,
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(PTRACE_TYPE_ARG3) &iov) == -1)
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perror_with_name (_("Couldn't get registers"));
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else
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supply_fpregset_regnum (regcache, ®s, regnum);
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}
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if ((regnum == RISCV_CSR_MISA_REGNUM)
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|| (regnum == -1))
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{
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/* TODO: Need to add a ptrace call for this. */
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regcache->raw_supply_zeroed (RISCV_CSR_MISA_REGNUM);
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}
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/* Access to other CSRs has potential security issues, don't support them for
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now. */
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}
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/* Store REGNUM (or all registers if REGNUM == -1) to the target
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from REGCACHE using PTRACE_SETREGSET. */
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void
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riscv_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
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{
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int tid;
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tid = get_ptrace_pid (regcache->ptid ());
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if ((regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_PC_REGNUM)
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|| (regnum == -1))
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{
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struct iovec iov;
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elf_gregset_t regs;
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iov.iov_base = ®s;
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iov.iov_len = sizeof (regs);
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if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS,
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(PTRACE_TYPE_ARG3) &iov) == -1)
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perror_with_name (_("Couldn't get registers"));
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else
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{
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fill_gregset (regcache, ®s, regnum);
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if (ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS,
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(PTRACE_TYPE_ARG3) &iov) == -1)
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perror_with_name (_("Couldn't set registers"));
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}
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}
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if ((regnum >= RISCV_FIRST_FP_REGNUM
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&& regnum <= RISCV_LAST_FP_REGNUM)
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|| (regnum == RISCV_CSR_FCSR_REGNUM)
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|| (regnum == -1))
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{
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struct iovec iov;
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elf_fpregset_t regs;
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iov.iov_base = ®s;
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iov.iov_len = ELF_NFPREG * register_size (regcache->arch (),
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RISCV_FIRST_FP_REGNUM);
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gdb_assert (iov.iov_len <= sizeof (regs));
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if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET,
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(PTRACE_TYPE_ARG3) &iov) == -1)
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perror_with_name (_("Couldn't get registers"));
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else
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{
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fill_fpregset (regcache, ®s, regnum);
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if (ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET,
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(PTRACE_TYPE_ARG3) &iov) == -1)
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perror_with_name (_("Couldn't set registers"));
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}
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}
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/* Access to CSRs has potential security issues, don't support them for
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now. */
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}
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/* Initialize RISC-V Linux native support. */
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void _initialize_riscv_linux_nat ();
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void
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_initialize_riscv_linux_nat ()
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{
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/* Register the target. */
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linux_target = &the_riscv_linux_nat_target;
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add_inf_child_target (&the_riscv_linux_nat_target);
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}
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