mirror of
https://sourceware.org/git/binutils-gdb.git
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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
370 lines
9.2 KiB
C
370 lines
9.2 KiB
C
/* OpenRISC simulator support code
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Copyright (C) 2017-2024 Free Software Foundation, Inc.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#define WANT_CPU_OR1K32BF
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#define WANT_CPU
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#include "sim-main.h"
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#include "symcat.h"
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#include "cgen-ops.h"
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#include "cgen-mem.h"
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#include "cpuall.h"
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#include <string.h>
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int
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or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, void *buf, int len)
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{
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if (rn < 32)
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SETTWI (buf, GET_H_GPR (rn));
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else
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switch (rn)
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{
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case PPC_REGNUM:
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SETTWI (buf, GET_H_SYS_PPC ());
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break;
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case PC_REGNUM:
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SETTWI (buf, GET_H_PC ());
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break;
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case SR_REGNUM:
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SETTWI (buf, GET_H_SYS_SR ());
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break;
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default:
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return 0;
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}
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return sizeof (WI); /* WI from arch.h */
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}
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int
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or1k32bf_store_register (sim_cpu *current_cpu, int rn, const void *buf, int len)
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{
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if (rn < 32)
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SET_H_GPR (rn, GETTWI (buf));
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else
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switch (rn)
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{
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case PPC_REGNUM:
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SET_H_SYS_PPC (GETTWI (buf));
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break;
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case PC_REGNUM:
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SET_H_PC (GETTWI (buf));
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break;
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case SR_REGNUM:
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SET_H_SYS_SR (GETTWI (buf));
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break;
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default:
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return 0;
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}
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return sizeof (WI); /* WI from arch.h */
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}
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int
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or1k32bf_model_or1200_u_exec (sim_cpu *current_cpu, const IDESC *idesc,
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int unit_num, int referenced)
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{
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return -1;
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}
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int
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or1k32bf_model_or1200nd_u_exec (sim_cpu *current_cpu, const IDESC *idesc,
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int unit_num, int referenced)
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{
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return -1;
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}
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void
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or1k32bf_model_insn_before (sim_cpu *current_cpu, int first_p)
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{
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}
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void
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or1k32bf_model_insn_after (sim_cpu *current_cpu, int last_p, int cycles)
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{
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}
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USI
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or1k32bf_h_spr_get_raw (sim_cpu *current_cpu, USI addr)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
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SIM_ASSERT (addr < NUM_SPR);
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return or1k_cpu->spr[addr];
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}
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void
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or1k32bf_h_spr_set_raw (sim_cpu *current_cpu, USI addr, USI val)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
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SIM_ASSERT (addr < NUM_SPR);
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or1k_cpu->spr[addr] = val;
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}
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USI
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or1k32bf_h_spr_field_get_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
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SIM_ASSERT (addr < NUM_SPR);
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return LSEXTRACTED (or1k_cpu->spr[addr], msb, lsb);
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}
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void
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or1k32bf_h_spr_field_set_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb,
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USI val)
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{
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struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
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or1k_cpu->spr[addr] &= ~LSMASK32 (msb, lsb);
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or1k_cpu->spr[addr] |= LSINSERTED (val, msb, lsb);
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}
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/* Initialize a sim cpu object. */
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void
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or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
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const USI or1k_upr, const USI or1k_cpucfgr)
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{
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struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
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/* Set the configuration registers passed from the user. */
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SET_H_SYS_VR (or1k_vr);
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SET_H_SYS_UPR (or1k_upr);
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SET_H_SYS_CPUCFGR (or1k_cpucfgr);
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#define CHECK_SPR_FIELD(GROUP, INDEX, FIELD, test) \
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do \
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{ \
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USI field = GET_H_##SYS##_##INDEX##_##FIELD (); \
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if (!(test)) \
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sim_io_eprintf \
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(sd, "WARNING: unsupported %s field in %s register: 0x%x\n", \
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#FIELD, #INDEX, field); \
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} while (0)
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/* Set flags indicating if we are in a delay slot or not. */
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or1k_cpu->next_delay_slot = 0;
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or1k_cpu->delay_slot = 0;
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/* Verify any user passed fields and warn on configurations we don't
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support. */
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CHECK_SPR_FIELD (SYS, UPR, UP, field == 1);
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CHECK_SPR_FIELD (SYS, UPR, DCP, field == 0);
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CHECK_SPR_FIELD (SYS, UPR, ICP, field == 0);
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CHECK_SPR_FIELD (SYS, UPR, DMP, field == 0);
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CHECK_SPR_FIELD (SYS, UPR, MP, field == 0);
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CHECK_SPR_FIELD (SYS, UPR, IMP, field == 0);
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CHECK_SPR_FIELD (SYS, UPR, DUP, field == 0);
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CHECK_SPR_FIELD (SYS, UPR, PCUP, field == 0);
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CHECK_SPR_FIELD (SYS, UPR, PICP, field == 0);
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CHECK_SPR_FIELD (SYS, UPR, PMP, field == 0);
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CHECK_SPR_FIELD (SYS, UPR, TTP, field == 0);
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CHECK_SPR_FIELD (SYS, UPR, CUP, field == 0);
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CHECK_SPR_FIELD (SYS, CPUCFGR, NSGR, field == 0);
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CHECK_SPR_FIELD (SYS, CPUCFGR, CGF, field == 0);
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CHECK_SPR_FIELD (SYS, CPUCFGR, OB32S, field == 1);
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CHECK_SPR_FIELD (SYS, CPUCFGR, OF32S, field == 1);
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CHECK_SPR_FIELD (SYS, CPUCFGR, OB64S, field == 0);
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CHECK_SPR_FIELD (SYS, CPUCFGR, OF64S, field == 0);
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CHECK_SPR_FIELD (SYS, CPUCFGR, OV64S, field == 0);
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#undef CHECK_SPR_FIELD
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/* Configure the fpu operations and mark fpu available. */
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cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu),
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or1k32bf_fpu_error);
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SET_H_SYS_CPUCFGR_OF32S (1);
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/* Set the UPR[UP] flag, even if the user tried to unset it, as we always
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support the Unit Present Register. */
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SET_H_SYS_UPR_UP (1);
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/* Set the supervisor register to indicate we are in supervisor mode and
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set the Fixed-One bit which must always be set. */
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SET_H_SYS_SR (SPR_FIELD_MASK_SYS_SR_SM | SPR_FIELD_MASK_SYS_SR_FO);
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/* Clear the floating point control status register. */
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SET_H_SYS_FPCSR (0);
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}
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void
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or1k32bf_insn_before (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
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or1k_cpu->delay_slot = or1k_cpu->next_delay_slot;
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or1k_cpu->next_delay_slot = 0;
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if (or1k_cpu->delay_slot &&
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CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) &
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CGEN_ATTR_MASK (CGEN_INSN_NOT_IN_DELAY_SLOT))
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{
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USI pc;
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#ifdef WITH_SCACHE
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pc = vpc->argbuf.addr;
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#else
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pc = vpc;
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#endif
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sim_io_error (sd, "invalid instruction in a delay slot at PC 0x%08x",
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pc);
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}
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}
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void
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or1k32bf_insn_after (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
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USI ppc;
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#ifdef WITH_SCACHE
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ppc = vpc->argbuf.addr;
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#else
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ppc = vpc;
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#endif
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SET_H_SYS_PPC (ppc);
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if (!GET_H_SYS_CPUCFGR_ND () &&
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CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) &
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CGEN_ATTR_MASK (CGEN_INSN_DELAYED_CTI))
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{
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SIM_ASSERT (!or1k_cpu->delay_slot);
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or1k_cpu->next_delay_slot = 1;
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}
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}
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void
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or1k32bf_nop (sim_cpu *current_cpu, USI uimm16)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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switch (uimm16)
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{
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case NOP_NOP:
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break;
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case NOP_EXIT:
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sim_io_printf (CPU_STATE (current_cpu), "exit(%d)\n", GET_H_GPR (3));
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ATTRIBUTE_FALLTHROUGH;
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case NOP_EXIT_SILENT:
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sim_engine_halt (sd, current_cpu, NULL, CPU_PC_GET (current_cpu),
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sim_exited, GET_H_GPR (3));
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break;
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case NOP_REPORT:
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sim_io_printf (CPU_STATE (current_cpu), "report(0x%08x);\n",
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GET_H_GPR (3));
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break;
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case NOP_PUTC:
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sim_io_printf (CPU_STATE (current_cpu), "%c",
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(char) (GET_H_GPR (3) & 0xff));
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break;
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default:
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sim_io_eprintf (sd, "WARNING: l.nop with unsupported code 0x%08x\n",
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uimm16);
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break;
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}
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}
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/* Build an address value used for load and store instructions. For example,
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the instruction 'l.lws rD, I(rA)' will require to load data from the 4 byte
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address represented by rA + I. Here the argument base is rA, offset is I
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and the size is the read size in bytes. Note, OpenRISC requires that word
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and half-word access be word and half-word aligned respectively, the check
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for alignment is not needed here. */
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USI
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or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset,
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int size)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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USI addr = base + offset;
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/* If little endian load/store is enabled we adjust the byte and half-word
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addresses to the little endian equivalent. */
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if (GET_H_SYS_SR_LEE ())
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{
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switch (size)
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{
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case 4: /* We are retrieving the entire word no adjustment. */
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break;
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case 2: /* Perform half-word adjustment 0 -> 2, 2 -> 0. */
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addr ^= 0x2;
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break;
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case 1: /* Perform byte adjustment, 0 -> 3, 2 -> 3, etc. */
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addr ^= 0x3;
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break;
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default:
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SIM_ASSERT (0);
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return 0;
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}
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}
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return addr;
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}
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/* The find first 1 instruction returns the location of the first set bit
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in the argument register. */
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USI
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or1k32bf_ff1 (sim_cpu *current_cpu, USI val)
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{
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USI bit;
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USI ret;
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for (bit = 1, ret = 1; bit; bit <<= 1, ret++)
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{
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if (val & bit)
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return ret;
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}
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return 0;
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}
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/* The find last 1 instruction returns the location of the last set bit in
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the argument register. */
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USI
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or1k32bf_fl1 (sim_cpu *current_cpu, USI val)
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{
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USI bit;
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USI ret;
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for (bit = 1 << 31, ret = 32; bit; bit >>= 1, ret--)
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{
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if (val & bit)
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return ret;
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}
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return 0;
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}
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