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binutils-gdb/sim
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John Baldwin 2694bce941 sim erc32: Add include path for readline. 
Add a READLINE_CFLAGS variable which adds the include path to the
in-tree readline when using the in-tree readline library.

sim/erc32/ChangeLog:

	* Makefile.in (READLINE_SRC, READLINE_CFLAGS): Add.
	(SIM_EXTRA_CFLAGS): Add READLINE_CFLAGS.
	* configure: Rebuild.
	* configure.ac (READLINE_CFLAGS): Add.
2021-04-15 16:07:46 -07:00
..
aarch64 sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
arm sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
avr sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
bfin sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
bpf sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
common sim: Add SIM_EXTRA_CFLAGS after CSEARCH. 2021-04-15 16:04:55 -07:00
cr16 sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
cris sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
d10v sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
erc32 sim erc32: Add include path for readline. 2021-04-15 16:07:46 -07:00
example-synacor sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
frv sim frv: Add a missing return value for frvbf_check_acc_range. 2021-04-15 16:05:41 -07:00
ft32 sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
h8300 sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
igen sim: igen: merge build into top level 2021-04-02 23:35:47 -04:00
iq2000 sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
lm32 sim lm32: Use a known-good shell with genmloop.sh. 2021-04-15 16:06:10 -07:00
m4 sim: unify toolchain settings 2021-04-02 23:31:14 -04:00
m32c sim: set ASAN_OPTIONS=detect_leaks=0 when running igen and opc2c 2021-04-08 09:49:30 -04:00
m32r sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
m68hc11 sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
mcore sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
microblaze sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
mips sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
mn10300 sim mn10300: Fix igen generation. 2021-04-15 16:06:39 -07:00
moxie sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
msp430 sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
or1k sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
ppc Add system includes in sim 2021-04-08 14:34:42 -06:00
pru sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
riscv sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
rl78 sim: unify toolchain settings 2021-04-02 23:31:14 -04:00
rx Add missing ChangeLog entry for sim/rx change. 2021-04-09 11:39:00 -03:00
sh sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
testsuite sim: testsuite: support exit 77 for unsupported tests 2021-04-08 00:48:54 -04:00
v850 sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code 2021-04-12 00:14:32 -04:00
.gitignore sim: drop common/cconfig.h in favor of a single config.h 2016-01-09 03:52:30 -05:00
aclocal.m4 sim: unify toolchain settings 2021-04-02 23:31:14 -04:00
ChangeLog sim: example-synacor: a simple implementation for reference 2021-04-03 16:19:16 -04:00
configure sim: example-synacor: a simple implementation for reference 2021-04-03 16:19:16 -04:00
configure.ac sim: example-synacor: a simple implementation for reference 2021-04-03 16:19:16 -04:00
MAINTAINERS sim: readd myself as a maintainer 2021-01-29 22:11:45 -05:00
Makefile.am sim: testsuite: integrate common tests into build 2021-04-03 15:34:13 -04:00
Makefile.in sim: testsuite: integrate common tests into build 2021-04-03 15:34:13 -04:00
README-HACKING sim: delete unused SIM_EXTRA_LIBDEPS 2021-02-28 01:39:02 -05:00