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403 lines
10 KiB
C
403 lines
10 KiB
C
/* Main simulator entry points for the M32R.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sim-main.h"
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#ifdef HAVE_STDLIB_H
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#include <stdlib.h>
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#endif
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#include "sim-options.h"
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#include "libiberty.h"
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#include "bfd.h"
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static void free_state (SIM_DESC);
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static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose);
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/* Records simulator descriptor so utilities like m32r_dump_regs can be
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called from gdb. */
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SIM_DESC current_state;
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/* Cover function of sim_state_free to free the cpu buffers as well. */
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static void
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free_state (SIM_DESC sd)
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{
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if (STATE_MODULES (sd) != NULL)
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sim_module_uninstall (sd);
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sim_cpu_free_all (sd);
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sim_state_free (sd);
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}
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/* Create an instance of the simulator. */
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SIM_DESC
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sim_open (kind, callback, abfd, argv)
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SIM_OPEN_KIND kind;
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host_callback *callback;
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struct _bfd *abfd;
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char **argv;
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{
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SIM_DESC sd = sim_state_alloc (kind, callback);
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/* The cpu data is kept in a separately allocated chunk of memory. */
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if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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#if 0 /* FIXME: pc is in mach-specific struct */
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/* FIXME: watchpoints code shouldn't need this */
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{
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SIM_CPU *current_cpu = STATE_CPU (sd, 0);
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STATE_WATCHPOINTS (sd)->pc = &(PC);
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STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
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}
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#endif
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if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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#if 0 /* FIXME: 'twould be nice if we could do this */
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/* These options override any module options.
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Obviously ambiguity should be avoided, however the caller may wish to
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augment the meaning of an option. */
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if (extra_options != NULL)
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sim_add_option_table (sd, extra_options);
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#endif
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/* Allocate core managed memory */
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sim_do_commandf (sd, "memory region 0,0x%lx", M32R_DEFAULT_MEM_SIZE);
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/* Allocate a handler for the control registers and other devices.
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All are allocated in one chunk to keep things from being
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unnecessarily complicated. */
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sim_core_attach (sd, NULL,
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0 /*level*/,
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access_read_write,
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0 /*space ???*/,
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M32R_DEVICE_ADDR, M32R_DEVICE_LEN /*nr_bytes*/,
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0 /*modulo*/,
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&m32r_devices,
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NULL /*buffer*/);
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/* getopt will print the error message so we just have to exit if this fails.
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FIXME: Hmmm... in the case of gdb we need getopt to call
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print_filtered. */
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if (sim_parse_args (sd, argv) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* check for/establish the reference program image */
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if (sim_analyze_program (sd,
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(STATE_PROG_ARGV (sd) != NULL
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? *STATE_PROG_ARGV (sd)
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: NULL),
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abfd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* If both cpu model and state architecture are set, ensure they're
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compatible. If only one is set, set the other. If neither are set,
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use the default model. STATE_ARCHITECTURE is the bfd_arch_info data
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for the selected "mach" (bfd terminology). */
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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if (! STATE_ARCHITECTURE (sd)
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/* Only check cpu 0. STATE_ARCHITECTURE is for that one only. */
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&& ! CPU_MACH (cpu))
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{
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/* Set the default model. */
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const MODEL *model = sim_model_lookup (WITH_DEFAULT_MODEL);
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sim_model_set (sd, NULL, model);
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}
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if (STATE_ARCHITECTURE (sd)
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&& CPU_MACH (cpu))
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{
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if (strcmp (STATE_ARCHITECTURE (sd)->printable_name,
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MACH_NAME (CPU_MACH (cpu))) != 0)
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{
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sim_io_eprintf (sd, "invalid model `%s' for `%s'\n",
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MODEL_NAME (CPU_MODEL (cpu)),
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STATE_ARCHITECTURE (sd)->printable_name);
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free_state (sd);
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return 0;
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}
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}
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else if (STATE_ARCHITECTURE (sd))
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{
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/* Use the default model for the selected machine.
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The default model is the first one in the list. */
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const MACH *mach = sim_mach_lookup (STATE_ARCHITECTURE (sd)->printable_name);
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sim_model_set (sd, NULL, MACH_MODELS (mach));
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}
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else
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{
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STATE_ARCHITECTURE (sd) = bfd_scan_arch (MACH_NAME (CPU_MACH (cpu)));
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}
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}
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/* Establish any remaining configuration options. */
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if (sim_config (sd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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if (sim_post_argv_init (sd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Initialize various cgen things not done by common framework. */
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cgen_init (sd);
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/* Open a copy of the opcode table. */
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STATE_OPCODE_TABLE (sd) = m32r_cgen_opcode_open (STATE_ARCHITECTURE (sd)->mach,
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CGEN_ENDIAN_BIG);
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m32r_cgen_init_dis (STATE_OPCODE_TABLE (sd));
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{
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int c;
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for (c = 0; c < MAX_NR_PROCESSORS; ++c)
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{
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/* Only needed for profiling, but the structure member is small. */
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memset (& CPU_M32R_MISC_PROFILE (STATE_CPU (sd, c)), 0,
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sizeof (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, c))));
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/* Hook in callback for reporting these stats */
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PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, c)))
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= print_m32r_misc_cpu;
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}
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}
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/* Store in a global so things like sparc32_dump_regs can be invoked
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from the gdb command line. */
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current_state = sd;
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return sd;
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}
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void
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sim_close (sd, quitting)
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SIM_DESC sd;
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int quitting;
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{
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m32r_cgen_opcode_close (STATE_OPCODE_TABLE (sd));
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sim_module_uninstall (sd);
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}
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SIM_RC
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sim_create_inferior (sd, abfd, argv, envp)
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SIM_DESC sd;
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struct _bfd *abfd;
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char **argv;
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char **envp;
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{
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SIM_CPU *current_cpu = STATE_CPU (sd, 0);
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SIM_ADDR addr;
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if (abfd != NULL)
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addr = bfd_get_start_address (abfd);
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else
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addr = 0;
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sim_pc_set (current_cpu, addr);
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#if 0
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STATE_ARGV (sd) = sim_copy_argv (argv);
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STATE_ENVP (sd) = sim_copy_argv (envp);
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#endif
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return SIM_RC_OK;
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}
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int
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sim_stop (SIM_DESC sd)
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{
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switch (STATE_ARCHITECTURE (sd)->mach)
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{
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case bfd_mach_m32r :
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return m32r_engine_stop (sd, NULL, NULL_CIA, sim_stopped, SIM_SIGINT);
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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return m32rx_engine_stop (sd, NULL, NULL_CIA, sim_stopped, SIM_SIGINT);
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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}
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/* This isn't part of the official interface.
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This is just a good place to put this for now. */
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void
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sim_sync_stop (SIM_DESC sd, SIM_CPU *cpu, PCADDR pc, enum sim_stop reason, int sigrc)
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{
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switch (STATE_ARCHITECTURE (sd)->mach)
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{
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case bfd_mach_m32r :
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(void) m32r_engine_stop (sd, cpu, pc, reason, sigrc);
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break;
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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(void) m32rx_engine_stop (sd, cpu, pc, reason, sigrc);
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break;
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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}
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void
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sim_resume (sd, step, siggnal)
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SIM_DESC sd;
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int step, siggnal;
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{
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sim_module_resume (sd);
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switch (STATE_ARCHITECTURE (sd)->mach)
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{
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case bfd_mach_m32r :
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m32r_engine_run (sd, step, siggnal);
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break;
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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m32rx_engine_run (sd, step, siggnal);
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break;
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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sim_module_suspend (sd);
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}
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/* PROFILE_CPU_CALLBACK */
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static void
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print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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char buf[20];
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if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX])
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{
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sim_io_printf (sd, "Miscellaneous Statistics\n\n");
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sim_io_printf (sd, " %-*s %s\n\n",
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PROFILE_LABEL_WIDTH, "Fill nops:",
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sim_add_commas (buf, sizeof (buf),
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CPU_M32R_MISC_PROFILE (cpu).fillnop_count));
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if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx)
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sim_io_printf (sd, " %-*s %s\n\n",
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PROFILE_LABEL_WIDTH, "Parallel insns:",
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sim_add_commas (buf, sizeof (buf),
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CPU_M32R_MISC_PROFILE (cpu).parallel_count));
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}
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}
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/* The contents of BUF are in target byte order. */
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int
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sim_fetch_register (sd, rn, buf, length)
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SIM_DESC sd;
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int rn;
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unsigned char *buf;
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int length;
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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return (* CPU_REG_FETCH (cpu)) (cpu, rn, buf, length);
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}
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/* The contents of BUF are in target byte order. */
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int
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sim_store_register (sd, rn, buf, length)
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SIM_DESC sd;
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int rn;
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unsigned char *buf;
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int length;
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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return (* CPU_REG_STORE (cpu)) (cpu, rn, buf, length);
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}
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void
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sim_do_command (sd, cmd)
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SIM_DESC sd;
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char *cmd;
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{
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if (sim_args_command (sd, cmd) != SIM_RC_OK)
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sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
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}
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/* Utility fns to access registers, without knowing the current mach. */
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SI
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h_gr_get (SIM_CPU *current_cpu, UINT regno)
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{
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switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
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{
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case bfd_mach_m32r :
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return m32r_h_gr_get (current_cpu, regno);
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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return m32rx_h_gr_get (current_cpu, regno);
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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}
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void
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h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
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{
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switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
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{
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case bfd_mach_m32r :
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m32r_h_gr_set (current_cpu, regno, newval);
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break;
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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m32rx_h_gr_set (current_cpu, regno, newval);
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break;
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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}
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