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b8a9943dd4
(extract.o): Pass -DSCACHE_P.
* mloop.in (extract{16,32}): Update call to m32r_decode.
* arch.h,cpu.h,cpuall.h,decode.[ch]: Regenerate.
* extract.c,model.c,sem-switch.c,sem.c: Regenerate.
* sim-main.h: #include "ansidecl.h".
Don't include cpu-opc.h, done by arch.h.
start-sanitize-m32rx
* Makefile.in (M32RX_OBJS): Build m32rx support now.
(m32rx.o): New rule.
* m32r-sim.h (m32rx_h_cr_[gs]et): Define.
* m32rx.c (m32rx_{fetch,store}_register): Update {get,set} of PC.
(m32rx_h_accums_get): New function.
* mloopx.in: Update call to m32rx_decode. Rewrite exec loop.
* cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
end-sanitize-m32rx
113 lines
3.3 KiB
C
113 lines
3.3 KiB
C
/* m32rx simulator support code
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Copyright (C) 1997, 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#define WANT_CPU
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#define WANT_CPU_M32RX
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#include "sim-main.h"
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#include <signal.h>
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#include "libiberty.h"
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#include "bfd.h"
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/* FIXME: need to provide general mechanism for accessing target files
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these. For now this is a hack to avoid getting the host version. */
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#include "../../libgloss/m32r/sys/syscall.h"
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#include "targ-vals.h"
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/* The contents of BUF are in target byte order. */
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void
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m32rx_fetch_register (sd, rn, buf)
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SIM_DESC sd;
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int rn;
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unsigned char *buf;
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{
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SIM_CPU *current_cpu = STATE_CPU (sd, 0);
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if (rn < 16)
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SETTWI (buf, GET_H_GR (rn));
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else if (rn < 21)
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SETTWI (buf, GET_H_CR (rn - 16));
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else switch (rn) {
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case PC_REGNUM:
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SETTWI (buf, GET_H_PC ());
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break;
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case ACCL_REGNUM:
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SETTWI (buf, GETLODI (GET_H_ACCUM ()));
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break;
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case ACCH_REGNUM:
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SETTWI (buf, GETHIDI (GET_H_ACCUM ()));
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break;
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#if 0
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case 23: *reg = STATE_CPU_CPU (sd, 0)->h_cond; break;
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case 24: *reg = STATE_CPU_CPU (sd, 0)->h_sm; break;
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case 25: *reg = STATE_CPU_CPU (sd, 0)->h_bsm; break;
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case 26: *reg = STATE_CPU_CPU (sd, 0)->h_ie; break;
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case 27: *reg = STATE_CPU_CPU (sd, 0)->h_bie; break;
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case 28: *reg = STATE_CPU_CPU (sd, 0)->h_bcarry; break; /* rename: bc */
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case 29: memcpy (buf, &STATE_CPU_CPU (sd, 0)->h_bpc, sizeof(WI)); break; /* duplicate */
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#endif
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default: abort ();
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}
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}
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/* The contents of BUF are in target byte order. */
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void
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m32rx_store_register (sd, rn, buf)
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SIM_DESC sd;
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int rn;
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unsigned char *buf;
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{
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SIM_CPU *current_cpu = STATE_CPU (sd, 0);
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if (rn < 16)
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SET_H_GR (rn, GETTWI (buf));
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else if (rn < 21)
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SET_H_CR (rn - 16, GETTWI (buf));
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else switch (rn) {
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case PC_REGNUM:
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SET_H_PC (GETTWI (buf));
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break;
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case ACCL_REGNUM:
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SETLODI (CPU (h_accum), GETTWI (buf));
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break;
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case ACCH_REGNUM:
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SETHIDI (CPU (h_accum), GETTWI (buf));
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break;
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#if 0
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case 23: STATE_CPU_CPU (sd, 0)->h_cond = *reg; break;
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case 24: STATE_CPU_CPU (sd, 0)->h_sm = *reg; break;
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case 25: STATE_CPU_CPU (sd, 0)->h_bsm = *reg; break;
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case 26: STATE_CPU_CPU (sd, 0)->h_ie = *reg; break;
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case 27: STATE_CPU_CPU (sd, 0)->h_bie = *reg; break;
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case 28: STATE_CPU_CPU (sd, 0)->h_bcarry = *reg; break; /* rename: bc */
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case 29: memcpy (&STATE_CPU_CPU (sd, 0)->h_bpc, buf, sizeof(DI)); break; /* duplicate */
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#endif
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}
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}
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/* Cover fn to access h-accums. */
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UDI
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m32rx_h_accums_get (SIM_CPU *current_cpu, UINT accum)
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{
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return 0;
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}
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