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4eb6f89250
gas * config/tc-arc.c (parse_opcode_flags): New function. (find_opcode_match): Move flag parsing code out to new function. Ignore operands marked IGNORE. (build_fake_opcode_hash_entry): New function. (find_special_case_long_opcode): New function. (find_special_case): Lookup long opcodes. * testsuite/gas/arc/nps400-7.d: New file. * testsuite/gas/arc/nps400-7.s: New file. include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16. (struct arc_long_opcode): New structure. (arc_long_opcodes): Declare. (arc_num_long_opcodes): Declare. opcodes * arc-dis.c (struct arc_operand_iterator): New structure. (find_format_from_table): All the old content from find_format, with some minor adjustments, and parameter renaming. (find_format_long_instructions): New function. (find_format): Rewritten. (arc_insn_length): Add LSB parameter. (extract_operand_value): New function. (operand_iterator_next): New function. (print_insn_arc): Use new functions to find opcode, and iterator over operands. * arc-opc.c (insert_nps_3bit_dst_short): New function. (extract_nps_3bit_dst_short): New function. (insert_nps_3bit_src2_short): New function. (extract_nps_3bit_src2_short): New function. (insert_nps_bitop1_size): New function. (extract_nps_bitop1_size): New function. (insert_nps_bitop2_size): New function. (extract_nps_bitop2_size): New function. (insert_nps_bitop_mod4_msb): New function. (extract_nps_bitop_mod4_msb): New function. (insert_nps_bitop_mod4_lsb): New function. (extract_nps_bitop_mod4_lsb): New function. (insert_nps_bitop_dst_pos3_pos4): New function. (extract_nps_bitop_dst_pos3_pos4): New function. (insert_nps_bitop_ins_ext): New function. (extract_nps_bitop_ins_ext): New function. (arc_operands): Add new operands. (arc_long_opcodes): New global array. (arc_num_long_opcodes): New global. * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1049 lines
27 KiB
C
1049 lines
27 KiB
C
/* Instruction printing code for the ARC.
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Copyright (C) 1994-2016 Free Software Foundation, Inc.
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Contributed by Claudiu Zissulescu (claziss@synopsys.com)
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include <assert.h>
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#include "dis-asm.h"
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#include "opcode/arc.h"
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#include "arc-dis.h"
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#include "arc-ext.h"
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/* Structure used to iterate over, and extract the values for, operands of
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an opcode. */
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struct arc_operand_iterator
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{
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enum
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{
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OPERAND_ITERATOR_STANDARD,
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OPERAND_ITERATOR_LONG
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} mode;
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/* The array of 32-bit values that make up this instruction. All
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required values have been pre-loaded into this array during the
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find_format call. */
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unsigned *insn;
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union
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{
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struct
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{
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/* The opcode this iterator is operating on. */
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const struct arc_opcode *opcode;
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/* The index into the opcodes operand index list. */
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const unsigned char *opidx;
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} standard;
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struct
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{
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/* The long instruction opcode this iterator is operating on. */
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const struct arc_long_opcode *long_opcode;
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/* Two indexes into the opcodes operand index lists. */
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const unsigned char *opidx_base, *opidx_limm;
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} long_insn;
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} state;
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};
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/* Globals variables. */
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static const char * const regnames[64] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
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"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
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"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
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"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
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"r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
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};
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/* Macros section. */
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#ifdef DEBUG
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# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
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#else
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# define pr_debug(fmt, args...)
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#endif
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#define ARRANGE_ENDIAN(info, buf) \
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(info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \
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: bfd_getb32 (buf))
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#define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \
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(s + (sizeof (word) * 8 - 1 - e)))
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#define OPCODE(word) (BITS ((word), 27, 31))
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#define OPCODE_AC(word) (BITS ((word), 11, 15))
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/* Functions implementation. */
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static bfd_vma
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bfd_getm32 (unsigned int data)
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{
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bfd_vma value = 0;
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value = ((data & 0xff00) | (data & 0xff)) << 16;
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value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
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return value;
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}
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static int
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special_flag_p (const char *opname,
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const char *flgname)
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{
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const struct arc_flag_special *flg_spec;
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unsigned i, j, flgidx;
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for (i = 0; i < arc_num_flag_special; i++)
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{
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flg_spec = &arc_flag_special_cases[i];
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if (strcmp (opname, flg_spec->name))
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continue;
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/* Found potential special case instruction. */
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for (j=0;; ++j)
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{
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flgidx = flg_spec->flags[j];
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if (flgidx == 0)
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break; /* End of the array. */
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if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0)
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return 1;
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}
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}
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return 0;
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}
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/* Find opcode from ARC_TABLE given the instruction described by INSN and
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INSNLEN. The ISA_MASK restricts the possible matches in ARC_TABLE. */
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static const struct arc_opcode *
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find_format_from_table (const struct arc_opcode *arc_table,
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unsigned *insn, unsigned int insn_len,
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unsigned isa_mask, bfd_boolean *has_limm)
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{
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unsigned int i = 0;
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const struct arc_opcode *opcode = NULL;
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const unsigned char *opidx;
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const unsigned char *flgidx;
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do {
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bfd_boolean invalid = FALSE;
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opcode = &arc_table[i++];
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if (ARC_SHORT (opcode->mask) && (insn_len == 2))
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{
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if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
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continue;
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}
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else if (!ARC_SHORT (opcode->mask) && (insn_len == 4))
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{
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if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
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continue;
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}
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else
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continue;
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if ((insn[0] ^ opcode->opcode) & opcode->mask)
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continue;
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if (!(opcode->cpu & isa_mask))
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continue;
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*has_limm = FALSE;
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/* Possible candidate, check the operands. */
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for (opidx = opcode->operands; *opidx; opidx++)
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{
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int value;
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const struct arc_operand *operand = &arc_operands[*opidx];
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if (operand->flags & ARC_OPERAND_FAKE)
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continue;
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if (operand->extract)
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value = (*operand->extract) (insn[0], &invalid);
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else
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value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
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/* Check for LIMM indicator. If it is there, then make sure
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we pick the right format. */
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if (operand->flags & ARC_OPERAND_IR
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&& !(operand->flags & ARC_OPERAND_LIMM))
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{
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if ((value == 0x3E && insn_len == 4)
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|| (value == 0x1E && insn_len == 2))
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{
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invalid = TRUE;
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break;
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}
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}
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if (operand->flags & ARC_OPERAND_LIMM
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&& !(operand->flags & ARC_OPERAND_DUPLICATE))
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*has_limm = TRUE;
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}
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/* Check the flags. */
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for (flgidx = opcode->flags; *flgidx; flgidx++)
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{
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/* Get a valid flag class. */
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const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
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const unsigned *flgopridx;
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int foundA = 0, foundB = 0;
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unsigned int value;
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/* Check first the extensions. */
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if (cl_flags->flag_class & F_CLASS_EXTEND)
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{
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value = (insn[0] & 0x1F);
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if (arcExtMap_condCodeName (value))
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continue;
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}
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for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
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{
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const struct arc_flag_operand *flg_operand =
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&arc_flag_operands[*flgopridx];
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value = (insn[0] >> flg_operand->shift)
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& ((1 << flg_operand->bits) - 1);
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if (value == flg_operand->code)
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foundA = 1;
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if (value)
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foundB = 1;
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}
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if (!foundA && foundB)
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{
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invalid = TRUE;
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break;
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}
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}
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if (invalid)
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continue;
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/* The instruction is valid. */
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return opcode;
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} while (opcode->mask);
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return NULL;
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}
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/* Find long instructions matching values in INSN array. */
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static const struct arc_long_opcode *
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find_format_long_instructions (unsigned *insn,
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unsigned int *insn_len,
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unsigned isa_mask,
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bfd_vma memaddr,
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struct disassemble_info *info)
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{
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unsigned int i;
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unsigned limm = 0;
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bfd_boolean limm_loaded = FALSE;
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for (i = 0; i < arc_num_long_opcodes; ++i)
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{
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bfd_byte buffer[4];
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int status;
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const struct arc_opcode *opcode;
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opcode = &arc_long_opcodes[i].base_opcode;
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if (ARC_SHORT (opcode->mask) && (*insn_len == 2))
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{
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if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
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continue;
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}
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else if (!ARC_SHORT (opcode->mask) && (*insn_len == 4))
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{
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if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
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continue;
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}
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else
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continue;
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if ((insn[0] ^ opcode->opcode) & opcode->mask)
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continue;
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if (!(opcode->cpu & isa_mask))
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continue;
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if (!limm_loaded)
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{
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status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
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4, info);
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if (status != 0)
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return NULL;
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limm = ARRANGE_ENDIAN (info, buffer);
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limm_loaded = TRUE;
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}
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/* Check the second word using the mask and template. */
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if ((limm & arc_long_opcodes[i].limm_mask)
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!= arc_long_opcodes[i].limm_template)
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continue;
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(*insn_len) += 4;
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insn[1] = limm;
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return &arc_long_opcodes[i];
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}
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return NULL;
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}
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/* Find opcode for INSN, trying various different sources. The instruction
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length in INSN_LEN will be updated if the instruction requires a LIMM
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extension, and the additional values loaded into the INSN array (which
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must be big enough).
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A pointer to the opcode is placed into OPCODE_RESULT, and ITER is
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initialised, ready to iterate over the operands of the found opcode.
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This function returns TRUE in almost all cases, FALSE is reserved to
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indicate an error (failing to find an opcode is not an error) a
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returned result of FALSE would indicate that the disassembler can't
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continue.
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If no matching opcode is found then the returned result will be TRUE,
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the value placed into OPCODE_RESULT will be NULL, ITER will be
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undefined, and INSN_LEN will be unchanged.
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If a matching opcode is found, then the returned result will be TRUE,
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the opcode pointer is placed into OPCODE_RESULT, INSN_LEN will be
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increased by 4 if the instruction requires a LIMM, and the LIMM value
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will have been loaded into the INSN[1]. Finally, ITER will have been
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initialised so that calls to OPERAND_ITERATOR_NEXT will iterate over
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the opcode's operands. */
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static bfd_boolean
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find_format (bfd_vma memaddr, unsigned *insn, unsigned int *insn_len,
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unsigned isa_mask, struct disassemble_info *info,
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const struct arc_opcode **opcode_result,
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struct arc_operand_iterator *iter)
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{
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const struct arc_opcode *opcode;
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bfd_boolean needs_limm;
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/* Find the first match in the opcode table. */
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opcode = find_format_from_table (arc_opcodes, insn, *insn_len,
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isa_mask, &needs_limm);
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if (opcode == NULL)
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{
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const extInstruction_t *einsn;
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/* No instruction found. Try the extensions. */
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einsn = arcExtMap_insn (OPCODE (insn[0]), insn[0]);
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if (einsn != NULL)
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{
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const char *errmsg = NULL;
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opcode = arcExtMap_genOpcode (einsn, isa_mask, &errmsg);
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if (opcode == NULL)
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{
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(*info->fprintf_func) (info->stream,
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"An error occured while "
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"generating the extension instruction "
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"operations");
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*opcode_result = NULL;
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return FALSE;
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}
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opcode = find_format_from_table (opcode, insn, *insn_len,
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isa_mask, &needs_limm);
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assert (opcode != NULL);
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}
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}
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if (needs_limm && opcode != NULL)
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{
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bfd_byte buffer[4];
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int status;
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status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
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4, info);
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if (status != 0)
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{
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opcode = NULL;
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}
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else
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{
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insn[1] = ARRANGE_ENDIAN (info, buffer);
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*insn_len += 4;
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}
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}
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if (opcode == NULL)
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{
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const struct arc_long_opcode *long_opcode;
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/* No instruction found yet, try the long instructions. */
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long_opcode =
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find_format_long_instructions (insn, insn_len, isa_mask,
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memaddr, info);
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if (long_opcode != NULL)
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{
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iter->mode = OPERAND_ITERATOR_LONG;
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iter->insn = insn;
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iter->state.long_insn.long_opcode = long_opcode;
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iter->state.long_insn.opidx_base =
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long_opcode->base_opcode.operands;
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iter->state.long_insn.opidx_limm =
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long_opcode->operands;
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opcode = &long_opcode->base_opcode;
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}
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}
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else
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{
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iter->mode = OPERAND_ITERATOR_STANDARD;
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iter->insn = insn;
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iter->state.standard.opcode = opcode;
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iter->state.standard.opidx = opcode->operands;
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}
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*opcode_result = opcode;
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return TRUE;
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}
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|
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static void
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print_flags (const struct arc_opcode *opcode,
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unsigned *insn,
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struct disassemble_info *info)
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{
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const unsigned char *flgidx;
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unsigned int value;
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|
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/* Now extract and print the flags. */
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for (flgidx = opcode->flags; *flgidx; flgidx++)
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{
|
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/* Get a valid flag class. */
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const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
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const unsigned *flgopridx;
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|
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/* Check first the extensions. */
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if (cl_flags->flag_class & F_CLASS_EXTEND)
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{
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const char *name;
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value = (insn[0] & 0x1F);
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|
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name = arcExtMap_condCodeName (value);
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if (name)
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{
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(*info->fprintf_func) (info->stream, ".%s", name);
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continue;
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}
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}
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|
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for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
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{
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const struct arc_flag_operand *flg_operand =
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&arc_flag_operands[*flgopridx];
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|
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if (!flg_operand->favail)
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continue;
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value = (insn[0] >> flg_operand->shift)
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& ((1 << flg_operand->bits) - 1);
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if (value == flg_operand->code)
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{
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/* FIXME!: print correctly nt/t flag. */
|
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if (!special_flag_p (opcode->name, flg_operand->name))
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(*info->fprintf_func) (info->stream, ".");
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else if (info->insn_type == dis_dref)
|
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{
|
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switch (flg_operand->name[0])
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{
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case 'b':
|
|
info->data_size = 1;
|
|
break;
|
|
case 'h':
|
|
case 'w':
|
|
info->data_size = 2;
|
|
break;
|
|
default:
|
|
info->data_size = 4;
|
|
break;
|
|
}
|
|
}
|
|
if (flg_operand->name[0] == 'd'
|
|
&& flg_operand->name[1] == 0)
|
|
info->branch_delay_insns = 1;
|
|
|
|
/* Check if it is a conditional flag. */
|
|
if (cl_flags->flag_class & F_CLASS_COND)
|
|
{
|
|
if (info->insn_type == dis_jsr)
|
|
info->insn_type = dis_condjsr;
|
|
else if (info->insn_type == dis_branch)
|
|
info->insn_type = dis_condbranch;
|
|
}
|
|
|
|
(*info->fprintf_func) (info->stream, "%s", flg_operand->name);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static const char *
|
|
get_auxreg (const struct arc_opcode *opcode,
|
|
int value,
|
|
unsigned isa_mask)
|
|
{
|
|
const char *name;
|
|
unsigned int i;
|
|
const struct arc_aux_reg *auxr = &arc_aux_regs[0];
|
|
|
|
if (opcode->insn_class != AUXREG)
|
|
return NULL;
|
|
|
|
name = arcExtMap_auxRegName (value);
|
|
if (name)
|
|
return name;
|
|
|
|
for (i = 0; i < arc_num_aux_regs; i++, auxr++)
|
|
{
|
|
if (!(auxr->cpu & isa_mask))
|
|
continue;
|
|
|
|
if (auxr->subclass != NONE)
|
|
return NULL;
|
|
|
|
if (auxr->address == value)
|
|
return auxr->name;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
/* Calculate the instruction length for an instruction starting with MSB
|
|
and LSB, the most and least significant byte. The ISA_MASK is used to
|
|
filter the instructions considered to only those that are part of the
|
|
current architecture.
|
|
|
|
The instruction lengths are calculated from the ARC_OPCODE table, and
|
|
cached for later use. */
|
|
|
|
static unsigned int
|
|
arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
|
|
{
|
|
bfd_byte major_opcode = msb >> 3;
|
|
|
|
switch (info->mach)
|
|
{
|
|
case bfd_mach_arc_nps400:
|
|
if (major_opcode == 0xb)
|
|
{
|
|
bfd_byte minor_opcode = lsb & 0x1f;
|
|
|
|
if (minor_opcode < 4)
|
|
return 2;
|
|
}
|
|
case bfd_mach_arc_arc700:
|
|
case bfd_mach_arc_arc600:
|
|
return (major_opcode > 0xb) ? 2 : 4;
|
|
break;
|
|
|
|
case bfd_mach_arc_arcv2:
|
|
return (major_opcode > 0x7) ? 2 : 4;
|
|
break;
|
|
|
|
default:
|
|
abort ();
|
|
}
|
|
}
|
|
|
|
/* Extract and return the value of OPERAND from the instruction whose value
|
|
is held in the array INSN. */
|
|
|
|
static int
|
|
extract_operand_value (const struct arc_operand *operand, unsigned *insn)
|
|
{
|
|
int value;
|
|
|
|
/* Read the limm operand, if required. */
|
|
if (operand->flags & ARC_OPERAND_LIMM)
|
|
/* The second part of the instruction value will have been loaded as
|
|
part of the find_format call made earlier. */
|
|
value = insn[1];
|
|
else
|
|
{
|
|
if (operand->extract)
|
|
value = (*operand->extract) (insn[0], (int *) NULL);
|
|
else
|
|
{
|
|
if (operand->flags & ARC_OPERAND_ALIGNED32)
|
|
{
|
|
value = (insn[0] >> operand->shift)
|
|
& ((1 << (operand->bits - 2)) - 1);
|
|
value = value << 2;
|
|
}
|
|
else
|
|
{
|
|
value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
|
|
}
|
|
if (operand->flags & ARC_OPERAND_SIGNED)
|
|
{
|
|
int signbit = 1 << (operand->bits - 1);
|
|
value = (value ^ signbit) - signbit;
|
|
}
|
|
}
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
/* Find the next operand, and the operands value from ITER. Return TRUE if
|
|
there is another operand, otherwise return FALSE. If there is an
|
|
operand returned then the operand is placed into OPERAND, and the value
|
|
into VALUE. If there is no operand returned then OPERAND and VALUE are
|
|
unchanged. */
|
|
|
|
static bfd_boolean
|
|
operand_iterator_next (struct arc_operand_iterator *iter,
|
|
const struct arc_operand **operand,
|
|
int *value)
|
|
{
|
|
if (iter->mode == OPERAND_ITERATOR_STANDARD)
|
|
{
|
|
if (*iter->state.standard.opidx == 0)
|
|
{
|
|
*operand = NULL;
|
|
return FALSE;
|
|
}
|
|
|
|
*operand = &arc_operands[*iter->state.standard.opidx];
|
|
*value = extract_operand_value (*operand, iter->insn);
|
|
iter->state.standard.opidx++;
|
|
}
|
|
else
|
|
{
|
|
const struct arc_operand *operand_base, *operand_limm;
|
|
int value_base, value_limm;
|
|
|
|
if (*iter->state.long_insn.opidx_limm == 0)
|
|
{
|
|
*operand = NULL;
|
|
return FALSE;
|
|
}
|
|
|
|
operand_base = &arc_operands[*iter->state.long_insn.opidx_base];
|
|
operand_limm = &arc_operands[*iter->state.long_insn.opidx_limm];
|
|
|
|
if (operand_base->flags & ARC_OPERAND_LIMM)
|
|
{
|
|
/* We've reached the end of the operand list. */
|
|
*operand = NULL;
|
|
return FALSE;
|
|
}
|
|
|
|
value_base = value_limm = 0;
|
|
if (!(operand_limm->flags & ARC_OPERAND_IGNORE))
|
|
{
|
|
/* This should never happen. If it does then the use of
|
|
extract_operand_value below will access memory beyond
|
|
the insn array. */
|
|
assert ((operand_limm->flags & ARC_OPERAND_LIMM) == 0);
|
|
|
|
*operand = operand_limm;
|
|
value_limm = extract_operand_value (*operand, &iter->insn[1]);
|
|
}
|
|
|
|
if (!(operand_base->flags & ARC_OPERAND_IGNORE))
|
|
{
|
|
*operand = operand_base;
|
|
value_base = extract_operand_value (*operand, iter->insn);
|
|
}
|
|
|
|
/* This is a bit of a fudge. There's no reason why simply ORing
|
|
together the two values is the right thing to do, however, for all
|
|
the cases we currently have, it is the right thing, so, for now,
|
|
I've put off solving the more complex problem. */
|
|
*value = value_base | value_limm;
|
|
|
|
iter->state.long_insn.opidx_base++;
|
|
iter->state.long_insn.opidx_limm++;
|
|
}
|
|
return TRUE;
|
|
}
|
|
|
|
/* Disassemble ARC instructions. */
|
|
|
|
static int
|
|
print_insn_arc (bfd_vma memaddr,
|
|
struct disassemble_info *info)
|
|
{
|
|
bfd_byte buffer[4];
|
|
unsigned int lowbyte, highbyte;
|
|
int status;
|
|
unsigned int insn_len;
|
|
unsigned insn[2] = { 0, 0 };
|
|
unsigned isa_mask;
|
|
const struct arc_opcode *opcode;
|
|
bfd_boolean need_comma;
|
|
bfd_boolean open_braket;
|
|
int size;
|
|
const struct arc_operand *operand;
|
|
int value;
|
|
struct arc_operand_iterator iter;
|
|
|
|
memset (&iter, 0, sizeof (iter));
|
|
lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
|
|
highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
|
|
|
|
switch (info->mach)
|
|
{
|
|
case bfd_mach_arc_nps400:
|
|
isa_mask = ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400;
|
|
break;
|
|
|
|
case bfd_mach_arc_arc700:
|
|
isa_mask = ARC_OPCODE_ARC700;
|
|
break;
|
|
|
|
case bfd_mach_arc_arc600:
|
|
isa_mask = ARC_OPCODE_ARC600;
|
|
break;
|
|
|
|
case bfd_mach_arc_arcv2:
|
|
default:
|
|
isa_mask = ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARCv2EM;
|
|
break;
|
|
}
|
|
|
|
/* This variable may be set by the instruction decoder. It suggests
|
|
the number of bytes objdump should display on a single line. If
|
|
the instruction decoder sets this, it should always set it to
|
|
the same value in order to get reasonable looking output. */
|
|
|
|
info->bytes_per_line = 8;
|
|
|
|
/* In the next lines, we set two info variables control the way
|
|
objdump displays the raw data. For example, if bytes_per_line is
|
|
8 and bytes_per_chunk is 4, the output will look like this:
|
|
00: 00000000 00000000
|
|
with the chunks displayed according to "display_endian". */
|
|
|
|
if (info->section
|
|
&& !(info->section->flags & SEC_CODE))
|
|
{
|
|
/* This is not a CODE section. */
|
|
switch (info->section->size)
|
|
{
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
size = info->section->size;
|
|
break;
|
|
default:
|
|
size = (info->section->size & 0x01) ? 1 : 4;
|
|
break;
|
|
}
|
|
info->bytes_per_chunk = 1;
|
|
info->display_endian = info->endian;
|
|
}
|
|
else
|
|
{
|
|
size = 2;
|
|
info->bytes_per_chunk = 2;
|
|
info->display_endian = info->endian;
|
|
}
|
|
|
|
/* Read the insn into a host word. */
|
|
status = (*info->read_memory_func) (memaddr, buffer, size, info);
|
|
if (status != 0)
|
|
{
|
|
(*info->memory_error_func) (status, memaddr, info);
|
|
return -1;
|
|
}
|
|
|
|
if (info->section
|
|
&& !(info->section->flags & SEC_CODE))
|
|
{
|
|
/* Data section. */
|
|
unsigned long data;
|
|
|
|
data = bfd_get_bits (buffer, size * 8,
|
|
info->display_endian == BFD_ENDIAN_BIG);
|
|
switch (size)
|
|
{
|
|
case 1:
|
|
(*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
|
|
break;
|
|
case 2:
|
|
(*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
|
|
break;
|
|
case 4:
|
|
(*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
|
|
break;
|
|
default:
|
|
abort ();
|
|
}
|
|
return size;
|
|
}
|
|
|
|
insn_len = arc_insn_length (buffer[lowbyte], buffer[highbyte], info);
|
|
pr_debug ("instruction length = %d bytes\n", insn_len);
|
|
switch (insn_len)
|
|
{
|
|
case 2:
|
|
insn[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
|
|
break;
|
|
|
|
default:
|
|
/* An unknown instruction is treated as being length 4. This is
|
|
possibly not the best solution, but matches the behaviour that was
|
|
in place before the table based instruction length look-up was
|
|
introduced. */
|
|
case 4:
|
|
/* This is a long instruction: Read the remaning 2 bytes. */
|
|
status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
|
|
if (status != 0)
|
|
{
|
|
(*info->memory_error_func) (status, memaddr + 2, info);
|
|
return -1;
|
|
}
|
|
insn[0] = ARRANGE_ENDIAN (info, buffer);
|
|
break;
|
|
}
|
|
|
|
/* Set some defaults for the insn info. */
|
|
info->insn_info_valid = 1;
|
|
info->branch_delay_insns = 0;
|
|
info->data_size = 0;
|
|
info->insn_type = dis_nonbranch;
|
|
info->target = 0;
|
|
info->target2 = 0;
|
|
|
|
/* FIXME to be moved in dissasemble_init_for_target. */
|
|
info->disassembler_needs_relocs = TRUE;
|
|
|
|
/* Find the first match in the opcode table. */
|
|
if (!find_format (memaddr, insn, &insn_len, isa_mask, info, &opcode, &iter))
|
|
return -1;
|
|
|
|
if (!opcode)
|
|
{
|
|
if (insn_len == 2)
|
|
(*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
|
|
else
|
|
(*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
|
|
|
|
info->insn_type = dis_noninsn;
|
|
return insn_len;
|
|
}
|
|
|
|
/* Print the mnemonic. */
|
|
(*info->fprintf_func) (info->stream, "%s", opcode->name);
|
|
|
|
/* Preselect the insn class. */
|
|
switch (opcode->insn_class)
|
|
{
|
|
case BRANCH:
|
|
case JUMP:
|
|
if (!strncmp (opcode->name, "bl", 2)
|
|
|| !strncmp (opcode->name, "jl", 2))
|
|
{
|
|
if (opcode->subclass == COND)
|
|
info->insn_type = dis_condjsr;
|
|
else
|
|
info->insn_type = dis_jsr;
|
|
}
|
|
else
|
|
{
|
|
if (opcode->subclass == COND)
|
|
info->insn_type = dis_condbranch;
|
|
else
|
|
info->insn_type = dis_branch;
|
|
}
|
|
break;
|
|
case MEMORY:
|
|
info->insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
|
|
break;
|
|
default:
|
|
info->insn_type = dis_nonbranch;
|
|
break;
|
|
}
|
|
|
|
pr_debug ("%s: 0x%08x\n", opcode->name, opcode->opcode);
|
|
|
|
print_flags (opcode, insn, info);
|
|
|
|
if (opcode->operands[0] != 0)
|
|
(*info->fprintf_func) (info->stream, "\t");
|
|
|
|
need_comma = FALSE;
|
|
open_braket = FALSE;
|
|
|
|
/* Now extract and print the operands. */
|
|
operand = NULL;
|
|
while (operand_iterator_next (&iter, &operand, &value))
|
|
{
|
|
if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
|
|
{
|
|
(*info->fprintf_func) (info->stream, "]");
|
|
open_braket = FALSE;
|
|
continue;
|
|
}
|
|
|
|
/* Only take input from real operands. */
|
|
if ((operand->flags & ARC_OPERAND_FAKE)
|
|
&& !(operand->flags & ARC_OPERAND_BRAKET))
|
|
continue;
|
|
|
|
if ((operand->flags & ARC_OPERAND_IGNORE)
|
|
&& (operand->flags & ARC_OPERAND_IR)
|
|
&& value == -1)
|
|
continue;
|
|
|
|
if (need_comma)
|
|
(*info->fprintf_func) (info->stream, ",");
|
|
|
|
if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET))
|
|
{
|
|
(*info->fprintf_func) (info->stream, "[");
|
|
open_braket = TRUE;
|
|
need_comma = FALSE;
|
|
continue;
|
|
}
|
|
|
|
/* Print the operand as directed by the flags. */
|
|
if (operand->flags & ARC_OPERAND_IR)
|
|
{
|
|
const char *rname;
|
|
|
|
assert (value >=0 && value < 64);
|
|
rname = arcExtMap_coreRegName (value);
|
|
if (!rname)
|
|
rname = regnames[value];
|
|
(*info->fprintf_func) (info->stream, "%s", rname);
|
|
if (operand->flags & ARC_OPERAND_TRUNCATE)
|
|
{
|
|
rname = arcExtMap_coreRegName (value + 1);
|
|
if (!rname)
|
|
rname = regnames[value + 1];
|
|
(*info->fprintf_func) (info->stream, "%s", rname);
|
|
}
|
|
}
|
|
else if (operand->flags & ARC_OPERAND_LIMM)
|
|
{
|
|
const char *rname = get_auxreg (opcode, value, isa_mask);
|
|
if (rname && open_braket)
|
|
(*info->fprintf_func) (info->stream, "%s", rname);
|
|
else
|
|
{
|
|
(*info->fprintf_func) (info->stream, "%#x", value);
|
|
if (info->insn_type == dis_branch
|
|
|| info->insn_type == dis_jsr)
|
|
info->target = (bfd_vma) value;
|
|
}
|
|
}
|
|
else if (operand->flags & ARC_OPERAND_PCREL)
|
|
{
|
|
/* PCL relative. */
|
|
if (info->flags & INSN_HAS_RELOC)
|
|
memaddr = 0;
|
|
(*info->print_address_func) ((memaddr & ~3) + value, info);
|
|
|
|
info->target = (bfd_vma) (memaddr & ~3) + value;
|
|
}
|
|
else if (operand->flags & ARC_OPERAND_SIGNED)
|
|
{
|
|
const char *rname = get_auxreg (opcode, value, isa_mask);
|
|
if (rname && open_braket)
|
|
(*info->fprintf_func) (info->stream, "%s", rname);
|
|
else
|
|
(*info->fprintf_func) (info->stream, "%d", value);
|
|
}
|
|
else
|
|
{
|
|
if (operand->flags & ARC_OPERAND_TRUNCATE
|
|
&& !(operand->flags & ARC_OPERAND_ALIGNED32)
|
|
&& !(operand->flags & ARC_OPERAND_ALIGNED16)
|
|
&& value > 0 && value <= 14)
|
|
(*info->fprintf_func) (info->stream, "r13-%s",
|
|
regnames[13 + value - 1]);
|
|
else
|
|
{
|
|
const char *rname = get_auxreg (opcode, value, isa_mask);
|
|
if (rname && open_braket)
|
|
(*info->fprintf_func) (info->stream, "%s", rname);
|
|
else
|
|
(*info->fprintf_func) (info->stream, "%#x", value);
|
|
}
|
|
}
|
|
|
|
need_comma = TRUE;
|
|
}
|
|
|
|
return insn_len;
|
|
}
|
|
|
|
|
|
disassembler_ftype
|
|
arc_get_disassembler (bfd *abfd)
|
|
{
|
|
/* Read the extenssion insns and registers, if any. */
|
|
build_ARC_extmap (abfd);
|
|
#ifdef DEBUG
|
|
dump_ARC_extmap ();
|
|
#endif
|
|
|
|
return print_insn_arc;
|
|
}
|
|
|
|
/* Disassemble ARC instructions. Used by debugger. */
|
|
|
|
struct arcDisState
|
|
arcAnalyzeInstr (bfd_vma memaddr,
|
|
struct disassemble_info *info)
|
|
{
|
|
struct arcDisState ret;
|
|
memset (&ret, 0, sizeof (struct arcDisState));
|
|
|
|
ret.instructionLen = print_insn_arc (memaddr, info);
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|
|
|
#if 0
|
|
ret.words[0] = insn[0];
|
|
ret.words[1] = insn[1];
|
|
ret._this = &ret;
|
|
ret.coreRegName = _coreRegName;
|
|
ret.auxRegName = _auxRegName;
|
|
ret.condCodeName = _condCodeName;
|
|
ret.instName = _instName;
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Local variables:
|
|
eval: (c-set-style "gnu")
|
|
indent-tabs-mode: t
|
|
End: */
|