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d87bef3a7b
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
388 lines
9.1 KiB
C
388 lines
9.1 KiB
C
/* Disassembler code for Renesas RX.
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Copyright (C) 2008-2023 Free Software Foundation, Inc.
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Contributed by Red Hat.
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Written by DJ Delorie.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "bfd.h"
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#include "dis-asm.h"
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#include "opcode/rx.h"
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#include "libiberty.h"
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#include "opintl.h"
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#include <setjmp.h>
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typedef struct
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{
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bfd_vma pc;
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disassemble_info * dis;
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} RX_Data;
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struct private
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{
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OPCODES_SIGJMP_BUF bailout;
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};
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static int
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rx_get_byte (void * vdata)
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{
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bfd_byte buf[1];
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RX_Data *rx_data = (RX_Data *) vdata;
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int status;
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status = rx_data->dis->read_memory_func (rx_data->pc,
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buf,
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1,
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rx_data->dis);
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if (status != 0)
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{
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struct private *priv = (struct private *) rx_data->dis->private_data;
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rx_data->dis->memory_error_func (status, rx_data->pc,
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rx_data->dis);
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OPCODES_SIGLONGJMP (priv->bailout, 1);
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}
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rx_data->pc ++;
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return buf[0];
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}
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static char const * size_names[RX_MAX_SIZE] =
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{
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"", ".b", ".ub", ".b", ".w", ".uw", ".w", ".a", ".l", "", "<error>"
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};
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static char const * opsize_names[RX_MAX_SIZE] =
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{
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"", ".b", ".b", ".b", ".w", ".w", ".w", ".a", ".l", ".d", "<error>"
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};
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static char const * register_names[] =
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{
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/* General registers. */
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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/* Control registers. */
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"psw", "pc", "usp", "fpsw", NULL, NULL, NULL, NULL,
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"bpsw", "bpc", "isp", "fintv", "intb", "extb", NULL, NULL,
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"a0", "a1", NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
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};
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static char const * condition_names[] =
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{
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/* Condition codes. */
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"eq", "ne", "c", "nc", "gtu", "leu", "pz", "n",
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"ge", "lt", "gt", "le", "o", "no", "<invalid>", "<invalid>"
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};
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static const char * flag_names[] =
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{
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"c", "z", "s", "o", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"i", "u", "", "", "", "", "", "",
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"", "", "", "", "", "", "", ""
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};
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static const char * double_register_names[] =
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{
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"dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7",
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"dr8", "dr9", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
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};
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static const char * double_register_high_names[] =
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{
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"drh0", "drh1", "drh2", "drh3", "drh4", "drh5", "drh6", "drh7",
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"drh8", "drh9", "drh10", "drh11", "drh12", "drh13", "drh14", "drh15"
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};
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static const char * double_register_low_names[] =
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{
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"drl0", "drl1", "drl2", "drl3", "drl4", "drl5", "drl6", "drl7",
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"drl8", "drl9", "drl10", "drl11", "drl12", "drl13", "drl14", "drl15"
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};
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static const char * double_control_register_names[] =
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{
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"dpsw", "dcmr", "decnt", "depc"
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};
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static const char * double_condition_names[] =
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{
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"", "un", "eq", "", "lt", "", "le"
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};
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static inline const char *
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get_register_name (unsigned int reg)
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{
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if (reg < ARRAY_SIZE (register_names))
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return register_names[reg];
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return _("<invalid register number>");
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}
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static inline const char *
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get_condition_name (unsigned int cond)
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{
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if (cond < ARRAY_SIZE (condition_names))
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return condition_names[cond];
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return _("<invalid condition code>");
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}
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static inline const char *
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get_flag_name (unsigned int flag)
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{
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if (flag < ARRAY_SIZE (flag_names))
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return flag_names[flag];
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return _("<invalid flag>");
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}
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static inline const char *
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get_double_register_name (unsigned int reg)
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{
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if (reg < ARRAY_SIZE (double_register_names))
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return double_register_names[reg];
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return _("<invalid register number>");
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}
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static inline const char *
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get_double_register_high_name (unsigned int reg)
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{
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if (reg < ARRAY_SIZE (double_register_high_names))
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return double_register_high_names[reg];
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return _("<invalid register number>");
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}
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static inline const char *
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get_double_register_low_name (unsigned int reg)
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{
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if (reg < ARRAY_SIZE (double_register_low_names))
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return double_register_low_names[reg];
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return _("<invalid register number>");
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}
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static inline const char *
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get_double_control_register_name (unsigned int reg)
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{
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if (reg < ARRAY_SIZE (double_control_register_names))
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return double_control_register_names[reg];
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return _("<invalid register number>");
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}
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static inline const char *
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get_double_condition_name (unsigned int cond)
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{
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if (cond < ARRAY_SIZE (double_condition_names))
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return double_condition_names[cond];
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return _("<invalid condition code>");
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}
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static inline const char *
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get_opsize_name (unsigned int opsize)
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{
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if (opsize < ARRAY_SIZE (opsize_names))
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return opsize_names[opsize];
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return _("<invalid opsize>");
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}
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static inline const char *
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get_size_name (unsigned int size)
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{
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if (size < ARRAY_SIZE (size_names))
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return size_names[size];
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return _("<invalid size>");
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}
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int
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print_insn_rx (bfd_vma addr, disassemble_info * dis)
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{
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int rv;
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RX_Data rx_data;
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RX_Opcode_Decoded opcode;
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const char * s;
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struct private priv;
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dis->private_data = &priv;
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rx_data.pc = addr;
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rx_data.dis = dis;
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if (OPCODES_SIGSETJMP (priv.bailout) != 0)
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{
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/* Error return. */
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return -1;
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}
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rv = rx_decode_opcode (addr, &opcode, rx_get_byte, &rx_data);
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dis->bytes_per_line = 10;
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#define PR (dis->fprintf_func)
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#define PS (dis->stream)
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#define PC(c) PR (PS, "%c", c)
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/* Detect illegal instructions. */
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if (opcode.op[0].size == RX_Bad_Size
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|| register_names [opcode.op[0].reg] == NULL
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|| register_names [opcode.op[1].reg] == NULL
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|| register_names [opcode.op[2].reg] == NULL)
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{
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bfd_byte buf[10];
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int i;
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PR (PS, ".byte ");
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rx_data.dis->read_memory_func (rx_data.pc - rv, buf, rv, rx_data.dis);
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for (i = 0 ; i < rv; i++)
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PR (PS, "0x%02x ", buf[i]);
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return rv;
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}
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for (s = opcode.syntax; *s; s++)
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{
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if (*s != '%')
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{
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PC (*s);
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}
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else
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{
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RX_Opcode_Operand * oper;
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int do_size = 0;
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int do_hex = 0;
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int do_addr = 0;
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s ++;
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if (*s == 'S')
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{
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do_size = 1;
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s++;
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}
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if (*s == 'x')
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{
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do_hex = 1;
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s++;
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}
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if (*s == 'a')
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{
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do_addr = 1;
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s++;
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}
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switch (*s)
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{
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case '%':
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PC ('%');
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break;
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case 's':
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PR (PS, "%s", get_opsize_name (opcode.size));
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break;
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case 'b':
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s ++;
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if (*s == 'f')
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{
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int imm = opcode.op[2].addend;
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int slsb, dlsb, width;
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dlsb = (imm >> 5) & 0x1f;
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slsb = (imm & 0x1f);
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slsb = (slsb >= 0x10?(slsb ^ 0x1f) + 1:slsb);
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slsb = dlsb - slsb;
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slsb = (slsb < 0?-slsb:slsb);
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width = ((imm >> 10) & 0x1f) - dlsb;
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PR (PS, "#%d, #%d, #%d, %s, %s",
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slsb, dlsb, width,
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get_register_name (opcode.op[1].reg),
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get_register_name (opcode.op[0].reg));
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}
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break;
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case '0':
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case '1':
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case '2':
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oper = opcode.op + (*s - '0');
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if (do_size)
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{
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if (oper->type == RX_Operand_Indirect || oper->type == RX_Operand_Zero_Indirect)
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PR (PS, "%s", get_size_name (oper->size));
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}
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else
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switch (oper->type)
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{
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case RX_Operand_Immediate:
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if (do_addr)
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dis->print_address_func (oper->addend, dis);
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else if (do_hex
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|| oper->addend > 999
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|| oper->addend < -999)
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PR (PS, "%#x", oper->addend);
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else
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PR (PS, "%d", oper->addend);
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break;
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case RX_Operand_Register:
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case RX_Operand_TwoReg:
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PR (PS, "%s", get_register_name (oper->reg));
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break;
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case RX_Operand_Indirect:
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PR (PS, "%d[%s]", oper->addend, get_register_name (oper->reg));
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break;
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case RX_Operand_Zero_Indirect:
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PR (PS, "[%s]", get_register_name (oper->reg));
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break;
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case RX_Operand_Postinc:
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PR (PS, "[%s+]", get_register_name (oper->reg));
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break;
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case RX_Operand_Predec:
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PR (PS, "[-%s]", get_register_name (oper->reg));
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break;
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case RX_Operand_Condition:
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PR (PS, "%s", get_condition_name (oper->reg));
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break;
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case RX_Operand_Flag:
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PR (PS, "%s", get_flag_name (oper->reg));
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break;
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case RX_Operand_DoubleReg:
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PR (PS, "%s", get_double_register_name (oper->reg));
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break;
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case RX_Operand_DoubleRegH:
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PR (PS, "%s", get_double_register_high_name (oper->reg));
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break;
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case RX_Operand_DoubleRegL:
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PR (PS, "%s", get_double_register_low_name (oper->reg));
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break;
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case RX_Operand_DoubleCReg:
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PR (PS, "%s", get_double_control_register_name (oper->reg));
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break;
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case RX_Operand_DoubleCond:
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PR (PS, "%s", get_double_condition_name (oper->reg));
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break;
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default:
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PR (PS, "[???]");
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break;
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}
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}
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}
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}
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return rv;
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}
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