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This commit brings all the changes made by running gdb/copyright.py as per GDB's Start of New Year Procedure. For the avoidance of doubt, all changes in this commits were performed by the script.
135 lines
3.8 KiB
C
135 lines
3.8 KiB
C
/* Common target dependent code for GDB on AArch64 systems.
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Copyright (C) 2009-2022 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef AARCH64_TDEP_H
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#define AARCH64_TDEP_H
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#include "arch/aarch64.h"
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#include "displaced-stepping.h"
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#include "infrun.h"
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#include "gdbarch.h"
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/* Forward declarations. */
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struct gdbarch;
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struct regset;
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/* AArch64 Dwarf register numbering. */
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#define AARCH64_DWARF_X0 0
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#define AARCH64_DWARF_SP 31
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#define AARCH64_DWARF_PAUTH_RA_STATE 34
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#define AARCH64_DWARF_PAUTH_DMASK 35
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#define AARCH64_DWARF_PAUTH_CMASK 36
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#define AARCH64_DWARF_V0 64
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#define AARCH64_DWARF_SVE_VG 46
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#define AARCH64_DWARF_SVE_FFR 47
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#define AARCH64_DWARF_SVE_P0 48
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#define AARCH64_DWARF_SVE_Z0 96
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/* Size of integer registers. */
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#define X_REGISTER_SIZE 8
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#define B_REGISTER_SIZE 1
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#define H_REGISTER_SIZE 2
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#define S_REGISTER_SIZE 4
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#define D_REGISTER_SIZE 8
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#define Q_REGISTER_SIZE 16
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/* Total number of general (X) registers. */
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#define AARCH64_X_REGISTER_COUNT 32
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/* Total number of D registers. */
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#define AARCH64_D_REGISTER_COUNT 32
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/* The maximum number of modified instructions generated for one
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single-stepped instruction. */
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#define AARCH64_DISPLACED_MODIFIED_INSNS 1
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/* Target-dependent structure in gdbarch. */
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struct aarch64_gdbarch_tdep : gdbarch_tdep
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{
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/* Lowest address at which instructions will appear. */
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CORE_ADDR lowest_pc = 0;
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/* Offset to PC value in jump buffer. If this is negative, longjmp
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support will be disabled. */
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int jb_pc = 0;
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/* And the size of each entry in the buf. */
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size_t jb_elt_size = 0;
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/* Types for AdvSISD registers. */
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struct type *vnq_type = nullptr;
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struct type *vnd_type = nullptr;
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struct type *vns_type = nullptr;
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struct type *vnh_type = nullptr;
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struct type *vnb_type = nullptr;
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struct type *vnv_type = nullptr;
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/* syscall record. */
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int (*aarch64_syscall_record) (struct regcache *regcache,
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unsigned long svc_number) = nullptr;
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/* The VQ value for SVE targets, or zero if SVE is not supported. */
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uint64_t vq = 0;
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/* Returns true if the target supports SVE. */
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bool has_sve () const
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{
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return vq != 0;
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}
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int pauth_reg_base = 0;
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int pauth_ra_state_regnum = 0;
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/* Returns true if the target supports pauth. */
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bool has_pauth () const
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{
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return pauth_reg_base != -1;
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}
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/* First MTE register. This is -1 if no MTE registers are available. */
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int mte_reg_base = 0;
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/* Returns true if the target supports MTE. */
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bool has_mte () const
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{
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return mte_reg_base != -1;
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}
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};
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const target_desc *aarch64_read_description (uint64_t vq, bool pauth_p,
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bool mte_p);
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extern int aarch64_process_record (struct gdbarch *gdbarch,
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struct regcache *regcache, CORE_ADDR addr);
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displaced_step_copy_insn_closure_up
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aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
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CORE_ADDR from, CORE_ADDR to,
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struct regcache *regs);
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void aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
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displaced_step_copy_insn_closure *dsc,
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CORE_ADDR from, CORE_ADDR to,
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struct regcache *regs);
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bool aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch);
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#endif /* aarch64-tdep.h */
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