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143 lines
3.9 KiB
C
143 lines
3.9 KiB
C
/* ARC target-dependent stuff. Extension data structures.
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Copyright (C) 1995-2021 Free Software Foundation, Inc.
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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/*This header file defines a table of extensions to the ARC processor
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architecture. These extensions are read from the '.arcextmap' or
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'.gnu.linkonce.arcextmap.<type>.<N>' sections in the ELF file which
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is identified by the bfd parameter to the build_ARC_extmap function.
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These extensions may include:
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core registers
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auxiliary registers
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instructions
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condition codes
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Once the table has been constructed, accessor functions may be used
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to retrieve information from it.
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The build_ARC_extmap constructor function build_ARC_extmap may be
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called as many times as required; it will re-initialize the table
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each time. */
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#ifndef ARC_EXTENSIONS_H
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#define ARC_EXTENSIONS_H
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#include "opcode/arc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define IGNORE_FIRST_OPD 1
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/* Define this if we do not want to encode instructions based on the
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ARCompact Programmer's Reference. */
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#define UNMANGLED
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/* This defines the kinds of extensions which may be read from the
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ections in the executable files. */
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enum ExtOperType
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{
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EXT_INSTRUCTION = 0,
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EXT_CORE_REGISTER = 1,
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EXT_AUX_REGISTER = 2,
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EXT_COND_CODE = 3,
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EXT_INSTRUCTION32 = 4,
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EXT_AC_INSTRUCTION = 4,
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EXT_REMOVE_CORE_REG = 5,
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EXT_LONG_CORE_REGISTER = 6,
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EXT_AUX_REGISTER_EXTENDED = 7,
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EXT_INSTRUCTION32_EXTENDED = 8,
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EXT_CORE_REGISTER_CLASS = 9
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};
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enum ExtReadWrite
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{
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REG_INVALID,
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REG_READ,
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REG_WRITE,
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REG_READWRITE
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};
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/* Macro used when generating the patterns for an extension
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instruction. */
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#define INSERT_XOP(OP, NAME, CODE, MASK, CPU, ARG, FLG) \
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do { \
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(OP)->name = NAME; \
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(OP)->opcode = CODE; \
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(OP)->mask = MASK; \
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(OP)->cpu = CPU; \
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(OP)->insn_class = ARITH; \
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(OP)->subclass = NONE; \
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memcpy ((OP)->operands, (ARG), MAX_INSN_ARGS); \
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memcpy ((OP)->flags, (FLG), MAX_INSN_FLGS); \
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(OP++); \
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} while (0)
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/* Typedef to hold the extension instruction definition. */
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typedef struct ExtInstruction
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{
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/* Name. */
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char *name;
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/* Major opcode. */
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char major;
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/* Minor(sub) opcode. */
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char minor;
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/* Flags, holds the syntax class and modifiers. */
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char flags;
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/* Syntax class. Use by assembler. */
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unsigned char syntax;
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/* Syntax class modifier. Used by assembler. */
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unsigned char modsyn;
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/* Suffix class. Used by assembler. */
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unsigned char suffix;
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/* Pointer to the next extension instruction. */
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struct ExtInstruction* next;
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} extInstruction_t;
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/* Constructor function. */
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extern void build_ARC_extmap (bfd *);
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/* Accessor functions. */
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extern enum ExtReadWrite arcExtMap_coreReadWrite (int);
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extern const char * arcExtMap_coreRegName (int);
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extern const char * arcExtMap_auxRegName (unsigned);
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extern const char * arcExtMap_condCodeName (int);
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extern const extInstruction_t *arcExtMap_insn (int, unsigned long long);
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extern struct arc_opcode *arcExtMap_genOpcode (const extInstruction_t *,
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unsigned arc_target,
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const char **errmsg);
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/* Dump function (for debugging). */
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extern void dump_ARC_extmap (void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARC_EXTENSIONS_H */
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