mirror of
https://sourceware.org/git/binutils-gdb.git
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d96bf37ba8
cpu/ * mep.opc (mep_cgen_expand_macros_and_parse_operand): Replace "if (x) free (x)" with "free (x)". opcodes/ * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout. * sparc-dis.c: Likewise. * tic4x-dis.c: Likewise. * xtensa-dis.c: Likewise. * bpf-desc.c: Regenerate. * epiphany-desc.c: Regenerate. * fr30-desc.c: Regenerate. * frv-desc.c: Regenerate. * ip2k-desc.c: Regenerate. * iq2000-desc.c: Regenerate. * lm32-desc.c: Regenerate. * m32c-desc.c: Regenerate. * m32r-desc.c: Regenerate. * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mt-desc.c: Regenerate. * or1k-desc.c: Regenerate. * xc16x-desc.c: Regenerate. * xstormy16-desc.c: Regenerate.
811 lines
21 KiB
C
811 lines
21 KiB
C
/* ARC target-dependent stuff. Extension structure access functions
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Copyright (C) 1995-2020 Free Software Foundation, Inc.
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include "bfd.h"
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#include "arc-ext.h"
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#include "elf/arc.h"
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#include "libiberty.h"
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/* This module provides support for extensions to the ARC processor
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architecture. */
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/* Local constants. */
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#define FIRST_EXTENSION_CORE_REGISTER 32
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#define LAST_EXTENSION_CORE_REGISTER 59
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#define FIRST_EXTENSION_CONDITION_CODE 0x10
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#define LAST_EXTENSION_CONDITION_CODE 0x1f
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#define NUM_EXT_CORE \
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(LAST_EXTENSION_CORE_REGISTER - FIRST_EXTENSION_CORE_REGISTER + 1)
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#define NUM_EXT_COND \
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(LAST_EXTENSION_CONDITION_CODE - FIRST_EXTENSION_CONDITION_CODE + 1)
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#define INST_HASH_BITS 6
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#define INST_HASH_SIZE (1 << INST_HASH_BITS)
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#define INST_HASH_MASK (INST_HASH_SIZE - 1)
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/* Local types. */
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/* These types define the information stored in the table. */
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struct ExtAuxRegister
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{
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unsigned address;
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char * name;
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struct ExtAuxRegister * next;
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};
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struct ExtCoreRegister
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{
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short number;
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enum ExtReadWrite rw;
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char * name;
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};
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struct arcExtMap
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{
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struct ExtAuxRegister* auxRegisters;
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struct ExtInstruction* instructions[INST_HASH_SIZE];
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struct ExtCoreRegister coreRegisters[NUM_EXT_CORE];
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char * condCodes[NUM_EXT_COND];
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};
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/* Local data. */
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/* Extension table. */
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static struct arcExtMap arc_extension_map;
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/* Local macros. */
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/* A hash function used to map instructions into the table. */
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#define INST_HASH(MAJOR, MINOR) ((((MAJOR) << 3) ^ (MINOR)) & INST_HASH_MASK)
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/* Local functions. */
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static void
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create_map (unsigned char *block,
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unsigned long length)
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{
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unsigned char *p = block;
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while (p && p < (block + length))
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{
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/* p[0] == length of record
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p[1] == type of record
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For instructions:
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p[2] = opcode
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p[3] = minor opcode (if opcode == 3)
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p[4] = flags
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p[5]+ = name
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For core regs and condition codes:
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p[2] = value
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p[3]+ = name
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For auxiliary regs:
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p[2..5] = value
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p[6]+ = name
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(value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]). */
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/* The sequence of records is temrinated by an "empty"
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record. */
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if (p[0] == 0)
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break;
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switch (p[1])
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{
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case EXT_INSTRUCTION:
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{
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struct ExtInstruction *insn = XNEW (struct ExtInstruction);
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int major = p[2];
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int minor = p[3];
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struct ExtInstruction **bucket =
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&arc_extension_map.instructions[INST_HASH (major, minor)];
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insn->name = xstrdup ((char *) (p + 5));
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insn->major = major;
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insn->minor = minor;
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insn->flags = p[4];
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insn->next = *bucket;
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insn->suffix = 0;
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insn->syntax = 0;
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insn->modsyn = 0;
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*bucket = insn;
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break;
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}
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case EXT_CORE_REGISTER:
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{
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unsigned char number = p[2];
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char* name = (char *) (p + 3);
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arc_extension_map.
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coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].number
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= number;
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arc_extension_map.
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coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].rw
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= REG_READWRITE;
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arc_extension_map.
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coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name
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= xstrdup (name);
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break;
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}
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case EXT_LONG_CORE_REGISTER:
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{
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unsigned char number = p[2];
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char* name = (char *) (p + 7);
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enum ExtReadWrite rw = p[6];
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arc_extension_map.
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coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].number
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= number;
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arc_extension_map.
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coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].rw
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= rw;
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arc_extension_map.
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coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name
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= xstrdup (name);
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break;
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}
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case EXT_COND_CODE:
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{
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char *cc_name = xstrdup ((char *) (p + 3));
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arc_extension_map.
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condCodes[p[2] - FIRST_EXTENSION_CONDITION_CODE]
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= cc_name;
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break;
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}
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case EXT_AUX_REGISTER:
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{
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/* Trickier -- need to store linked list of these. */
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struct ExtAuxRegister *newAuxRegister
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= XNEW (struct ExtAuxRegister);
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char *aux_name = xstrdup ((char *) (p + 6));
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newAuxRegister->name = aux_name;
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newAuxRegister->address = (((unsigned) p[2] << 24) | (p[3] << 16)
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| (p[4] << 8) | p[5]);
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newAuxRegister->next = arc_extension_map.auxRegisters;
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arc_extension_map.auxRegisters = newAuxRegister;
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break;
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}
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default:
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break;
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}
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p += p[0]; /* Move on to next record. */
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}
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}
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/* Free memory that has been allocated for the extensions. */
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static void
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destroy_map (void)
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{
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struct ExtAuxRegister *r;
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unsigned int i;
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/* Free auxiliary registers. */
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r = arc_extension_map.auxRegisters;
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while (r)
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{
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/* N.B. after r has been freed, r->next is invalid! */
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struct ExtAuxRegister* next = r->next;
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free (r->name);
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free (r);
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r = next;
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}
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/* Free instructions. */
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for (i = 0; i < INST_HASH_SIZE; i++)
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{
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struct ExtInstruction *insn = arc_extension_map.instructions[i];
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while (insn)
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{
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/* N.B. after insn has been freed, insn->next is invalid! */
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struct ExtInstruction *next = insn->next;
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free (insn->name);
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free (insn);
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insn = next;
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}
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}
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/* Free core registers. */
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for (i = 0; i < NUM_EXT_CORE; i++)
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free (arc_extension_map.coreRegisters[i].name);
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/* Free condition codes. */
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for (i = 0; i < NUM_EXT_COND; i++)
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free (arc_extension_map.condCodes[i]);
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memset (&arc_extension_map, 0, sizeof (arc_extension_map));
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}
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static const char *
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ExtReadWrite_image (enum ExtReadWrite val)
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{
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switch (val)
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{
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case REG_INVALID : return "INVALID";
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case REG_READ : return "RO";
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case REG_WRITE : return "WO";
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case REG_READWRITE: return "R/W";
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default : return "???";
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}
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}
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/* Externally visible functions. */
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/* Get the name of an extension instruction. */
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const extInstruction_t *
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arcExtMap_insn (int opcode, unsigned long long insn)
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{
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/* Here the following tasks need to be done. First of all, the
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opcode stored in the Extension Map is the real opcode. However,
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the subopcode stored in the instruction to be disassembled is
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mangled. We pass (in minor opcode), the instruction word. Here
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we will un-mangle it and get the real subopcode which we can look
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for in the Extension Map. This function is used both for the
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ARCTangent and the ARCompact, so we would also need some sort of
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a way to distinguish between the two architectures. This is
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because the ARCTangent does not do any of this mangling so we
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have no issues there. */
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/* If P[22:23] is 0 or 2 then un-mangle using iiiiiI. If it is 1
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then use iiiiIi. Now, if P is 3 then check M[5:5] and if it is 0
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then un-mangle using iiiiiI else iiiiii. */
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unsigned char minor;
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extInstruction_t *temp;
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/* 16-bit instructions. */
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if (0x08 <= opcode && opcode <= 0x0b)
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{
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unsigned char b, c, i;
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b = (insn & 0x0700) >> 8;
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c = (insn & 0x00e0) >> 5;
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i = (insn & 0x001f);
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if (i)
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minor = i;
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else
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minor = (c == 0x07) ? b : c;
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}
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/* 32-bit instructions. */
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else
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{
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unsigned char I, A, B;
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I = (insn & 0x003f0000) >> 16;
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A = (insn & 0x0000003f);
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B = ((insn & 0x07000000) >> 24) | ((insn & 0x00007000) >> 9);
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if (I != 0x2f)
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{
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#ifndef UNMANGLED
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switch (P)
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{
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case 3:
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if (M)
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{
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minor = I;
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break;
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}
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case 0:
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case 2:
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minor = (I >> 1) | ((I & 0x1) << 5);
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break;
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case 1:
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minor = (I >> 1) | (I & 0x1) | ((I & 0x2) << 4);
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}
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#else
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minor = I;
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#endif
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}
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else
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{
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if (A != 0x3f)
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minor = A;
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else
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minor = B;
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}
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}
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temp = arc_extension_map.instructions[INST_HASH (opcode, minor)];
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while (temp)
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{
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if ((temp->major == opcode) && (temp->minor == minor))
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{
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return temp;
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}
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temp = temp->next;
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}
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return NULL;
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}
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/* Get the name of an extension core register. */
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const char *
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arcExtMap_coreRegName (int regnum)
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{
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if (regnum < FIRST_EXTENSION_CORE_REGISTER
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|| regnum > LAST_EXTENSION_CORE_REGISTER)
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return NULL;
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return arc_extension_map.
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coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name;
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}
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/* Get the access mode of an extension core register. */
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enum ExtReadWrite
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arcExtMap_coreReadWrite (int regnum)
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{
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if (regnum < FIRST_EXTENSION_CORE_REGISTER
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|| regnum > LAST_EXTENSION_CORE_REGISTER)
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return REG_INVALID;
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return arc_extension_map.
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coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw;
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}
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/* Get the name of an extension condition code. */
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const char *
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arcExtMap_condCodeName (int code)
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{
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if (code < FIRST_EXTENSION_CONDITION_CODE
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|| code > LAST_EXTENSION_CONDITION_CODE)
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return NULL;
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return arc_extension_map.
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condCodes[code - FIRST_EXTENSION_CONDITION_CODE];
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}
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/* Get the name of an extension auxiliary register. */
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const char *
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arcExtMap_auxRegName (unsigned address)
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{
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/* Walk the list of auxiliary register names and find the name. */
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struct ExtAuxRegister *r;
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for (r = arc_extension_map.auxRegisters; r; r = r->next)
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{
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if (r->address == address)
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return (const char *)r->name;
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}
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return NULL;
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}
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/* Load extensions described in .arcextmap and
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.gnu.linkonce.arcextmap.* ELF section. */
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void
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build_ARC_extmap (bfd *text_bfd)
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{
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asection *sect;
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/* The map is built each time gdb loads an executable file - so free
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any existing map, as the map defined by the new file may differ
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from the old. */
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destroy_map ();
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for (sect = text_bfd->sections; sect != NULL; sect = sect->next)
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if (!strncmp (sect->name,
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".gnu.linkonce.arcextmap.",
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sizeof (".gnu.linkonce.arcextmap.") - 1)
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|| !strcmp (sect->name,".arcextmap"))
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{
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bfd_size_type count = bfd_section_size (sect);
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unsigned char* buffer = xmalloc (count);
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if (buffer)
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{
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if (bfd_get_section_contents (text_bfd, sect, buffer, 0, count))
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create_map (buffer, count);
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free (buffer);
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}
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}
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}
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/* Debug function used to dump the ARC information fount in arcextmap
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sections. */
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void
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dump_ARC_extmap (void)
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{
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struct ExtAuxRegister *r;
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int i;
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r = arc_extension_map.auxRegisters;
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while (r)
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{
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printf ("AUX : %s %u\n", r->name, r->address);
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r = r->next;
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}
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for (i = 0; i < INST_HASH_SIZE; i++)
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{
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struct ExtInstruction *insn;
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for (insn = arc_extension_map.instructions[i];
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insn != NULL; insn = insn->next)
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{
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printf ("INST: 0x%02x 0x%02x ", insn->major, insn->minor);
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switch (insn->flags & ARC_SYNTAX_MASK)
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{
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case ARC_SYNTAX_2OP:
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printf ("SYNTAX_2OP");
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break;
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case ARC_SYNTAX_3OP:
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printf ("SYNTAX_3OP");
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break;
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case ARC_SYNTAX_1OP:
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printf ("SYNTAX_1OP");
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break;
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case ARC_SYNTAX_NOP:
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printf ("SYNTAX_NOP");
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break;
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default:
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printf ("SYNTAX_UNK");
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break;
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}
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if (insn->flags & 0x10)
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printf ("|MODIFIER");
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printf (" %s\n", insn->name);
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}
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}
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for (i = 0; i < NUM_EXT_CORE; i++)
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{
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struct ExtCoreRegister reg = arc_extension_map.coreRegisters[i];
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if (reg.name)
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printf ("CORE: 0x%04x %s %s\n", reg.number,
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ExtReadWrite_image (reg.rw),
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reg.name);
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}
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for (i = 0; i < NUM_EXT_COND; i++)
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if (arc_extension_map.condCodes[i])
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printf ("COND: %s\n", arc_extension_map.condCodes[i]);
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}
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|
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/* For a given extension instruction generate the equivalent arc
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opcode structure. */
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|
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struct arc_opcode *
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arcExtMap_genOpcode (const extInstruction_t *einsn,
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unsigned arc_target,
|
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const char **errmsg)
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{
|
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struct arc_opcode *q, *arc_ext_opcodes = NULL;
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const unsigned char *lflags_f;
|
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const unsigned char *lflags_ccf;
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int count;
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|
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/* Check for the class to see how many instructions we generate. */
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switch (einsn->flags & ARC_SYNTAX_MASK)
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{
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case ARC_SYNTAX_3OP:
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count = (einsn->modsyn & ARC_OP1_MUST_BE_IMM) ? 10 : 20;
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break;
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case ARC_SYNTAX_2OP:
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count = (einsn->flags & 0x10) ? 7 : 6;
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break;
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case ARC_SYNTAX_1OP:
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count = 3;
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break;
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case ARC_SYNTAX_NOP:
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count = 1;
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break;
|
|
default:
|
|
count = 0;
|
|
break;
|
|
}
|
|
|
|
/* Allocate memory. */
|
|
arc_ext_opcodes = (struct arc_opcode *)
|
|
xmalloc ((count + 1) * sizeof (*arc_ext_opcodes));
|
|
|
|
if (arc_ext_opcodes == NULL)
|
|
{
|
|
*errmsg = "Virtual memory exhausted";
|
|
return NULL;
|
|
}
|
|
|
|
/* Generate the patterns. */
|
|
q = arc_ext_opcodes;
|
|
|
|
if (einsn->suffix)
|
|
{
|
|
lflags_f = flags_none;
|
|
lflags_ccf = flags_none;
|
|
}
|
|
else
|
|
{
|
|
lflags_f = flags_f;
|
|
lflags_ccf = flags_ccf;
|
|
}
|
|
|
|
if (einsn->suffix & ARC_SUFFIX_COND)
|
|
lflags_ccf = flags_cc;
|
|
if (einsn->suffix & ARC_SUFFIX_FLAG)
|
|
{
|
|
lflags_f = flags_f;
|
|
lflags_ccf = flags_f;
|
|
}
|
|
if (einsn->suffix & (ARC_SUFFIX_FLAG | ARC_SUFFIX_COND))
|
|
lflags_ccf = flags_ccf;
|
|
|
|
if (einsn->flags & ARC_SYNTAX_2OP
|
|
&& !(einsn->flags & 0x10))
|
|
{
|
|
/* Regular 2OP instruction. */
|
|
if (einsn->suffix & ARC_SUFFIX_COND)
|
|
*errmsg = "Suffix SUFFIX_COND ignored";
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN2OP_BC (einsn->major, einsn->minor), MINSN2OP_BC,
|
|
arc_target, arg_32bit_rbrc, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN2OP_0C (einsn->major, einsn->minor), MINSN2OP_0C,
|
|
arc_target, arg_32bit_zarc, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN2OP_BU (einsn->major, einsn->minor), MINSN2OP_BU,
|
|
arc_target, arg_32bit_rbu6, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN2OP_0U (einsn->major, einsn->minor), MINSN2OP_0U,
|
|
arc_target, arg_32bit_zau6, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN2OP_BL (einsn->major, einsn->minor), MINSN2OP_BL,
|
|
arc_target, arg_32bit_rblimm, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN2OP_0L (einsn->major, einsn->minor), MINSN2OP_0L,
|
|
arc_target, arg_32bit_zalimm, lflags_f);
|
|
}
|
|
else if (einsn->flags & (0x10 | ARC_SYNTAX_2OP))
|
|
{
|
|
/* This is actually a 3OP pattern. The first operand is
|
|
immplied and is set to zero. */
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0BC (einsn->major, einsn->minor), MINSN3OP_0BC,
|
|
arc_target, arg_32bit_rbrc, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0BU (einsn->major, einsn->minor), MINSN3OP_0BU,
|
|
arc_target, arg_32bit_rbu6, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0BL (einsn->major, einsn->minor), MINSN3OP_0BL,
|
|
arc_target, arg_32bit_rblimm, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_C0LC (einsn->major, einsn->minor), MINSN3OP_C0LC,
|
|
arc_target, arg_32bit_limmrc, lflags_ccf);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_C0LU (einsn->major, einsn->minor), MINSN3OP_C0LU,
|
|
arc_target, arg_32bit_limmu6, lflags_ccf);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0LS (einsn->major, einsn->minor), MINSN3OP_0LS,
|
|
arc_target, arg_32bit_limms12, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_C0LL (einsn->major, einsn->minor), MINSN3OP_C0LL,
|
|
arc_target, arg_32bit_limmlimm, lflags_ccf);
|
|
}
|
|
else if (einsn->flags & ARC_SYNTAX_3OP
|
|
&& !(einsn->modsyn & ARC_OP1_MUST_BE_IMM))
|
|
{
|
|
/* Regular 3OP instruction. */
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_ABC (einsn->major, einsn->minor), MINSN3OP_ABC,
|
|
arc_target, arg_32bit_rarbrc, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0BC (einsn->major, einsn->minor), MINSN3OP_0BC,
|
|
arc_target, arg_32bit_zarbrc, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_CBBC (einsn->major, einsn->minor), MINSN3OP_CBBC,
|
|
arc_target, arg_32bit_rbrbrc, lflags_ccf);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_ABU (einsn->major, einsn->minor), MINSN3OP_ABU,
|
|
arc_target, arg_32bit_rarbu6, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0BU (einsn->major, einsn->minor), MINSN3OP_0BU,
|
|
arc_target, arg_32bit_zarbu6, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_CBBU (einsn->major, einsn->minor), MINSN3OP_CBBU,
|
|
arc_target, arg_32bit_rbrbu6, lflags_ccf);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_BBS (einsn->major, einsn->minor), MINSN3OP_BBS,
|
|
arc_target, arg_32bit_rbrbs12, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_ALC (einsn->major, einsn->minor), MINSN3OP_ALC,
|
|
arc_target, arg_32bit_ralimmrc, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_ABL (einsn->major, einsn->minor), MINSN3OP_ABL,
|
|
arc_target, arg_32bit_rarblimm, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0LC (einsn->major, einsn->minor), MINSN3OP_0LC,
|
|
arc_target, arg_32bit_zalimmrc, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0BL (einsn->major, einsn->minor), MINSN3OP_0BL,
|
|
arc_target, arg_32bit_zarblimm, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_C0LC (einsn->major, einsn->minor), MINSN3OP_C0LC,
|
|
arc_target, arg_32bit_zalimmrc, lflags_ccf);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_CBBL (einsn->major, einsn->minor), MINSN3OP_CBBL,
|
|
arc_target, arg_32bit_rbrblimm, lflags_ccf);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_ALU (einsn->major, einsn->minor), MINSN3OP_ALU,
|
|
arc_target, arg_32bit_ralimmu6, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0LU (einsn->major, einsn->minor), MINSN3OP_0LU,
|
|
arc_target, arg_32bit_zalimmu6, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_C0LU (einsn->major, einsn->minor), MINSN3OP_C0LU,
|
|
arc_target, arg_32bit_zalimmu6, lflags_ccf);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0LS (einsn->major, einsn->minor), MINSN3OP_0LS,
|
|
arc_target, arg_32bit_zalimms12, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_ALL (einsn->major, einsn->minor), MINSN3OP_ALL,
|
|
arc_target, arg_32bit_ralimmlimm, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0LL (einsn->major, einsn->minor), MINSN3OP_0LL,
|
|
arc_target, arg_32bit_zalimmlimm, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_C0LL (einsn->major, einsn->minor), MINSN3OP_C0LL,
|
|
arc_target, arg_32bit_zalimmlimm, lflags_ccf);
|
|
}
|
|
else if (einsn->flags & ARC_SYNTAX_3OP)
|
|
{
|
|
/* 3OP instruction which accepts only zero as first
|
|
argument. */
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0BC (einsn->major, einsn->minor), MINSN3OP_0BC,
|
|
arc_target, arg_32bit_zarbrc, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0BU (einsn->major, einsn->minor), MINSN3OP_0BU,
|
|
arc_target, arg_32bit_zarbu6, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0LC (einsn->major, einsn->minor), MINSN3OP_0LC,
|
|
arc_target, arg_32bit_zalimmrc, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0BL (einsn->major, einsn->minor), MINSN3OP_0BL,
|
|
arc_target, arg_32bit_zarblimm, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_C0LC (einsn->major, einsn->minor), MINSN3OP_C0LC,
|
|
arc_target, arg_32bit_zalimmrc, lflags_ccf);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0LU (einsn->major, einsn->minor), MINSN3OP_0LU,
|
|
arc_target, arg_32bit_zalimmu6, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_C0LU (einsn->major, einsn->minor), MINSN3OP_C0LU,
|
|
arc_target, arg_32bit_zalimmu6, lflags_ccf);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0LS (einsn->major, einsn->minor), MINSN3OP_0LS,
|
|
arc_target, arg_32bit_zalimms12, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_0LL (einsn->major, einsn->minor), MINSN3OP_0LL,
|
|
arc_target, arg_32bit_zalimmlimm, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN3OP_C0LL (einsn->major, einsn->minor), MINSN3OP_C0LL,
|
|
arc_target, arg_32bit_zalimmlimm, lflags_ccf);
|
|
}
|
|
else if (einsn->flags & ARC_SYNTAX_1OP)
|
|
{
|
|
if (einsn->suffix & ARC_SUFFIX_COND)
|
|
*errmsg = "Suffix SUFFIX_COND ignored";
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN2OP (einsn->major, 0x3F) | FIELDB (einsn->minor),
|
|
MINSN2OP_0C, arc_target, arg_32bit_rc, lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN2OP (einsn->major, 0x3F) | FIELDB (einsn->minor)
|
|
| (0x01 << 22), MINSN2OP_0U, arc_target, arg_32bit_u6,
|
|
lflags_f);
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN2OP (einsn->major, 0x3F) | FIELDB (einsn->minor)
|
|
| FIELDC (62), MINSN2OP_0L, arc_target, arg_32bit_limm,
|
|
lflags_f);
|
|
|
|
}
|
|
else if (einsn->flags & ARC_SYNTAX_NOP)
|
|
{
|
|
if (einsn->suffix & ARC_SUFFIX_COND)
|
|
*errmsg = "Suffix SUFFIX_COND ignored";
|
|
|
|
INSERT_XOP (q, einsn->name,
|
|
INSN2OP (einsn->major, 0x3F) | FIELDB (einsn->minor)
|
|
| (0x01 << 22), MINSN2OP_0L, arc_target, arg_none, lflags_f);
|
|
}
|
|
else
|
|
{
|
|
*errmsg = "Unknown syntax";
|
|
return NULL;
|
|
}
|
|
|
|
/* End marker. */
|
|
memset (q, 0, sizeof (*arc_ext_opcodes));
|
|
|
|
return arc_ext_opcodes;
|
|
}
|