mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-23 10:03:47 +08:00
1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
128 lines
2.7 KiB
C
128 lines
2.7 KiB
C
/* RISC-V simulator.
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Copyright (C) 2005-2024 Free Software Foundation, Inc.
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Contributed by Mike Frysinger.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include "sim-main.h"
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#include "machs.h"
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static void
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riscv_model_init (SIM_CPU *cpu)
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{
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}
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static void
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riscv_init_cpu (SIM_CPU *cpu)
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{
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}
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static void
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riscv_prepare_run (SIM_CPU *cpu)
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{
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}
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static const SIM_MACH_IMP_PROPERTIES riscv_imp_properties =
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{
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sizeof (SIM_CPU),
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0,
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};
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#if WITH_TARGET_WORD_BITSIZE >= 32
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static const SIM_MACH rv32i_mach;
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static const SIM_MODEL rv32_models[] =
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{
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#define M(ext) { "RV32"#ext, &rv32i_mach, MODEL_RV32##ext, NULL, riscv_model_init },
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#include "model_list.def"
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#undef M
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{ 0, NULL, 0, NULL, NULL, }
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};
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static const SIM_MACH rv32i_mach =
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{
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"rv32i", "riscv:rv32", MACH_RV32I,
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32, 32, &rv32_models[0], &riscv_imp_properties,
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riscv_init_cpu,
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riscv_prepare_run
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};
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#endif
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#if WITH_TARGET_WORD_BITSIZE >= 64
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static const SIM_MACH rv64i_mach;
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static const SIM_MODEL rv64_models[] =
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{
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#define M(ext) { "RV64"#ext, &rv64i_mach, MODEL_RV64##ext, NULL, riscv_model_init },
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#include "model_list.def"
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#undef M
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{ 0, NULL, 0, NULL, NULL, }
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};
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static const SIM_MACH rv64i_mach =
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{
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"rv64i", "riscv:rv64", MACH_RV64I,
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64, 64, &rv64_models[0], &riscv_imp_properties,
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riscv_init_cpu,
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riscv_prepare_run
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};
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#endif
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#if WITH_TARGET_WORD_BITSIZE >= 128
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static const SIM_MACH rv128i_mach;
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static const SIM_MODEL rv128_models[] =
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{
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#define M(ext) { "RV128"#ext, &rv128i_mach, MODEL_RV128##ext, NULL, riscv_model_init },
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#include "model_list.def"
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#undef M
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{ 0, NULL, 0, NULL, NULL, }
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};
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static const SIM_MACH rv128i_mach =
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{
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"rv128i", "riscv:rv128", MACH_RV128I,
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128, 128, &rv128_models[0], &riscv_imp_properties,
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riscv_init_cpu,
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riscv_prepare_run
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};
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#endif
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/* Order matters here. */
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const SIM_MACH * const riscv_sim_machs[] =
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{
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#if WITH_TARGET_WORD_BITSIZE >= 128
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&rv128i_mach,
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#endif
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#if WITH_TARGET_WORD_BITSIZE >= 64
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&rv64i_mach,
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#endif
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#if WITH_TARGET_WORD_BITSIZE >= 32
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&rv32i_mach,
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#endif
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NULL
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};
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