mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-23 10:03:47 +08:00
cbdfef872b
I don't know what this emulation does exactly, but it missing a break statement seems kind of obvious based on the 32-bit case above it.
1066 lines
29 KiB
C
1066 lines
29 KiB
C
/* This file is part of the program psim.
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Copyright (C) 1994-1996, Andrew Cagney <cagney@highland.com.au>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _HW_PHB_C_
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#define _HW_PHB_C_
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#include "device_table.h"
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#include "hw_phb.h"
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#include "corefile.h"
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#include <stdlib.h>
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#include <ctype.h>
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/* DEVICE
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phb - PCI Host Bridge
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DESCRIPTION
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PHB implements a model of the PCI-host bridge described in the PPCP
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document.
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For bridge devices, Open Firmware specifies that the <<ranges>>
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property be used to specify the mapping of address spaces between a
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bridges parent and child busses. This PHB model configures itsself
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according to the information specified in its ranges property. The
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<<ranges>> property is described in detail in the Open Firmware
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documentation.
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For DMA transfers, any access to a PCI address space which falls
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outside of the mapped memory space is assumed to be a transfer
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intended for the parent bus.
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PROPERTIES
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ranges = <my-phys-addr> <parent-phys-addr> <my-size> ... (required)
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Define a number of mappings from the parent bus to one of this
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devices PCI busses. The exact format of the <<parent-phys-addr>>
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is parent bus dependant. The format of <<my-phys-addr>> is
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described in the Open Firmware PCI bindings document (note that the
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address must be non-relocatable).
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#address-cells = 3 (required)
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Number of cells used by an Open Firmware PCI address. This
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property must be defined before specifying the <<ranges>> property.
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#size-cells = 2 (required)
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Number of cells used by an Open Firmware PCI size. This property
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must be defined before specifying the <<ranges>> property.
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EXAMPLES
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Enable tracing:
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| $ psim \
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| -t phb-device \
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Since device tree entries that are specified on the command line
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are added before most of the device tree has been built it is often
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necessary to explictly add certain device properties and thus
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ensure they are already present in the device tree. For the
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<<phb>> one such property is parent busses <<#address-cells>>.
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| -o '/#address-cells 1' \
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Create the PHB remembering to include the cell size properties:
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| -o '/phb@0x80000000/#address-cells 3' \
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| -o '/phb@0x80000000/#size-cells 2' \
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Specify that the memory address range <<0x80000000>> to
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<<0x8fffffff>> should map directly onto the PCI memory address
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space while the processor address range <<0xc0000000>> to
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<<0xc000ffff>> should map onto the PCI I/O address range starting
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at location zero:
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| -o '/phb@0x80000000/ranges \
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| nm0,0,0,80000000 0x80000000 0x10000000 \
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| ni0,0,0,0 0xc0000000 0x10000' \
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Insert a 4k <<nvram>> into slot zero of the PCI bus. Have it
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directly accessible in both the I/O (address <<0x100>>) and memory
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(address 0x80001000) spaces:
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| -o '/phb@0x80000000/nvram@0/assigned-addresses \
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| nm0,0,10,80001000 4096 \
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| ni0,0,14,100 4096'
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| -o '/phb@0x80000000/nvram@0/reg \
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| 0 0 \
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| i0,0,14,0 4096'
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| -o '/phb@0x80000000/nvram@0/alternate-reg \
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| 0 0 \
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| m0,0,10,0 4096'
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The <<assigned-address>> property corresponding to what (if it were
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implemented) be found in the config base registers while the
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<<reg>> and <<alternative-reg>> properties indicating the location
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of registers within each address space.
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Of the possible addresses, only the non-relocatable versions are
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used when attaching the device to the bus.
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BUGS
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The implementation of the PCI configuration space is left as an
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exercise for the reader. Such a restriction should only impact on
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systems wanting to dynamically configure devices on the PCI bus.
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The <<CHRP>> document specfies additional (optional) functionality
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of the primary PHB. The implementation of such functionality is
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left as an exercise for the reader.
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The Open Firmware PCI bus bindings document (rev 1.6 and 2.0) is
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unclear on the value of the "ss" bits for a 64bit memory address.
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The correct value, as used by this module, is 0b11.
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The Open Firmware PCI bus bindings document (rev 1.6) suggests that
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the register field of non-relocatable PCI address should be zero.
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Unfortunatly, PCI addresses specified in the <<assigned-addresses>>
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property must be both non-relocatable and have non-zero register
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fields.
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The unit-decode method is not inserting a bus number into any
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address that it decodes. Instead the bus-number is left as zero.
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Support for aliased memory and I/O addresses is left as an exercise
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for the reader.
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Support for interrupt-ack and special cycles are left as an
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exercise for the reader. One issue to consider when attempting
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this exercise is how to specify the address of the int-ack and
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special cycle register. Hint: <</8259-interrupt-ackowledge>> is
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the wrong answer.
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Children of this node can only use the client callback interface
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when attaching themselves to the <<phb>>.
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REFERENCES
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http://playground.sun.com/1275/home.html#OFDbusPCI
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*/
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typedef struct _phb_space {
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core *map;
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core_map *readable;
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core_map *writeable;
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unsigned_word parent_base;
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int parent_space;
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unsigned_word my_base;
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int my_space;
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unsigned size;
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const char *name;
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} phb_space;
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typedef struct _hw_phb_device {
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phb_space space[nr_hw_phb_spaces];
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} hw_phb_device;
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static const char *
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hw_phb_decode_name(hw_phb_decode level)
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{
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switch (level) {
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case hw_phb_normal_decode: return "normal";
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case hw_phb_subtractive_decode: return "subtractive";
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case hw_phb_master_abort_decode: return "master-abort";
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default: return "invalid decode";
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}
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}
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static void
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hw_phb_init_address(device *me)
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{
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hw_phb_device *phb = device_data(me);
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/* check some basic properties */
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if (device_nr_address_cells(me) != 3)
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device_error(me, "incorrect #address-cells");
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if (device_nr_size_cells(me) != 2)
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device_error(me, "incorrect #size-cells");
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/* (re) initialize each PCI space */
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{
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hw_phb_spaces space_nr;
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for (space_nr = 0; space_nr < nr_hw_phb_spaces; space_nr++) {
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phb_space *pci_space = &phb->space[space_nr];
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core_init(pci_space->map);
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pci_space->size = 0;
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}
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}
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/* decode each of the ranges properties entering the information
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into the space table */
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{
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range_property_spec range;
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int ranges_entry;
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for (ranges_entry = 0;
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device_find_range_array_property(me, "ranges", ranges_entry,
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&range);
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ranges_entry++) {
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int my_attach_space;
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unsigned_word my_attach_address;
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int parent_attach_space;
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unsigned_word parent_attach_address;
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unsigned size;
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phb_space *pci_space;
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/* convert the addresses into something meaningful */
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device_address_to_attach_address(me, &range.child_address,
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&my_attach_space,
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&my_attach_address,
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me);
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device_address_to_attach_address(device_parent(me),
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&range.parent_address,
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&parent_attach_space,
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&parent_attach_address,
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me);
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device_size_to_attach_size(me, &range.size, &size, me);
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if (my_attach_space < 0 || my_attach_space >= nr_hw_phb_spaces)
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device_error(me, "ranges property contains an invalid address space");
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pci_space = &phb->space[my_attach_space];
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if (pci_space->size != 0)
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device_error(me, "ranges property contains duplicate mappings for %s address space",
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pci_space->name);
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pci_space->parent_base = parent_attach_address;
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pci_space->parent_space = parent_attach_space;
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pci_space->my_base = my_attach_address;
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pci_space->my_space = my_attach_space;
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pci_space->size = size;
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device_attach_address(device_parent(me),
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attach_callback,
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parent_attach_space, parent_attach_address, size,
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access_read_write_exec,
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me);
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DTRACE(phb, ("map %d:0x%lx to %s:0x%lx (0x%lx bytes)\n",
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(int)parent_attach_space,
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(unsigned long)parent_attach_address,
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pci_space->name,
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(unsigned long)my_attach_address,
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(unsigned long)size));
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}
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if (ranges_entry == 0) {
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device_error(me, "Missing or empty ranges property");
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}
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}
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}
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static void
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hw_phb_attach_address(device *me,
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attach_type type,
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int space,
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unsigned_word addr,
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unsigned nr_bytes,
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access_type access,
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device *client) /*callback/default*/
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{
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hw_phb_device *phb = device_data(me);
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phb_space *pci_space;
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hw_phb_decode phb_type = (hw_phb_decode)type;
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/* sanity checks */
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if (space < 0 || space >= nr_hw_phb_spaces)
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device_error(me, "attach space (%d) specified by %s invalid",
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space, device_path(client));
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pci_space = &phb->space[space];
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if (addr + nr_bytes > pci_space->my_base + pci_space->size
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|| addr < pci_space->my_base)
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device_error(me, "attach addr (0x%lx) specified by %s outside of bus address range",
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(unsigned long)addr, device_path(client));
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if (phb_type != hw_phb_normal_decode && phb_type != hw_phb_subtractive_decode)
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device_error(me, "attach type (%d) specified by %s invalid",
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type, device_path(client));
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/* attach it to the relevent bus */
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DTRACE(phb, ("attach %s - %s %s:0x%lx (0x%lx bytes)\n",
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device_path(client),
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hw_phb_decode_name(phb_type),
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pci_space->name,
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(unsigned long)addr,
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(unsigned long)nr_bytes));
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core_attach(pci_space->map,
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type,
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space,
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access,
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addr,
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nr_bytes,
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client);
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}
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/* Extract/set various fields from a PCI unit address.
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Note: only the least significant 32 bits of each cell is used.
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Note: for PPC MSB is 0 while for PCI it is 31. */
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/* relocatable bit n */
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static unsigned
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extract_n(const device_unit *address)
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{
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return EXTRACTED32(address->cells[0], 0, 0);
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}
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static void
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set_n(device_unit *address)
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{
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BLIT32(address->cells[0], 0, 1);
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}
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/* prefetchable bit p */
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static unsigned
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extract_p(const device_unit *address)
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{
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ASSERT(address->nr_cells == 3);
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return EXTRACTED32(address->cells[0], 1, 1);
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}
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static void
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set_p(device_unit *address)
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{
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BLIT32(address->cells[0], 1, 1);
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}
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/* aliased bit t */
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static unsigned
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extract_t(const device_unit *address)
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{
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ASSERT(address->nr_cells == 3);
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return EXTRACTED32(address->cells[0], 2, 2);
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}
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static void
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set_t(device_unit *address)
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{
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BLIT32(address->cells[0], 2, 1);
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}
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/* space code ss */
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typedef enum {
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ss_config_code = 0,
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ss_io_code = 1,
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ss_32bit_memory_code = 2,
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ss_64bit_memory_code = 3,
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} ss_type;
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static ss_type
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extract_ss(const device_unit *address)
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{
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ASSERT(address->nr_cells == 3);
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return EXTRACTED32(address->cells[0], 6, 7);
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}
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static void
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set_ss(device_unit *address, ss_type val)
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{
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MBLIT32(address->cells[0], 6, 7, val);
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}
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/* bus number bbbbbbbb */
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#if 0
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static unsigned
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extract_bbbbbbbb(const device_unit *address)
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{
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ASSERT(address->nr_cells == 3);
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return EXTRACTED32(address->cells[0], 8, 15);
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}
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#endif
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#if 0
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static void
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set_bbbbbbbb(device_unit *address, unsigned val)
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{
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MBLIT32(address->cells[0], 8, 15, val);
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}
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#endif
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/* device number ddddd */
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static unsigned
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extract_ddddd(const device_unit *address)
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{
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ASSERT(address->nr_cells == 3);
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return EXTRACTED32(address->cells[0], 16, 20);
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}
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static void
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set_ddddd(device_unit *address, unsigned val)
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{
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MBLIT32(address->cells[0], 16, 20, val);
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}
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/* function number fff */
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static unsigned
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extract_fff(const device_unit *address)
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{
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ASSERT(address->nr_cells == 3);
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return EXTRACTED32(address->cells[0], 21, 23);
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}
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static void
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set_fff(device_unit *address, unsigned val)
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{
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MBLIT32(address->cells[0], 21, 23, val);
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}
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/* register number rrrrrrrr */
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static unsigned
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extract_rrrrrrrr(const device_unit *address)
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{
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ASSERT(address->nr_cells == 3);
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return EXTRACTED32(address->cells[0], 24, 31);
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}
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static void
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set_rrrrrrrr(device_unit *address, unsigned val)
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{
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MBLIT32(address->cells[0], 24, 31, val);
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}
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/* MSW of 64bit address hh..hh */
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static unsigned
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extract_hh_hh(const device_unit *address)
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{
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ASSERT(address->nr_cells == 3);
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return address->cells[1];
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}
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static void
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set_hh_hh(device_unit *address, unsigned val)
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{
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address->cells[2] = val;
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}
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/* LSW of 64bit address ll..ll */
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static unsigned
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extract_ll_ll(const device_unit *address)
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{
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ASSERT(address->nr_cells == 3);
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return address->cells[2];
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}
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static void
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set_ll_ll(device_unit *address, unsigned val)
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{
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address->cells[2] = val;
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}
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/* Convert PCI textual bus address into a device unit */
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static int
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hw_phb_unit_decode(device *me,
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const char *unit,
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device_unit *address)
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{
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char *end = NULL;
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const char *chp = unit;
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unsigned long val;
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if (device_nr_address_cells(me) != 3)
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device_error(me, "PCI bus should have #address-cells == 3");
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memset(address, 0, sizeof(*address));
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if (unit == NULL)
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return 0;
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address->nr_cells = 3;
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if (isxdigit(*chp)) {
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set_ss(address, ss_config_code);
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}
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else {
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/* non-relocatable? */
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if (*chp == 'n') {
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set_n(address);
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chp++;
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}
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/* address-space? */
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if (*chp == 'i') {
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set_ss(address, ss_io_code);
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chp++;
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}
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else if (*chp == 'm') {
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set_ss(address, ss_32bit_memory_code);
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chp++;
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}
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else if (*chp == 'x') {
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set_ss(address, ss_64bit_memory_code);
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chp++;
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}
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else
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device_error(me, "Problem parsing PCI address %s", unit);
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/* possible alias */
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if (*chp == 't') {
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if (extract_ss(address) == ss_64bit_memory_code)
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device_error(me, "Invalid alias bit in PCI address %s", unit);
|
|
set_t(address);
|
|
chp++;
|
|
}
|
|
|
|
/* possible p */
|
|
if (*chp == 'p') {
|
|
if (extract_ss(address) != ss_32bit_memory_code)
|
|
device_error(me, "Invalid prefetchable bit (p) in PCI address %s",
|
|
unit);
|
|
set_p(address);
|
|
chp++;
|
|
}
|
|
|
|
}
|
|
|
|
/* required DD */
|
|
if (!isxdigit(*chp))
|
|
device_error(me, "Missing device number in PCI address %s", unit);
|
|
val = strtoul(chp, &end, 16);
|
|
if (chp == end)
|
|
device_error(me, "Problem parsing device number in PCI address %s", unit);
|
|
if ((val & 0x1f) != val)
|
|
device_error(me, "Device number (0x%lx) out of range (0..0x1f) in PCI address %s",
|
|
val, unit);
|
|
set_ddddd(address, val);
|
|
chp = end;
|
|
|
|
/* For config space, the F is optional */
|
|
if (extract_ss(address) == ss_config_code
|
|
&& (isspace(*chp) || *chp == '\0'))
|
|
return chp - unit;
|
|
|
|
/* function number F */
|
|
if (*chp != ',')
|
|
device_error(me, "Missing function number in PCI address %s", unit);
|
|
chp++;
|
|
val = strtoul(chp, &end, 10);
|
|
if (chp == end)
|
|
device_error(me, "Problem parsing function number in PCI address %s",
|
|
unit);
|
|
if ((val & 7) != val)
|
|
device_error(me, "Function number (%ld) out of range (0..7) in PCI address %s",
|
|
(long)val, unit);
|
|
set_fff(address, val);
|
|
chp = end;
|
|
|
|
/* for config space, must be end */
|
|
if (extract_ss(address) == ss_config_code) {
|
|
if (!isspace(*chp) && *chp != '\0')
|
|
device_error(me, "Problem parsing PCI config address %s",
|
|
unit);
|
|
return chp - unit;
|
|
}
|
|
|
|
/* register number RR */
|
|
if (*chp != ',')
|
|
device_error(me, "Missing register number in PCI address %s", unit);
|
|
chp++;
|
|
val = strtoul(chp, &end, 16);
|
|
if (chp == end)
|
|
device_error(me, "Problem parsing register number in PCI address %s",
|
|
unit);
|
|
switch (extract_ss(address)) {
|
|
case ss_io_code:
|
|
#if 0
|
|
if (extract_n(address) && val != 0)
|
|
device_error(me, "non-relocatable I/O register must be zero in PCI address %s", unit);
|
|
else if (!extract_n(address)
|
|
&& val != 0x10 && val != 0x14 && val != 0x18
|
|
&& val != 0x1c && val != 0x20 && val != 0x24)
|
|
device_error(me, "I/O register invalid in PCI address %s", unit);
|
|
#endif
|
|
break;
|
|
case ss_32bit_memory_code:
|
|
#if 0
|
|
if (extract_n(address) && val != 0)
|
|
device_error(me, "non-relocatable memory register must be zero in PCI address %s", unit);
|
|
else if (!extract_n(address)
|
|
&& val != 0x10 && val != 0x14 && val != 0x18
|
|
&& val != 0x1c && val != 0x20 && val != 0x24 && val != 0x30)
|
|
device_error(me, "I/O register (0x%lx) invalid in PCI address %s",
|
|
val, unit);
|
|
#endif
|
|
break;
|
|
case ss_64bit_memory_code:
|
|
if (extract_n(address) && val != 0)
|
|
device_error(me, "non-relocatable 32bit memory register must be zero in PCI address %s", unit);
|
|
else if (!extract_n(address)
|
|
&& val != 0x10 && val != 0x18 && val != 0x20)
|
|
device_error(me, "Register number (0x%lx) invalid in 64bit PCI address %s",
|
|
val, unit);
|
|
break;
|
|
case ss_config_code:
|
|
device_error(me, "internal error");
|
|
}
|
|
if ((val & 0xff) != val)
|
|
device_error(me, "Register number (0x%lx) out of range (0..0xff) in PCI address %s",
|
|
val, unit);
|
|
set_rrrrrrrr(address, val);
|
|
chp = end;
|
|
|
|
/* address */
|
|
if (*chp != ',')
|
|
device_error(me, "Missing address in PCI address %s", unit);
|
|
chp++;
|
|
switch (extract_ss(address)) {
|
|
case ss_io_code:
|
|
case ss_32bit_memory_code:
|
|
val = strtoul(chp, &end, 16);
|
|
if (chp == end)
|
|
device_error(me, "Problem parsing address in PCI address %s", unit);
|
|
switch (extract_ss(address)) {
|
|
case ss_io_code:
|
|
if (extract_n(address) && extract_t(address)
|
|
&& (val & 1024) != val)
|
|
device_error(me, "10bit aliased non-relocatable address (0x%lx) out of range in PCI address %s",
|
|
val, unit);
|
|
if (!extract_n(address) && extract_t(address)
|
|
&& (val & 0xffff) != val)
|
|
device_error(me, "64k relocatable address (0x%lx) out of range in PCI address %s",
|
|
val, unit);
|
|
break;
|
|
case ss_32bit_memory_code:
|
|
if (extract_t(address) && (val & 0xfffff) != val)
|
|
device_error(me, "1mb memory address (0x%lx) out of range in PCI address %s",
|
|
val, unit);
|
|
if (!extract_t(address) && (val & 0xffffffff) != val)
|
|
device_error(me, "32bit memory address (0x%lx) out of range in PCI address %s",
|
|
val, unit);
|
|
break;
|
|
case ss_64bit_memory_code:
|
|
case ss_config_code:
|
|
device_error(me, "internal error");
|
|
}
|
|
set_ll_ll(address, val);
|
|
chp = end;
|
|
break;
|
|
case ss_64bit_memory_code:
|
|
device_error(me, "64bit addresses unimplemented");
|
|
set_hh_hh(address, val);
|
|
set_ll_ll(address, val);
|
|
break;
|
|
case ss_config_code:
|
|
device_error(me, "internal error");
|
|
break;
|
|
}
|
|
|
|
/* finished? */
|
|
if (!isspace(*chp) && *chp != '\0')
|
|
device_error(me, "Problem parsing PCI address %s", unit);
|
|
|
|
return chp - unit;
|
|
}
|
|
|
|
|
|
/* Convert PCI device unit into its corresponding textual
|
|
representation */
|
|
|
|
static int
|
|
hw_phb_unit_encode(device *me,
|
|
const device_unit *unit_address,
|
|
char *buf,
|
|
int sizeof_buf)
|
|
{
|
|
if (unit_address->nr_cells != 3)
|
|
device_error(me, "Incorrect number of cells in PCI unit address");
|
|
if (device_nr_address_cells(me) != 3)
|
|
device_error(me, "PCI bus should have #address-cells == 3");
|
|
if (extract_ss(unit_address) == ss_config_code
|
|
&& extract_fff(unit_address) == 0
|
|
&& extract_rrrrrrrr(unit_address) == 0
|
|
&& extract_hh_hh(unit_address) == 0
|
|
&& extract_ll_ll(unit_address) == 0) {
|
|
/* DD - Configuration Space address */
|
|
sprintf(buf, "%x",
|
|
extract_ddddd(unit_address));
|
|
}
|
|
else if (extract_ss(unit_address) == ss_config_code
|
|
&& extract_fff(unit_address) != 0
|
|
&& extract_rrrrrrrr(unit_address) == 0
|
|
&& extract_hh_hh(unit_address) == 0
|
|
&& extract_ll_ll(unit_address) == 0) {
|
|
/* DD,F - Configuration Space */
|
|
sprintf(buf, "%x,%d",
|
|
extract_ddddd(unit_address),
|
|
extract_fff(unit_address));
|
|
}
|
|
else if (extract_ss(unit_address) == ss_io_code
|
|
&& extract_hh_hh(unit_address) == 0) {
|
|
/* [n]i[t]DD,F,RR,NNNNNNNN - 32bit I/O space */
|
|
sprintf(buf, "%si%s%x,%d,%x,%x",
|
|
extract_n(unit_address) ? "n" : "",
|
|
extract_t(unit_address) ? "t" : "",
|
|
extract_ddddd(unit_address),
|
|
extract_fff(unit_address),
|
|
extract_rrrrrrrr(unit_address),
|
|
extract_ll_ll(unit_address));
|
|
}
|
|
else if (extract_ss(unit_address) == ss_32bit_memory_code
|
|
&& extract_hh_hh(unit_address) == 0) {
|
|
/* [n]m[t][p]DD,F,RR,NNNNNNNN - 32bit memory space */
|
|
sprintf(buf, "%sm%s%s%x,%d,%x,%x",
|
|
extract_n(unit_address) ? "n" : "",
|
|
extract_t(unit_address) ? "t" : "",
|
|
extract_p(unit_address) ? "p" : "",
|
|
extract_ddddd(unit_address),
|
|
extract_fff(unit_address),
|
|
extract_rrrrrrrr(unit_address),
|
|
extract_ll_ll(unit_address));
|
|
}
|
|
else if (extract_ss(unit_address) == ss_32bit_memory_code) {
|
|
/* [n]x[p]DD,F,RR,NNNNNNNNNNNNNNNN - 64bit memory space */
|
|
sprintf(buf, "%sx%s%x,%d,%x,%x%08x",
|
|
extract_n(unit_address) ? "n" : "",
|
|
extract_p(unit_address) ? "p" : "",
|
|
extract_ddddd(unit_address),
|
|
extract_fff(unit_address),
|
|
extract_rrrrrrrr(unit_address),
|
|
extract_hh_hh(unit_address),
|
|
extract_ll_ll(unit_address));
|
|
}
|
|
else {
|
|
device_error(me, "Invalid PCI unit address 0x%08lx 0x%08lx 0x%08lx",
|
|
(unsigned long)unit_address->cells[0],
|
|
(unsigned long)unit_address->cells[1],
|
|
(unsigned long)unit_address->cells[2]);
|
|
}
|
|
if (strlen(buf) > sizeof_buf)
|
|
error("buffer overflow");
|
|
return strlen(buf);
|
|
}
|
|
|
|
|
|
static int
|
|
hw_phb_address_to_attach_address(device *me,
|
|
const device_unit *address,
|
|
int *attach_space,
|
|
unsigned_word *attach_address,
|
|
device *client)
|
|
{
|
|
if (address->nr_cells != 3)
|
|
device_error(me, "attach address has incorrect number of cells");
|
|
if (address->cells[1] != 0)
|
|
device_error(me, "64bit attach address unsupported");
|
|
|
|
/* directly decode the address/space */
|
|
*attach_address = address->cells[2];
|
|
switch (extract_ss(address)) {
|
|
case ss_config_code:
|
|
*attach_space = hw_phb_config_space;
|
|
break;
|
|
case ss_io_code:
|
|
*attach_space = hw_phb_io_space;
|
|
break;
|
|
case ss_32bit_memory_code:
|
|
case ss_64bit_memory_code:
|
|
*attach_space = hw_phb_memory_space;
|
|
break;
|
|
}
|
|
|
|
/* if non-relocatable finished */
|
|
if (extract_n(address))
|
|
return 1;
|
|
|
|
/* make memory and I/O addresses absolute */
|
|
if (*attach_space == hw_phb_io_space
|
|
|| *attach_space == hw_phb_memory_space) {
|
|
int reg_nr;
|
|
reg_property_spec assigned;
|
|
if (extract_ss(address) == ss_64bit_memory_code)
|
|
device_error(me, "64bit memory address not unsuported");
|
|
for (reg_nr = 0;
|
|
device_find_reg_array_property(client, "assigned-addresses", reg_nr,
|
|
&assigned);
|
|
reg_nr++) {
|
|
if (!extract_n(&assigned.address)
|
|
|| extract_rrrrrrrr(&assigned.address) == 0)
|
|
device_error(me, "client %s has invalid assigned-address property",
|
|
device_path(client));
|
|
if (extract_rrrrrrrr(address) == extract_rrrrrrrr(&assigned.address)) {
|
|
/* corresponding base register */
|
|
if (extract_ss(address) != extract_ss(&assigned.address))
|
|
device_error(me, "client %s has conflicting types for base register 0x%lx",
|
|
device_path(client),
|
|
(unsigned long)extract_rrrrrrrr(address));
|
|
*attach_address += assigned.address.cells[2];
|
|
return 0;
|
|
}
|
|
}
|
|
device_error(me, "client %s missing base address register 0x%lx in assigned-addresses property",
|
|
device_path(client),
|
|
(unsigned long)extract_rrrrrrrr(address));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int
|
|
hw_phb_size_to_attach_size(device *me,
|
|
const device_unit *size,
|
|
unsigned *nr_bytes,
|
|
device *client)
|
|
{
|
|
if (size->nr_cells != 2)
|
|
device_error(me, "size has incorrect number of cells");
|
|
if (size->cells[0] != 0)
|
|
device_error(me, "64bit size unsupported");
|
|
*nr_bytes = size->cells[1];
|
|
return size->cells[1];
|
|
}
|
|
|
|
|
|
static const phb_space *
|
|
find_phb_space(hw_phb_device *phb,
|
|
unsigned_word addr,
|
|
unsigned nr_bytes)
|
|
{
|
|
hw_phb_spaces space;
|
|
/* find the space that matches the address */
|
|
for (space = 0; space < nr_hw_phb_spaces; space++) {
|
|
phb_space *pci_space = &phb->space[space];
|
|
if (addr >= pci_space->parent_base
|
|
&& (addr + nr_bytes) <= (pci_space->parent_base + pci_space->size)) {
|
|
return pci_space;
|
|
}
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
|
|
static unsigned_word
|
|
map_phb_addr(const phb_space *space,
|
|
unsigned_word addr)
|
|
{
|
|
return addr - space->parent_base + space->my_base;
|
|
}
|
|
|
|
|
|
|
|
static unsigned
|
|
hw_phb_io_read_buffer(device *me,
|
|
void *dest,
|
|
int space,
|
|
unsigned_word addr,
|
|
unsigned nr_bytes,
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
hw_phb_device *phb = (hw_phb_device*)device_data(me);
|
|
const phb_space *pci_space = find_phb_space(phb, addr, nr_bytes);
|
|
unsigned_word bus_addr;
|
|
if (pci_space == NULL)
|
|
return 0;
|
|
bus_addr = map_phb_addr(pci_space, addr);
|
|
DTRACE(phb, ("io read - %d:0x%lx -> %s:0x%lx (%u bytes)\n",
|
|
space, (unsigned long)addr, pci_space->name, (unsigned long)bus_addr,
|
|
nr_bytes));
|
|
return core_map_read_buffer(pci_space->readable,
|
|
dest, bus_addr, nr_bytes);
|
|
}
|
|
|
|
|
|
static unsigned
|
|
hw_phb_io_write_buffer(device *me,
|
|
const void *source,
|
|
int space,
|
|
unsigned_word addr,
|
|
unsigned nr_bytes,
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
hw_phb_device *phb = (hw_phb_device*)device_data(me);
|
|
const phb_space *pci_space = find_phb_space(phb, addr, nr_bytes);
|
|
unsigned_word bus_addr;
|
|
if (pci_space == NULL)
|
|
return 0;
|
|
bus_addr = map_phb_addr(pci_space, addr);
|
|
DTRACE(phb, ("io write - %d:0x%lx -> %s:0x%lx (%u bytes)\n",
|
|
space, (unsigned long)addr, pci_space->name, (unsigned long)bus_addr,
|
|
nr_bytes));
|
|
return core_map_write_buffer(pci_space->writeable, source,
|
|
bus_addr, nr_bytes);
|
|
}
|
|
|
|
|
|
static unsigned
|
|
hw_phb_dma_read_buffer(device *me,
|
|
void *dest,
|
|
int space,
|
|
unsigned_word addr,
|
|
unsigned nr_bytes)
|
|
{
|
|
hw_phb_device *phb = (hw_phb_device*)device_data(me);
|
|
const phb_space *pci_space;
|
|
/* find the space */
|
|
if (space != hw_phb_memory_space)
|
|
device_error(me, "invalid dma address space %d", space);
|
|
pci_space = &phb->space[space];
|
|
/* check out the address */
|
|
if ((addr >= pci_space->my_base
|
|
&& addr <= pci_space->my_base + pci_space->size)
|
|
|| (addr + nr_bytes >= pci_space->my_base
|
|
&& addr + nr_bytes <= pci_space->my_base + pci_space->size))
|
|
device_error(me, "Do not support DMA into own bus");
|
|
/* do it */
|
|
DTRACE(phb, ("dma read - %s:0x%lx (%d bytes)\n",
|
|
pci_space->name, (unsigned long)addr, nr_bytes));
|
|
return device_dma_read_buffer(device_parent(me),
|
|
dest, pci_space->parent_space,
|
|
addr, nr_bytes);
|
|
}
|
|
|
|
|
|
static unsigned
|
|
hw_phb_dma_write_buffer(device *me,
|
|
const void *source,
|
|
int space,
|
|
unsigned_word addr,
|
|
unsigned nr_bytes,
|
|
int violate_read_only_section)
|
|
{
|
|
hw_phb_device *phb = (hw_phb_device*)device_data(me);
|
|
const phb_space *pci_space;
|
|
/* find the space */
|
|
if (space != hw_phb_memory_space)
|
|
device_error(me, "invalid dma address space %d", space);
|
|
pci_space = &phb->space[space];
|
|
/* check out the address */
|
|
if ((addr >= pci_space->my_base
|
|
&& addr <= pci_space->my_base + pci_space->size)
|
|
|| (addr + nr_bytes >= pci_space->my_base
|
|
&& addr + nr_bytes <= pci_space->my_base + pci_space->size))
|
|
device_error(me, "Do not support DMA into own bus");
|
|
/* do it */
|
|
DTRACE(phb, ("dma write - %s:0x%lx (%d bytes)\n",
|
|
pci_space->name, (unsigned long)addr, nr_bytes));
|
|
return device_dma_write_buffer(device_parent(me),
|
|
source, pci_space->parent_space,
|
|
addr, nr_bytes,
|
|
violate_read_only_section);
|
|
}
|
|
|
|
|
|
static device_callbacks const hw_phb_callbacks = {
|
|
{ hw_phb_init_address, },
|
|
{ hw_phb_attach_address, },
|
|
{ hw_phb_io_read_buffer, hw_phb_io_write_buffer },
|
|
{ hw_phb_dma_read_buffer, hw_phb_dma_write_buffer },
|
|
{ NULL, }, /* interrupt */
|
|
{ hw_phb_unit_decode,
|
|
hw_phb_unit_encode,
|
|
hw_phb_address_to_attach_address,
|
|
hw_phb_size_to_attach_size }
|
|
};
|
|
|
|
|
|
static void *
|
|
hw_phb_create(const char *name,
|
|
const device_unit *unit_address,
|
|
const char *args)
|
|
{
|
|
/* create the descriptor */
|
|
hw_phb_device *phb = ZALLOC(hw_phb_device);
|
|
|
|
/* create the core maps now */
|
|
hw_phb_spaces space_nr;
|
|
for (space_nr = 0; space_nr < nr_hw_phb_spaces; space_nr++) {
|
|
phb_space *pci_space = &phb->space[space_nr];
|
|
pci_space->map = core_create();
|
|
pci_space->readable = core_readable(pci_space->map);
|
|
pci_space->writeable = core_writeable(pci_space->map);
|
|
switch (space_nr) {
|
|
case hw_phb_memory_space:
|
|
pci_space->name = "memory";
|
|
break;
|
|
case hw_phb_io_space:
|
|
pci_space->name = "I/O";
|
|
break;
|
|
case hw_phb_config_space:
|
|
pci_space->name = "config";
|
|
break;
|
|
case hw_phb_special_space:
|
|
pci_space->name = "special";
|
|
break;
|
|
default:
|
|
error ("internal error");
|
|
break;
|
|
}
|
|
}
|
|
|
|
return phb;
|
|
}
|
|
|
|
|
|
const device_descriptor hw_phb_device_descriptor[] = {
|
|
{ "phb", hw_phb_create, &hw_phb_callbacks },
|
|
{ "pci", NULL, &hw_phb_callbacks },
|
|
{ NULL, },
|
|
};
|
|
|
|
#endif /* _HW_PHB_ */
|