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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
316 lines
7.8 KiB
C
316 lines
7.8 KiB
C
/* m32rx simulator support code
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Copyright (C) 1997-2024 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#define WANT_CPU m32rxf
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#define WANT_CPU_M32RXF
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#include "sim-main.h"
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#include "cgen-mem.h"
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#include "cgen-ops.h"
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#include "m32r-sim.h"
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/* The contents of BUF are in target byte order. */
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int
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m32rxf_fetch_register (SIM_CPU *current_cpu, int rn, void *buf, int len)
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{
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return m32rbf_fetch_register (current_cpu, rn, buf, len);
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}
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/* The contents of BUF are in target byte order. */
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int
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m32rxf_store_register (SIM_CPU *current_cpu, int rn, const void *buf, int len)
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{
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return m32rbf_store_register (current_cpu, rn, buf, len);
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}
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/* Cover fns to get/set the control registers.
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FIXME: Duplicated from m32r.c. The issue is structure offsets. */
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USI
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m32rxf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
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{
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switch (cr)
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{
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case H_CR_PSW : /* psw */
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return (((CPU (h_bpsw) & 0xc1) << 8)
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| ((CPU (h_psw) & 0xc0) << 0)
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| GET_H_COND ());
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case H_CR_BBPSW : /* backup backup psw */
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return CPU (h_bbpsw) & 0xc1;
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case H_CR_CBR : /* condition bit */
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return GET_H_COND ();
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case H_CR_SPI : /* interrupt stack pointer */
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if (! GET_H_SM ())
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return CPU (h_gr[H_GR_SP]);
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else
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return CPU (h_cr[H_CR_SPI]);
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case H_CR_SPU : /* user stack pointer */
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if (GET_H_SM ())
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return CPU (h_gr[H_GR_SP]);
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else
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return CPU (h_cr[H_CR_SPU]);
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case H_CR_BPC : /* backup pc */
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return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
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case H_CR_BBPC : /* backup backup pc */
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return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
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case 4 : /* ??? unspecified, but apparently available */
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case 5 : /* ??? unspecified, but apparently available */
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return CPU (h_cr[cr]);
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default :
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return 0;
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}
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}
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void
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m32rxf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
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{
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switch (cr)
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{
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case H_CR_PSW : /* psw */
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{
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int old_sm = (CPU (h_psw) & 0x80) != 0;
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int new_sm = (newval & 0x80) != 0;
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CPU (h_bpsw) = (newval >> 8) & 0xff;
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CPU (h_psw) = newval & 0xff;
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SET_H_COND (newval & 1);
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/* When switching stack modes, update the registers. */
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if (old_sm != new_sm)
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{
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if (old_sm)
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{
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/* Switching user -> system. */
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CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
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CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
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}
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else
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{
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/* Switching system -> user. */
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CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
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CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
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}
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}
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break;
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}
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case H_CR_BBPSW : /* backup backup psw */
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CPU (h_bbpsw) = newval & 0xff;
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break;
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case H_CR_CBR : /* condition bit */
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SET_H_COND (newval & 1);
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break;
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case H_CR_SPI : /* interrupt stack pointer */
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if (! GET_H_SM ())
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CPU (h_gr[H_GR_SP]) = newval;
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else
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CPU (h_cr[H_CR_SPI]) = newval;
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break;
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case H_CR_SPU : /* user stack pointer */
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if (GET_H_SM ())
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CPU (h_gr[H_GR_SP]) = newval;
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else
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CPU (h_cr[H_CR_SPU]) = newval;
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break;
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case H_CR_BPC : /* backup pc */
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CPU (h_cr[H_CR_BPC]) = newval;
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break;
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case H_CR_BBPC : /* backup backup pc */
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CPU (h_cr[H_CR_BBPC]) = newval;
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break;
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case 4 : /* ??? unspecified, but apparently available */
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case 5 : /* ??? unspecified, but apparently available */
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CPU (h_cr[cr]) = newval;
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break;
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default :
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/* ignore */
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break;
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}
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}
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/* Cover fns to access h-psw. */
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UQI
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m32rxf_h_psw_get_handler (SIM_CPU *current_cpu)
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{
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return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
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}
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void
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m32rxf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_psw) = newval;
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CPU (h_cond) = newval & 1;
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}
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/* Cover fns to access h-accum. */
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DI
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m32rxf_h_accum_get_handler (SIM_CPU *current_cpu)
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{
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/* Sign extend the top 8 bits. */
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DI r;
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r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
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r = XORDI (r, MAKEDI (0x800000, 0));
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r = SUBDI (r, MAKEDI (0x800000, 0));
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return r;
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}
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void
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m32rxf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
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{
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CPU (h_accum) = newval;
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}
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/* Cover fns to access h-accums. */
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DI
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m32rxf_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
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{
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/* FIXME: Yes, this is just a quick hack. */
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DI r;
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if (regno == 0)
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r = CPU (h_accum);
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else
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r = CPU (h_accums[1]);
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/* Sign extend the top 8 bits. */
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r = ANDDI (r, MAKEDI (0xffffff, 0xffffffff));
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r = XORDI (r, MAKEDI (0x800000, 0));
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r = SUBDI (r, MAKEDI (0x800000, 0));
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return r;
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}
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void
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m32rxf_h_accums_set_handler (SIM_CPU *current_cpu, UINT regno, DI newval)
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{
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/* FIXME: Yes, this is just a quick hack. */
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if (regno == 0)
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CPU (h_accum) = newval;
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else
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CPU (h_accums[1]) = newval;
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}
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#if WITH_PROFILE_MODEL_P
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/* Initialize cycle counting for an insn.
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FIRST_P is non-zero if this is the first insn in a set of parallel
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insns. */
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void
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m32rxf_model_insn_before (SIM_CPU *cpu, int first_p)
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{
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m32rbf_model_insn_before (cpu, first_p);
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}
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/* Record the cycles computed for an insn.
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LAST_P is non-zero if this is the last insn in a set of parallel insns,
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and we update the total cycle count.
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CYCLES is the cycle count of the insn. */
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void
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m32rxf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
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{
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m32rbf_model_insn_after (cpu, last_p, cycles);
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}
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static INLINE void
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check_load_stall (SIM_CPU *cpu, int regno)
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{
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UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
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if (regno != -1
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&& (h_gr & (1 << regno)) != 0)
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{
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CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
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if (TRACE_INSN_P (cpu))
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cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
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}
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}
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int
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m32rxf_model_m32rx_u_exec (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT sr, INT sr2, INT dr)
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{
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check_load_stall (cpu, sr);
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check_load_stall (cpu, sr2);
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return idesc->timing->units[unit_num].done;
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}
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int
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m32rxf_model_m32rx_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT src1, INT src2)
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{
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check_load_stall (cpu, src1);
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check_load_stall (cpu, src2);
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return idesc->timing->units[unit_num].done;
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}
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int
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m32rxf_model_m32rx_u_mac (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT src1, INT src2)
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{
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check_load_stall (cpu, src1);
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check_load_stall (cpu, src2);
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return idesc->timing->units[unit_num].done;
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}
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int
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m32rxf_model_m32rx_u_cti (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT sr)
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{
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PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
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int taken_p = (referenced & (1 << 1)) != 0;
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check_load_stall (cpu, sr);
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if (taken_p)
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{
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CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
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PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
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}
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else
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PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
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return idesc->timing->units[unit_num].done;
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}
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int
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m32rxf_model_m32rx_u_load (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT sr, INT dr)
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{
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CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
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return idesc->timing->units[unit_num].done;
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}
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int
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m32rxf_model_m32rx_u_store (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT src1, INT src2)
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{
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return idesc->timing->units[unit_num].done;
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}
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#endif /* WITH_PROFILE_MODEL_P */
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