mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-27 03:54:41 +08:00
1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
538 lines
15 KiB
C
538 lines
15 KiB
C
/* CPU family header for iq2000bf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2024 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef CPU_IQ2000BF_H
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#define CPU_IQ2000BF_H
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/* Maximum number of instructions that are fetched at a time.
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This is for LIW type instructions sets (e.g. m32r). */
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#define MAX_LIW_INSNS 1
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/* Maximum number of instructions that can be executed in parallel. */
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#define MAX_PARALLEL_INSNS 1
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/* The size of an "int" needed to hold an instruction word.
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This is usually 32 bits, but some architectures needs 64 bits. */
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typedef CGEN_INSN_INT CGEN_INSN_WORD;
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#include "cgen-engine.h"
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/* CPU state information. */
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typedef struct {
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/* Hardware elements. */
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struct {
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/* program counter */
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USI h_pc;
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#define GET_H_PC() get_h_pc (current_cpu)
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#define SET_H_PC(x) \
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do { \
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set_h_pc (current_cpu, (x));\
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;} while (0)
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/* General purpose registers */
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SI h_gr[32];
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#define GET_H_GR(index) (((index) == (0))) ? (0) : (CPU (h_gr[index]))
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#define SET_H_GR(index, x) \
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do { \
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if ((((index)) == (0))) {\
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((void) 0); /*nop*/\
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}\
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else {\
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CPU (h_gr[(index)]) = (x);\
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}\
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;} while (0)
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} hardware;
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#define CPU_CGEN_HW(cpu) (& IQ2000_SIM_CPU (cpu)->cpu_data.hardware)
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} IQ2000BF_CPU_DATA;
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/* Cover fns for register access. */
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USI iq2000bf_h_pc_get (SIM_CPU *);
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void iq2000bf_h_pc_set (SIM_CPU *, USI);
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SI iq2000bf_h_gr_get (SIM_CPU *, UINT);
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void iq2000bf_h_gr_set (SIM_CPU *, UINT, SI);
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/* These must be hand-written. */
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extern CPUREG_FETCH_FN iq2000bf_fetch_register;
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extern CPUREG_STORE_FN iq2000bf_store_register;
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typedef struct {
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int empty;
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} MODEL_IQ2000_DATA;
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/* Instruction argument buffer. */
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union sem_fields {
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struct { /* no operands */
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int empty;
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} sfmt_empty;
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struct { /* */
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IADDR i_jmptarg;
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} sfmt_j;
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struct { /* */
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IADDR i_offset;
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UINT f_rs;
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UINT f_rt;
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} sfmt_bbi;
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struct { /* */
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UINT f_imm;
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UINT f_rs;
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UINT f_rt;
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} sfmt_addi;
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struct { /* */
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UINT f_mask;
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UINT f_rd;
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UINT f_rs;
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UINT f_rt;
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} sfmt_mrgb;
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struct { /* */
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UINT f_maskl;
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UINT f_rd;
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UINT f_rs;
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UINT f_rt;
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UINT f_shamt;
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} sfmt_ram;
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#if WITH_SCACHE_PBB
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/* Writeback handler. */
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struct {
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/* Pointer to argbuf entry for insn whose results need writing back. */
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const struct argbuf *abuf;
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} write;
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/* x-before handler */
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struct {
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/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
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int first_p;
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} before;
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/* x-after handler */
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struct {
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int empty;
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} after;
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/* This entry is used to terminate each pbb. */
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struct {
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/* Number of insns in pbb. */
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int insn_count;
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/* Next pbb to execute. */
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SCACHE *next;
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SCACHE *branch_target;
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} chain;
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#endif
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};
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/* The ARGBUF struct. */
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struct argbuf {
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/* These are the baseclass definitions. */
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IADDR addr;
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const IDESC *idesc;
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char trace_p;
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char profile_p;
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/* ??? Temporary hack for skip insns. */
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char skip_count;
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char unused;
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/* cpu specific data follows */
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union sem semantic;
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int written;
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union sem_fields fields;
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};
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/* A cached insn.
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??? SCACHE used to contain more than just argbuf. We could delete the
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type entirely and always just use ARGBUF, but for future concerns and as
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a level of abstraction it is left in. */
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struct scache {
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struct argbuf argbuf;
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};
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/* Macros to simplify extraction, reading and semantic code.
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These define and assign the local vars that contain the insn's fields. */
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#define EXTRACT_IFMT_EMPTY_VARS \
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unsigned int length;
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#define EXTRACT_IFMT_EMPTY_CODE \
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length = 0; \
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#define EXTRACT_IFMT_ADD_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_rd; \
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UINT f_shamt; \
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UINT f_func; \
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unsigned int length;
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#define EXTRACT_IFMT_ADD_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
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f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
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#define EXTRACT_IFMT_ADDI_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_imm; \
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unsigned int length;
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#define EXTRACT_IFMT_ADDI_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
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#define EXTRACT_IFMT_RAM_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_rd; \
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UINT f_shamt; \
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UINT f_5; \
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UINT f_maskl; \
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unsigned int length;
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#define EXTRACT_IFMT_RAM_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
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f_5 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \
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f_maskl = EXTRACT_LSB0_UINT (insn, 32, 4, 5); \
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#define EXTRACT_IFMT_SLL_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_rd; \
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UINT f_shamt; \
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UINT f_func; \
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unsigned int length;
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#define EXTRACT_IFMT_SLL_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
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f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
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#define EXTRACT_IFMT_SLMV_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_rd; \
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UINT f_shamt; \
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UINT f_func; \
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unsigned int length;
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#define EXTRACT_IFMT_SLMV_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
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f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
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#define EXTRACT_IFMT_SLTI_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_imm; \
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unsigned int length;
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#define EXTRACT_IFMT_SLTI_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
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#define EXTRACT_IFMT_BBI_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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SI f_offset; \
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unsigned int length;
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#define EXTRACT_IFMT_BBI_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4)))); \
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#define EXTRACT_IFMT_BBV_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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SI f_offset; \
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unsigned int length;
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#define EXTRACT_IFMT_BBV_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4)))); \
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#define EXTRACT_IFMT_BGEZ_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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SI f_offset; \
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unsigned int length;
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#define EXTRACT_IFMT_BGEZ_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4)))); \
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#define EXTRACT_IFMT_JALR_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_rd; \
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UINT f_shamt; \
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UINT f_func; \
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unsigned int length;
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#define EXTRACT_IFMT_JALR_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
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f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
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#define EXTRACT_IFMT_JR_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_rd; \
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UINT f_shamt; \
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UINT f_func; \
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unsigned int length;
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#define EXTRACT_IFMT_JR_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
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f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
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#define EXTRACT_IFMT_LB_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_imm; \
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unsigned int length;
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#define EXTRACT_IFMT_LB_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
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#define EXTRACT_IFMT_LUI_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_imm; \
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unsigned int length;
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#define EXTRACT_IFMT_LUI_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
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#define EXTRACT_IFMT_BREAK_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_rd; \
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UINT f_shamt; \
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UINT f_func; \
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unsigned int length;
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#define EXTRACT_IFMT_BREAK_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
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f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
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#define EXTRACT_IFMT_SYSCALL_VARS \
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UINT f_opcode; \
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UINT f_excode; \
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UINT f_func; \
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unsigned int length;
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#define EXTRACT_IFMT_SYSCALL_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_excode = EXTRACT_LSB0_UINT (insn, 32, 25, 20); \
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f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
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#define EXTRACT_IFMT_ANDOUI_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_imm; \
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unsigned int length;
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#define EXTRACT_IFMT_ANDOUI_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
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#define EXTRACT_IFMT_MRGB_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_rd; \
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UINT f_10; \
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UINT f_mask; \
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UINT f_func; \
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unsigned int length;
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#define EXTRACT_IFMT_MRGB_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_10 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \
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f_mask = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
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f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
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#define EXTRACT_IFMT_BC0F_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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SI f_offset; \
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unsigned int length;
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#define EXTRACT_IFMT_BC0F_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4)))); \
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#define EXTRACT_IFMT_CFC0_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_rd; \
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UINT f_10_11; \
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unsigned int length;
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#define EXTRACT_IFMT_CFC0_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
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#define EXTRACT_IFMT_CHKHDR_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_rd; \
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UINT f_shamt; \
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UINT f_func; \
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unsigned int length;
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#define EXTRACT_IFMT_CHKHDR_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
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f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
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#define EXTRACT_IFMT_LULCK_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_rd; \
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UINT f_shamt; \
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UINT f_func; \
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unsigned int length;
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#define EXTRACT_IFMT_LULCK_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
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f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
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#define EXTRACT_IFMT_PKRLR1_VARS \
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UINT f_opcode; \
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UINT f_rs; \
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UINT f_rt; \
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UINT f_count; \
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UINT f_index; \
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unsigned int length;
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#define EXTRACT_IFMT_PKRLR1_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_count = EXTRACT_LSB0_UINT (insn, 32, 15, 7); \
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f_index = EXTRACT_LSB0_UINT (insn, 32, 8, 9); \
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#define EXTRACT_IFMT_RFE_VARS \
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UINT f_opcode; \
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UINT f_25; \
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UINT f_24_19; \
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UINT f_func; \
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unsigned int length;
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#define EXTRACT_IFMT_RFE_CODE \
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length = 4; \
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|
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_25 = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
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f_24_19 = EXTRACT_LSB0_UINT (insn, 32, 24, 19); \
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f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
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#define EXTRACT_IFMT_J_VARS \
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UINT f_opcode; \
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UINT f_rsrvd; \
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USI f_jtarg; \
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unsigned int length;
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#define EXTRACT_IFMT_J_CODE \
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length = 4; \
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|
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_rsrvd = EXTRACT_LSB0_UINT (insn, 32, 25, 10); \
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f_jtarg = ((((pc) & (0xf0000000))) | (((EXTRACT_LSB0_UINT (insn, 32, 15, 16)) << (2)))); \
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/* Collection of various things for the trace handler to use. */
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typedef struct trace_record {
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IADDR pc;
|
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/* FIXME:wip */
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} TRACE_RECORD;
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#endif /* CPU_IQ2000BF_H */
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