mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-30 05:23:49 +08:00
1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
398 lines
11 KiB
C
398 lines
11 KiB
C
/* The common simulator framework for GDB, the GNU Debugger.
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Copyright 2002-2024 Free Software Foundation, Inc.
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Contributed by Andrew Cagney and Red Hat.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef N
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#error "N must be #defined"
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#endif
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#ifndef M
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#define M N
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#endif
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/* N: The number of bytes of data to transfer.
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M: The number of bytes in the type used to transfer the data */
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#if (N > M)
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#error "N (nr bytes of data) must be <= M (nr of bytes in data type)"
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#endif
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#include "symcat.h"
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/* NOTE: see end of file for #undef of these macros */
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#define unsigned_M XCONCAT2(unsigned_,M)
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#define T2H_M XCONCAT2(T2H_,M)
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#define H2T_M XCONCAT2(H2T_,M)
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#define SWAP_M XCONCAT2(SWAP_,M)
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#define sim_core_read_aligned_N XCONCAT2(sim_core_read_aligned_,N)
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#define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N)
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#define sim_core_read_misaligned_N XCONCAT2(sim_core_read_misaligned_,N)
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#define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N)
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#define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
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#define sim_core_write_misaligned_N XCONCAT2(sim_core_write_misaligned_,N)
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#define sim_core_trace_M XCONCAT2(sim_core_trace_,M)
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#define sim_core_dummy_M XCONCAT2(sim_core_dummy_,M)
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#if (M == N && N > 1)
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/* dummy variable used as a return value when nothing else is
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available and the compiler is complaining */
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static unsigned_M sim_core_dummy_M;
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#endif
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/* TAGS: sim_core_trace_1 sim_core_trace_2 */
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/* TAGS: sim_core_trace_4 sim_core_trace_8 */
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/* TAGS: sim_core_trace_16 */
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#if (M == N)
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STATIC_SIM_CORE(void)
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sim_core_trace_M (sim_cpu *cpu,
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sim_cia cia,
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int line_nr,
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transfer_type type,
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unsigned map,
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address_word addr,
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unsigned_M val,
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int nr_bytes)
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{
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const char *transfer = (type == read_transfer ? "read" : "write");
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const char *direction = (type == read_transfer ? "->" : "<-");
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if (TRACE_DEBUG_P (cpu))
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trace_printf (CPU_STATE (cpu), cpu, "sim-n-core.h:%d: ", line_nr);
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#if (M == 16)
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trace_printf (CPU_STATE (cpu), cpu,
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"%s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx\n",
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transfer, nr_bytes,
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map_to_str (map),
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(unsigned long) addr,
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direction,
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(unsigned long) V4_16 (val, 0),
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(unsigned long) V4_16 (val, 1),
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(unsigned long) V4_16 (val, 2),
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(unsigned long) V4_16 (val, 3));
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#endif
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#if (M == 8)
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trace_printf (CPU_STATE (cpu), cpu,
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"%s-%d %s:0x%08lx %s 0x%08lx%08lx\n",
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transfer, nr_bytes,
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map_to_str (map),
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(unsigned long) addr,
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direction,
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(unsigned long) V4_8 (val, 0),
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(unsigned long) V4_8 (val, 1));
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#endif
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#if (M == 4)
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trace_printf (CPU_STATE (cpu), cpu,
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"%s-%d %s:0x%08lx %s 0x%08lx\n",
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transfer,
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nr_bytes,
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map_to_str (map),
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(unsigned long) addr,
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direction,
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(unsigned long) val);
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#endif
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#if (M == 2)
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trace_printf (CPU_STATE (cpu), cpu,
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"%s-%d %s:0x%08lx %s 0x%04lx\n",
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transfer,
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nr_bytes,
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map_to_str (map),
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(unsigned long) addr,
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direction,
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(unsigned long) val);
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#endif
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#if (M == 1)
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trace_printf (CPU_STATE (cpu), cpu,
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"%s-%d %s:0x%08lx %s 0x%02lx\n",
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transfer,
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nr_bytes,
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map_to_str (map),
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(unsigned long) addr,
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direction,
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(unsigned long) val);
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#endif
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}
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#endif
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/* TAGS: sim_core_read_aligned_1 sim_core_read_aligned_2 */
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/* TAGS: sim_core_read_aligned_4 sim_core_read_aligned_8 */
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/* TAGS: sim_core_read_aligned_16 */
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#if (M == N)
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INLINE_SIM_CORE(unsigned_M)
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sim_core_read_aligned_N(sim_cpu *cpu,
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sim_cia cia,
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unsigned map,
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address_word xaddr)
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{
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sim_cpu_core *cpu_core = CPU_CORE (cpu);
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sim_core_common *core = &cpu_core->common;
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unsigned_M val;
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sim_core_mapping *mapping;
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address_word addr;
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#if WITH_XOR_ENDIAN != 0
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if (WITH_XOR_ENDIAN)
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addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
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else
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#endif
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addr = xaddr;
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mapping = sim_core_find_mapping (core, map, addr, N, read_transfer, 1 /*abort*/, cpu, cia);
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do
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{
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#if (WITH_HW)
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if (mapping->device != NULL)
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{
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unsigned_M data;
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sim_cpu_hw_io_read_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N);
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val = T2H_M (data);
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break;
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}
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#endif
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val = T2H_M (*(unsigned_M*) sim_core_translate (mapping, addr));
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}
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while (0);
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PROFILE_COUNT_CORE (cpu, addr, N, map);
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if (TRACE_P (cpu, TRACE_CORE_IDX))
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sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
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return val;
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}
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#endif
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/* TAGS: sim_core_read_unaligned_1 sim_core_read_unaligned_2 */
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/* TAGS: sim_core_read_unaligned_4 sim_core_read_unaligned_8 */
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/* TAGS: sim_core_read_unaligned_16 */
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#if (M == N && N > 1)
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INLINE_SIM_CORE(unsigned_M)
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sim_core_read_unaligned_N(sim_cpu *cpu,
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sim_cia cia,
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unsigned map,
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address_word addr)
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{
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int alignment = N - 1;
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/* if hardwired to forced alignment just do it */
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if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
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return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
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else if ((addr & alignment) == 0)
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return sim_core_read_aligned_N (cpu, cia, map, addr);
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else
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switch (CURRENT_ALIGNMENT)
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{
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case STRICT_ALIGNMENT:
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SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
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read_transfer, sim_core_unaligned_signal);
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case NONSTRICT_ALIGNMENT:
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{
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unsigned_M val;
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if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
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SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
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read_transfer, sim_core_unaligned_signal);
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val = T2H_M(val);
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PROFILE_COUNT_CORE (cpu, addr, N, map);
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if (TRACE_P (cpu, TRACE_CORE_IDX))
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sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
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return val;
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}
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case FORCED_ALIGNMENT:
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return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
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case MIXED_ALIGNMENT:
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sim_engine_abort (CPU_STATE (cpu), cpu, cia,
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"internal error - %s - mixed alignment",
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XSTRING (sim_core_read_unaligned_N));
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default:
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sim_engine_abort (CPU_STATE (cpu), cpu, cia,
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"internal error - %s - bad switch",
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XSTRING (sim_core_read_unaligned_N));
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/* to keep some compilers happy, we return a dummy */
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return sim_core_dummy_M;
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}
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}
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#endif
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/* TAGS: sim_core_read_misaligned_3 sim_core_read_misaligned_5 */
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/* TAGS: sim_core_read_misaligned_6 sim_core_read_misaligned_7 */
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#if (M != N)
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INLINE_SIM_CORE(unsigned_M)
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sim_core_read_misaligned_N(sim_cpu *cpu,
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sim_cia cia,
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unsigned map,
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address_word addr)
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{
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unsigned_M val = 0;
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if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
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SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
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read_transfer, sim_core_unaligned_signal);
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if (HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
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val = SWAP_M (val);
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if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
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val >>= (M - N) * 8;
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PROFILE_COUNT_CORE (cpu, addr, N, map);
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if (TRACE_P (cpu, TRACE_CORE_IDX))
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sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
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return val;
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}
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#endif
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/* TAGS: sim_core_write_aligned_1 sim_core_write_aligned_2 */
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/* TAGS: sim_core_write_aligned_4 sim_core_write_aligned_8 */
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/* TAGS: sim_core_write_aligned_16 */
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#if (M == N)
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INLINE_SIM_CORE(void)
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sim_core_write_aligned_N(sim_cpu *cpu,
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sim_cia cia,
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unsigned map,
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address_word xaddr,
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unsigned_M val)
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{
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sim_cpu_core *cpu_core = CPU_CORE (cpu);
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sim_core_common *core = &cpu_core->common;
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sim_core_mapping *mapping;
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address_word addr;
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#if WITH_XOR_ENDIAN != 0
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if (WITH_XOR_ENDIAN)
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addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
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else
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#endif
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addr = xaddr;
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mapping = sim_core_find_mapping (core, map, addr, N, write_transfer, 1 /*abort*/, cpu, cia);
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do
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{
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#if (WITH_HW)
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if (mapping->device != NULL)
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{
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unsigned_M data = H2T_M (val);
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sim_cpu_hw_io_write_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N);
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break;
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}
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#endif
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*(unsigned_M*) sim_core_translate (mapping, addr) = H2T_M (val);
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}
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while (0);
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PROFILE_COUNT_CORE (cpu, addr, N, map);
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if (TRACE_P (cpu, TRACE_CORE_IDX))
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sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
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}
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#endif
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/* TAGS: sim_core_write_unaligned_1 sim_core_write_unaligned_2 */
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/* TAGS: sim_core_write_unaligned_4 sim_core_write_unaligned_8 */
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/* TAGS: sim_core_write_unaligned_16 */
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#if (M == N && N > 1)
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INLINE_SIM_CORE(void)
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sim_core_write_unaligned_N(sim_cpu *cpu,
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sim_cia cia,
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unsigned map,
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address_word addr,
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unsigned_M val)
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{
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int alignment = N - 1;
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/* if hardwired to forced alignment just do it */
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if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
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sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
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else if ((addr & alignment) == 0)
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sim_core_write_aligned_N (cpu, cia, map, addr, val);
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else
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switch (CURRENT_ALIGNMENT)
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{
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case STRICT_ALIGNMENT:
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SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
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write_transfer, sim_core_unaligned_signal);
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break;
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case NONSTRICT_ALIGNMENT:
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{
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unsigned_M data = H2T_M (val);
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if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
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SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
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write_transfer, sim_core_unaligned_signal);
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PROFILE_COUNT_CORE (cpu, addr, N, map);
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if (TRACE_P (cpu, TRACE_CORE_IDX))
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sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
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break;
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}
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case FORCED_ALIGNMENT:
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sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
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break;
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case MIXED_ALIGNMENT:
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sim_engine_abort (CPU_STATE (cpu), cpu, cia,
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"internal error - %s - mixed alignment",
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XSTRING (sim_core_write_unaligned_N));
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break;
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default:
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sim_engine_abort (CPU_STATE (cpu), cpu, cia,
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"internal error - %s - bad switch",
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XSTRING (sim_core_write_unaligned_N));
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break;
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}
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}
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#endif
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/* TAGS: sim_core_write_misaligned_3 sim_core_write_misaligned_5 */
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/* TAGS: sim_core_write_misaligned_6 sim_core_write_misaligned_7 */
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#if (M != N)
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INLINE_SIM_CORE(void)
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sim_core_write_misaligned_N(sim_cpu *cpu,
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sim_cia cia,
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unsigned map,
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address_word addr,
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unsigned_M val)
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{
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unsigned_M data = val;
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if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
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data <<= (M - N) * 8;
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if (HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
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data = SWAP_M (data);
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if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
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SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
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write_transfer, sim_core_unaligned_signal);
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PROFILE_COUNT_CORE (cpu, addr, N, map);
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if (TRACE_P (cpu, TRACE_CORE_IDX))
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sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
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}
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#endif
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/* NOTE: see start of file for #define of these macros */
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#undef unsigned_M
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#undef T2H_M
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#undef H2T_M
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#undef SWAP_M
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#undef sim_core_read_aligned_N
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#undef sim_core_read_unaligned_N
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#undef sim_core_read_misaligned_N
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#undef sim_core_write_aligned_N
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#undef sim_core_write_unaligned_N
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#undef sim_core_write_misaligned_N
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#undef sim_core_trace_M
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#undef sim_core_dummy_M
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#undef M
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#undef N
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