mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-23 10:03:47 +08:00
1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
102 lines
3.2 KiB
C
102 lines
3.2 KiB
C
/* Blackfin device support.
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Copyright (C) 2010-2024 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include "sim-main.h"
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#include "sim-hw.h"
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#include "hw-device.h"
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#include "devices.h"
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#include "dv-bfin_cec.h"
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#include "dv-bfin_mmu.h"
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static void
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bfin_mmr_invalid (struct hw *me, address_word addr,
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unsigned nr_bytes, bool write, bool missing)
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{
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SIM_CPU *cpu = hw_system_cpu (me);
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const char *rw = write ? "write" : "read";
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const char *reason =
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missing ? "no such register" :
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(addr & 3) ? "must be 32-bit aligned" : "invalid length";
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/* Only throw a fit if the cpu is doing the access. DMA/GDB simply
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go unnoticed. Not exactly hardware behavior, but close enough. */
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if (!cpu)
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{
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sim_io_eprintf (hw_system (me),
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"%s: invalid MMR %s at %#x length %u: %s\n",
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hw_path (me), rw, addr, nr_bytes, reason);
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return;
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}
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HW_TRACE ((me, "invalid MMR %s at %#x length %u: %s",
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rw, addr, nr_bytes, reason));
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/* XXX: is this what hardware does ? What about priority of unaligned vs
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wrong length vs missing register ? What about system-vs-core ? */
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/* XXX: We should move this addr check to a model property so we get the
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same behavior regardless of where we map the model. */
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if (addr >= BFIN_CORE_MMR_BASE)
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/* XXX: This should be setting up CPLB fault addrs ? */
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mmu_process_fault (cpu, addr, write, false, false, true);
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else
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/* XXX: Newer parts set up an interrupt from EBIU and program
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EBIU_ERRADDR with the address. */
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cec_hwerr (cpu, HWERR_SYSTEM_MMR);
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}
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void
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dv_bfin_mmr_invalid (struct hw *me, address_word addr, unsigned nr_bytes,
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bool write)
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{
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bfin_mmr_invalid (me, addr, nr_bytes, write, true);
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}
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bool
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dv_bfin_mmr_require (struct hw *me, address_word addr, unsigned nr_bytes,
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unsigned size, bool write)
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{
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if ((addr & 0x3) == 0 && nr_bytes == size)
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return true;
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bfin_mmr_invalid (me, addr, nr_bytes, write, false);
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return false;
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}
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/* For 32-bit memory mapped registers that allow 16-bit or 32-bit access. */
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bool
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dv_bfin_mmr_require_16_32 (struct hw *me, address_word addr, unsigned nr_bytes,
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bool write)
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{
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if ((addr & 0x3) == 0 && (nr_bytes == 2 || nr_bytes == 4))
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return true;
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bfin_mmr_invalid (me, addr, nr_bytes, write, false);
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return false;
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}
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unsigned int dv_get_bus_num (struct hw *me)
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{
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const hw_unit *unit = hw_unit_address (me);
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return unit->cells[unit->nr_cells - 1];
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}
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