Commit Graph

3036 Commits

Author SHA1 Message Date
Tamar Christina
f7dd2fb2e2 Arm: Backport hlt to all architectures.
The software trap instruction HLT that was introduced in Armv8-a is used
as the semihosting trap instruction in AArch64.  In order to allow systems
configured to run AArch64 code to also run AArch32 with semihosting it was
decided that AArch32 should also use HLT in the case of the "mixed mode"
environment.  This requires that HLT also be backported to all earlier
architectures.  The instruction is in the undefined encoding space earlier
architectures but must trigger a semihosting trap [3].

The Arm Architectural Reference Manual [1] doesn't explicitly mention this
however this is an explicit requirement in the Semihosting-v2 protocol [2].

[1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
[2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface
[3] 19a6e31c9d

gas/ChangeLog:

	* config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
	hlt to armv1.
	* testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs
	* testsuite/gas/arm/hlt.d: New test.
	* testsuite/gas/arm/hlt.s: New test.

opcodes/ChangeLog:

	* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2019-02-07 17:20:41 +00:00
Tamar Christina
6456d318aa AArch64: Add verifier for By elem Single and Double sized instructions.
The AArch64 instruction set has cut-outs inside instructions encodings for
when a given encoding that would normally fall within the encoding space of
an instruction is instead undefined.

This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case
where sz:L == 11.

gas/ChangeLog:

	PR binutils/23212
	* testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test.
	* testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test.

opcodes/ChangeLog:

	PR binutils/23212
	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
	* aarch64-opc.c (verify_elem_sd): New.
	(fields): Add FLD_sz entr.
	* aarch64-tbl.h (_SIMD_INSN): New.
	(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
	fmulx scalar and vector by element isns.
2019-02-07 16:56:35 +00:00
Nick Clifton
4a83b61091 Updated Swedish translation for the opcodes sub-directory 2019-02-07 14:49:38 +00:00
Andreas Krebbel
fc60b8c806 S/390: Implement instruction set extensions
opcodes/ChangeLog:

2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	* s390-mkopc.c (main): Accept arch13 as cpu string.
	* s390-opc.c: Add new instruction formats and instruction opcode
	masks.
	* s390-opc.txt: Add new arch13 instructions.

include/ChangeLog:

2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	* opcode/s390.h (enum s390_opcode_cpu_val): Add
	S390_OPCODE_ARCH13.

gas/ChangeLog:

2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	* config/tc-s390.c (s390_parse_cpu): New entry for arch13.
	* doc/c-s390.texi: Document arch13 march option.
	* testsuite/gas/s390/s390.exp: Run the arch13 related tests.
	* testsuite/gas/s390/zarch-arch13.d: New test.
	* testsuite/gas/s390/zarch-arch13.s: New test.
	* testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics
	also for z13.
2019-01-31 17:32:18 +01:00
Tamar Christina
e10620d3b9 AArch64: Add missing changelog for Update encodings for stg, st2g, stzg and st2zg 2019-01-25 15:50:01 +00:00
Sudi Das
20a4ca5524 AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.
This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch adds the new STZGM instruction.

STGZM Xt, [<Xn|SP>]

Committed on behalf of Sudakshina Das.

*** gas/ChangeLog ***

	* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** opcodes/ChangeLog ***

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2019-01-25 14:49:52 +00:00
Sudi Das
550fd7bf68 AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension.
This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV
instructions. These instructions needed special infrastructure to support
[base]! style for addressing mode. That is also removed now.

Committed on behalf of Sudakshina Das.

*** gas/ChangeLog ***

	* config/tc-aarch64.c (parse_address_main): Remove support for
	[base]! address expression.
	(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
	(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
	and stgv.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** include/ChangeLog ***

	* opcode/aarch64.h (enum aarch64_opnd): Remove
	AARCH64_OPND_ADDR_SIMPLE_2.
	(enum aarch64_insn_class): Remove ldstgv_indexed.

*** opcodes/ChangeLog ***

	* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
	* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
	* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
	* aarch64-dis.h (ext_addr_simple_2): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Remove
	case for ldstgv_indexed.
	(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
	* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
	(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
2019-01-25 14:49:51 +00:00
Nick Clifton
d99386305c Updated translations for some of the binutils subdirectory. 2019-01-23 10:26:54 +00:00
Nick Clifton
375cd4233d Updated translations for various binutils subdirectories. 2019-01-21 12:59:20 +00:00
Chenghua Xu
57299f4831 [MIPS] fix typo in mips_arch_choices.
opcodes/
	* mips-dis.c (mips_arch_choices): Fix typo in
	gs464, gs464e and gs264e descriptors.
2019-01-20 02:36:40 +00:00
Nick Clifton
f48dfe417e Change version to 2.32.51 and regenerate configure and pot files. 2019-01-19 16:51:42 +00:00
Nick Clifton
f974f26cb1 Add markers for 2.32 branch to NEWS and ChangeLog files. 2019-01-19 15:55:50 +00:00
John Darrington
448b8ca865 S12Z: Don't crash when disassembling invalid instructions.
Check for null before dereferencing an operand pointer.  Normally
this situation should never arise, but could happen if a "partial"
instruction is encountered at the end of a file or section.

opcodes/
	* s12z-dis.c (print_insn_s12z):  Do not dereference an
	operand if it is null.
2019-01-09 19:47:06 +01:00
John Darrington
39f286cd58 S12Z: Fix disassembly of indexed OPR operands with zero index.
gas/
	* testsuite/gas/s12z/jsr.s: New case.
	* testsuite/gas/s12z/jsr.d: New case.
opcodes/
	* s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is
	zero.
2019-01-09 19:44:27 +01:00
Andrew Paprocki
3107326d3d Adjust bfd/warning.m4 egrep patterns
Adjust the `bfd/warning.m4` `egrep` patterns to handle preprocessors
that do not define `__GNUC__`, leaving the string in the output.

bfd/
	* warning.m4: Adjust egrep pattern for non-GNU compilers.
	* configure: Regenerate.
binutils/
	* configure: Regenerate.
gas/
	* configure: Regenerate.
gold/
	* configure: Regenerate.
gprof/
	* configure: Regenerate.
ld/
	* configure: Regenerate.
opcodes/
	* configure: Regenerate.
2019-01-09 13:51:08 +10:30
Alan Modra
7e9ca91e00 s12z regen
* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
2019-01-07 15:05:34 +10:30
John Darrington
ef1ad42b8b S12Z: opcodes: Separate the decoding of operations from their display.
This change adds an abstraction layer between the decoding of machine
operations and their disassembled textual representation.  This allows
the decoding routines to be re-used for other purposes (at the expense)
of slightly slower running time.

ChangeLog: opcodes/

   * s12z-opc.c: New file.
   * s12z-opc.h: New file.
   * s12z-dis.c: Removed all code not directly related to display
     of instructions.  Used the interface provided by the new files
     instead.
   * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
   * Makefile.in: regenerate.
   * configure.ac (bfd_s12z_arch): Correct the dependencies.
   * configure: regenerate.
2019-01-03 18:30:40 +01:00
Alan Modra
827041555a Update year range in copyright notice of binutils files 2019-01-01 22:06:53 +10:30
Alan Modra
d5c04e1bf8 ChangeLog rotation 2019-01-01 21:25:40 +10:30
Alan Modra
d1a3c973fa PR24028, PPC_INT_FMT
PPC_INT_FMT is redundant now that bfd.h pulls in inttypes.h if
available.  Apparently MacOS Mojave defines int64_t as long long even
though long is also 64 bits, which confuses the logic selecting
PPC_INT_FMT (and BFD_PRI64 too).  Hopefully inttypes.h is available on
Mojave.

	PR 24028
include/
	* opcode/ppc.h (PPC_INT_FMT): Delete.
opcodes/
	* ppc-dis.c (print_insn_powerpc): Replace PPC_INT_FMT uses with
	PRId64/PRIx64.
2018-12-28 15:02:04 +10:30
Alan Modra
2d5d5a8f0a Include bfd_stdint.h in bfd.h
This patch adds bfd_stdint.h to bfd.h, so that BFD can use size_t
where appropriate in function parameters and return values.  I also
tidy a few other cases where headers are included twice.

bfd/
	* Makefile.am (bfdinclude_HEADERS): Add bfd_stdint.h.
	(BFD_H_DEPS): Add include/diagnostics.h.
	(LOCAL_H_DEPS): Add bfd_stdint.h.
	* bfd-in.h: Include bfd_stdint.h.
	* arc-plt.h: Don't include stdint.h.
	* coff-rs6000.c: Likewise.
	* coff64-rs6000.c: Likewise.
	* elfxx-riscv.c: Likewise.
	* cache.c: Don't include bfd_stdint.h.
	* elf32-arm.c: Likewise.
	* elf32-avr.c: Likewise.
	* elf32-nds32.c: Likewise.
	* elf32-rl78.c: Likewise.
	* elf32-rx.c: Likewise.
	* elf32-wasm32.c: Likewise.
	* elf64-nfp.c: Likewise.
	* elflink.c: Likewise.
	* elfnn-aarch64.c: Likewise.
	* elfnn-ia64.c: Likewise.
	* elfxx-ia64.c: Likewise.
	* elfxx-x86.h: Likewise.
	* wasm-module.c: Likewise, and don't include sysdep.h twice.
	* elf-nacl.h: Don't include bfd.h.
	* mach-o.h: Likewise.
	* elfxx-aarch64.c: Include bfd.h and elf-bfd.h.
	* elfxx-aarch64.h: Don't include bfd.h, elf-bfd.h or stdint.h.
	* mach-o-aarch64.c: Include mach-o.h later.
	* mach-o-arm.c: Likewise.
	* mach-o-i386.c: Likewise.
	* mach-o-x86-64.c: Likewise.
	* mach-o.c: Likewise.
	* sysdep.h: Don't include ansidecl.h or sys/stat.h.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
opcodes/
	* arm-dis.c: Include bfd.h.
	* aarch64-opc.c: Include bfd_stdint.h rather than stdint.h.
	* csky-dis.c: Likewise.
	* nds32-asm.c: Likewise.
	* riscv-dis.c: Likewise.
	* s12z-dis.c: Likewise.
	* wasm32-dis.c: Likewise.
2018-12-18 23:49:48 +10:30
Jim Wilson
f50fabe4f6 RISC-V: Fix 4-arg add parsing.
PR gas/23956
	gas/
	* config/tc-riscv.c (validate_riscv_insn) <'1'>: New case.
	(percent_op_null): New.
	(riscv_ip) <'j'>: Set imm_reloc before p.
	<'1'>: New case.
	<'0'>: Use percent_op_null and don't set imm_reloc.
	<alu_op>: Handle *args == '1'.
	* testsuite/gas/riscv/tprel-add.d: New.
	* testsuite/gas/riscv/tprel-add.l: New.
	* testsuite/gas/riscv/tprel-add.s: New.
	opcodes/
	* riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg.
2018-12-07 12:31:05 -08:00
Andrew Burgess
7fb45a6895 sim/opcodes: Allow use of out of tree cgen source directory
When configuring with '--enbale-cgen-maint' the default for both the
opcodes/ and sim/ directories is to assume that the cgen source is
within the binutils-gdb source tree as binutils-gdb/cgen/.

In the old cvs days, this worked well, as cgen was just another
sub-module of the single cvs repository and could easily be checked
out within the binutils-gdb directory, and managed by cvs in the
normal way.

Now that binutils-gdb is in git, while cgen is still in cvs, placing
the cgen respository within the binutils-gdb tree is more troublesome,
and it would be nice if the two tools could be kept separate.

Luckily there is already some initial code in the configure.ac files
for both opcodes/ and sim/ to support having cgen be located outside
of the binutils-gdb tree, however, this was speculative code written
imagining a future where cgen would be built and installed to some
location.

Right now there is no install support for cgen, and so the configure
code in opcodes/ and sim/ doesn't really do anything useful.  In this
commit I repurpose this code to allow binutils-gdb to be configured so
that it can make use of a cgen source directory that is outside of the
binutils-gdb tree.

With this commit applied it is now possible to configure and build
binutils-gdb like this:

    /path/to/binutils-gdb/src/configure --enable-cgen-maint=/path/to/cgen/src/cgen/
    make all-opcodes
    make -C opcodes run-cgen-all

Just in case anyone is still using cgen inside the binutils-gdb tree,
I have left the default behaviour of '--enable-cgen-maint' (with no
parameter) unchanged, that is it looks for the cgen directory as
'binutils-gdb/cgen/'.

opcodes/ChangeLog:

	* configure.ac (enable-cgen-maint): Support passing path to cgen
	source tree.
	* configure: Regenerate.

sim/ChangeLog:

	* common/acinclude.m4 (enable-cgen-maint): Support passing path to
	cgen source tree.
	* cris/configure: Regenerate.
	* frv/configure: Regenerate.
	* iq2000/configure: Regenerate.
	* lm32/configure: Regenerate.
	* m32r/configure: Regenerate.
	* or1k/configure: Regenerate.
	* sh64/configure: Regenerate.
2018-12-06 12:21:10 +00:00
Andrew Burgess
884b49e3a9 opcodes/riscv: Hide '.L0 ' fake symbols
The RISC-V assembler generates fake labels with the name '.L0 ' as
part of the debug information (see
gas/config/tc-riscv.h:FAKE_LABEL_NAME).

The problem is that currently, when disassembling an object file, the
output looks like this (this is an example from the GDB testsuite, but
is pretty representative of anything with debug information):

  000000000000001e <main>:
    1e:   7179                    addi    sp,sp,-48
    20:   f406                    sd      ra,40(sp)
    22:   f022                    sd      s0,32(sp)
    24:   1800                    addi    s0,sp,48

  0000000000000026 <.L0 >:
    26:   87aa                    mv      a5,a0
    28:   feb43023                sd      a1,-32(s0)
    2c:   fcc43c23                sd      a2,-40(s0)
    30:   fef42623                sw      a5,-20(s0)

  0000000000000034 <.L0 >:
    34:   fec42783                lw      a5,-20(s0)
    38:   0007871b                sext.w  a4,a5
    3c:   678d                    lui     a5,0x3
    3e:   03978793                addi    a5,a5,57 # 3039 <.LASF30+0x2a9d>
    42:   02f71463                bne     a4,a5,6a <.L0 >

  0000000000000046 <.L0 >:
    46:   000007b7                lui     a5,0x0
    4a:   0007b783                ld      a5,0(a5) # 0 <need_malloc>
    4e:   6f9c                    ld      a5,24(a5)

  0000000000000050 <.L0 >:
    50:   86be                    mv      a3,a5
    52:   466d                    li      a2,27
    54:   4585                    li      a1,1
    56:   000007b7                lui     a5,0x0
    5a:   00078513                mv      a0,a5
    5e:   00000097                auipc   ra,0x0
    62:   000080e7                jalr    ra # 5e <.L0 +0xe>

  0000000000000066 <.L0 >:
    66:   4785                    li      a5,1
    68:   a869                    j       102 <.L0 >

  000000000000006a <.L0 >:
    6a:   000007b7                lui     a5,0x0
    6e:   00078513                mv      a0,a5
    72:   00000097                auipc   ra,0x0
    76:   000080e7                jalr    ra # 72 <.L0 +0x8>

The frequent repeated '.L0 ' labels are pointless, as they are
non-unique there's no way to match a use of '.L0 ' to its appearence
in the output, so we'd be better off just not printing it at all.
That's what this patch does by defining a 'symbol_is_valid' method for
RISC-V.  With this commit, the same disassembly now looks like this:

  000000000000001e <main>:
    1e:   7179                    addi    sp,sp,-48
    20:   f406                    sd      ra,40(sp)
    22:   f022                    sd      s0,32(sp)
    24:   1800                    addi    s0,sp,48
    26:   87aa                    mv      a5,a0
    28:   feb43023                sd      a1,-32(s0)
    2c:   fcc43c23                sd      a2,-40(s0)
    30:   fef42623                sw      a5,-20(s0)
    34:   fec42783                lw      a5,-20(s0)
    38:   0007871b                sext.w  a4,a5
    3c:   678d                    lui     a5,0x3
    3e:   03978793                addi    a5,a5,57 # 3039 <.LASF30+0x2a9d>
    42:   02f71463                bne     a4,a5,6a <.L4>
    46:   000007b7                lui     a5,0x0
    4a:   0007b783                ld      a5,0(a5) # 0 <need_malloc>
    4e:   6f9c                    ld      a5,24(a5)
    50:   86be                    mv      a3,a5
    52:   466d                    li      a2,27
    54:   4585                    li      a1,1
    56:   000007b7                lui     a5,0x0
    5a:   00078513                mv      a0,a5
    5e:   00000097                auipc   ra,0x0
    62:   000080e7                jalr    ra # 5e <main+0x40>
    66:   4785                    li      a5,1
    68:   a869                    j       102 <.L5>

  000000000000006a <.L4>:
    6a:   000007b7                lui     a5,0x0
    6e:   00078513                mv      a0,a5
    72:   00000097                auipc   ra,0x0
    76:   000080e7                jalr    ra # 72 <.L4+0x8>

In order to share the fake label between the assembler and the
libopcodes library, I've added some new defines RISCV_FAKE_LABEL_NAME
and RISCV_FAKE_LABEL_CHAR in include/opcode/riscv.h.  I could have
just moved FAKE_LABEL_NAME to the include file, however, I thnk this
would be confusing, someone working on the assembler would likely not
expect to find FAKE_LABEL_NAME defined outside of the assembler source
tree.  By introducing the RISCV_FAKE_LABEL_* defines I can leave the
assembler standard FAKE_LABEL_ defines in the assembler source, but
still share the RISCV_FAKE_LABEL_* with libopcodes.

gas/ChangeLog:

	* config/tc-riscv.h (FAKE_LABEL_NAME): Define as
	RISCV_FAKE_LABEL_NAME.
	(FAKE_LABEL_CHAR): Define as RISCV_FAKE_LABEL_CHAR.

include/ChangeLog:

	* dis-asm.h (riscv_symbol_is_valid): Declare.
	* opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define.
	(RISCV_FAKE_LABEL_CHAR): Define.

opcodes/ChangeLog:

        * disassembler.c (disassemble_init_for_target): Add RISC-V
        initialisation.
        * riscv-dis.c (riscv_symbol_is_valid): New function.
2018-12-06 09:40:56 +00:00
Jim Wilson
1080bf78c0 RISC-V: Accept version, supervisor ext and more than one NSE for -march.
This patch moves all -march parsing logic into bfd, because we will use this
code in ELF attributes.

	bfd/
	* elfxx-riscv.h (RISCV_DONT_CARE_VERSION): New macro.
	(struct riscv_subset_t): New structure.
	(riscv_subset_t): New typedef.
	(riscv_subset_list_t): New structure.
	(riscv_release_subset_list): New prototype.
	(riscv_add_subset): Likewise.
	(riscv_lookup_subset): Likewise.
	(riscv_lookup_subset_version): Likewise.
	(riscv_release_subset_list): Likewise.
	* elfxx-riscv.c: Include safe-ctype.h.
	(riscv_parsing_subset_version): New function.
	(riscv_supported_std_ext): Likewise.
	(riscv_parse_std_ext): Likewise.
	(riscv_parse_sv_or_non_std_ext): Likewise.
	(riscv_parse_subset): Likewise.
	(riscv_add_subset): Likewise.
	(riscv_lookup_subset): Likewise.
	(riscv_lookup_subset_version): Likewise.
	(riscv_release_subset_list): Likewise.
	gas/
	* config/tc-riscv.c: Include elfxx-riscv.h.
	(struct riscv_subset): Removed.
	(riscv_subsets): Change type to riscv_subset_list_t.
	(riscv_subset_supports): Removed argument: xlen_required and move
	logic into libbfd.
	(riscv_multi_subset_supports): Removed argument: xlen_required.
	(riscv_clear_subsets): Removed.
	(riscv_add_subset): Ditto.
	(riscv_set_arch): Extract parsing logic into libbfd.
	(riscv_ip): Update argument for riscv_multi_subset_supports and
	riscv_subset_supports. Update riscv_subsets due to struct definition
	changed.
	(riscv_after_parse_args): Update riscv_subsets due to struct
	definition changed, update and argument for riscv_subset_supports.
	* testsuite/gas/riscv/empty.s: New.
	* testsuite/gas/riscv/march-fail-rv32ef.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32i.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32i.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iam.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iam.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ic.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ic.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32icx2p.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32imc.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32imc.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64I.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64I.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64e.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64e.l: Likewise.
	* testsuite/gas/riscv/march-ok-g2.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
	* testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
	* testsuite/gas/riscv/march-ok-nse-with-version.: Likewise.d
	* testsuite/gas/riscv/march-ok-s-with-version.d: Likewise.
	* testsuite/gas/riscv/march-ok-s.d: Likewise.
	* testsuite/gas/riscv/march-ok-sx.d: Likewise.
	* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
	* testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
	include/
	* opcode/riscv.h (riscv_opcode): Change type of xlen_requirement to
	unsigned.
	opcodes/
	* riscv-opc.c: Change the type of xlen, because type of
	xlen_requirement changed.
2018-12-03 14:05:17 -08:00
Egeyar Bagcioglu
57b64c4103 [aarch64] - Only use MOV for disassembly when shifter op is LSL #0
ARM Architecture Reference Manual for the profile ARMv8-A, Issue C.a,
states that MOV (register) is an alias of the ORR (shifted register)
iff shift == '00' && imm6 == '000000' && Rn == '11111'.  However, mov
is currently preferred for a broader range of orr instructions, which
is incorrect.

2018-12-03  Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>

opcodes:
	PR 23193
        PR 19721
        * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
	encoding as MOV if the shift operation is a left shift of zero.

gas:
	PR 23193
	PR 19721
	* testsuite/gas/aarch64/pr19721.s: Add new test cases.
	* testsuite/gas/aarch64/pr19721.d: Correct existing test
	cases and add new ones.
2018-12-03 17:34:33 +00:00
Jim Wilson
12951a2f08 RISC-V: Add missing c.unimp instruction.
opcodes/
	* riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
	(c.unimp): New.
2018-11-29 13:10:38 -08:00
Jim Wilson
4765cd6119 RISC-V: Add .insn CA support.
gas/
	* config/tc-riscv.c (validate_riscv_insn) <'F'>: Add support for CF6
	and CF2 operands.
	(riscv_ip) <'F'>: Likewise.
	* doc/c-riscv.texi (RISC-V-Formats): Add func6 abbreviation.  Use rs2
	instead of rs1 in CR description.  Add CA docs.
	* gas/testsuite/riscv/insn.s: Add use of .insn ca.
	* gas/testsuite/riscv/insn.d: Update to match.
	include/
	* opcode/riscv.h (OP_MASK_CFUNCT6, OP_SH_CFUNCT6): New.
	(OP_MASK_CFUNCT2, OP_SH_CFUNCT2): New.
	opcodes/
	* riscv-opc.c (ciw): Fix whitespace to align columns.
	(ca): New.
2018-11-27 11:29:23 -08:00
John Darrington
27f42a4ddb S12Z opcodes: Fix bug disassembling certain shift instructions.
Shift and rotate instructions when the number of bit positions
was an immediate value greater than 1 were incorrectly disassembled.
This change fixes that problem and extends the test to check for
it.

gas/ChangeLog:

  testsuite/gas/s12z/shift.s: Add new test case.
  testsuite/gas/s12z/shift.d: Add expected result.

opcodes/ChangeLog:

  s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
  if the postbyte matches the appropriate pattern.
2018-11-21 21:34:47 +01:00
Francois H. Theron
97b3f39201 opcodes/nfp: Fix disassembly of crc[] with swapped operands.
The decoding of the CRC operation in alu instructions was using bits
from the instruction word directly, instead of srcA which would be
different if the swap bit was set.

Signed-off-by: Francois H. Theron <francois.theron@netronome.com>
2018-11-13 15:33:21 +02:00
Sudakshina Das
3a0f69be55 [BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch adds all the data cache instructions that are part of this
extension:
- DC IGVAC, Xt
- DC IGSW, Xt
- DC CGSW, Xt
- DC CIGSW, Xt
- DC CGVAC, Xt
- DC CGVAP, Xt
- DC CGVADP, Xt
- DC CIGVAC, Xt
- DC GVA, Xt
- DC IGDVAC, Xt
- DC IGDSW, Xt
- DC CGDSW, Xt
- DC CIGDSW, Xt
- DC CGDVAC, Xt
- DC CGDVAP, Xt
- DC CGDVADP, Xt
- DC CIGDVAC, Xt
- DC GZVA, Xt

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_sys_regs_dc): New entries for
	IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
	IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
	CIGDVAC and GZVA.
	(aarch64_sys_ins_reg_supported_p): New check for above.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/sysreg-4.s: Test IGVAC, IGSW,
	CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
	IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
	CIGDVAC and GZVA with DC.
	* testsuite/gas/aarch64/sysreg-4.d: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-11-12 13:29:38 +00:00
Sudakshina Das
70f3d23af7 [BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch adds all the system registers that are part of this
extension and are accessible via the MRS/MSR instructions:
- TCO
- TFSRE0_SL1
- TFSR_EL1
- TFSR_EL2
- TFSR_EL3
- TFSR_EL12
- RGSR_EL1
- GCR_EL1
TCO is also accessible with the MSR(immediate) instruction.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
	TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
	RGSR_EL1 and GCR_EL1.
	(aarch64_sys_reg_supported_p): New check for above.
	(aarch64_pstatefields): New entry for TCO.
	(aarch64_pstatefield_supported_p): New check for above.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1,
	TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and
	GCR_EL1 MSR and MRS.
	* testsuite/gas/aarch64/sysreg-4.d: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-11-12 13:26:01 +00:00
Sudakshina Das
503ba60025 [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch add support to the Bulk Allocation Tag instructions from
MTE. These are the following instructions added in this patch:
- LDGV <Xt>, [<Xn|SP>]!
- STGV <Xt>, [<Xn|SP>]!

This needed a new kind of operand for the new addressing [<Xn|SP>]!
since this has no offset and only takes a pre-indexed version.
Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced.
(AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does
not allow writeback). We also needed new encoding and decoding
functions to be able to do the same.

where
<Xt> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.

*** include/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
	(aarch64_insn_class): Add ldstgv_indexed.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm.c (aarch64_ins_addr_simple_2): New.
	* aarch64-asm.h (ins_addr_simple_2): Declare the above.
	* aarch64-dis.c (aarch64_ext_addr_simple_2): New.
	* aarch64-dis.h (ext_addr_simple_2): Declare the above.
	* aarch64-opc.c (operand_general_constraint_met_p): Add case for
	AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
	(aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
	* aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
	(AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_operands): Add switch case for
	AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
	(warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12 13:20:58 +00:00
Sudakshina Das
e6025b546c [BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch add support to the Tag Getting instruction from Memory Tagging
Extension.
- LDG <Xt>, [<Xn|SP>, #<simm>]

where
<Xt> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range of -4096 and 4080, defaulting to 0.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (QL_LDG): New.
	(aarch64_opcode_table): Add ldg.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldg.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12 13:20:37 +00:00
Sudakshina Das
fb3265b371 [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>

where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.

*** include/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
	and AARCH64_OPND_ADDR_SIMM13.
	(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
	for AARCH64_OPND_QLF_imm_tag.
	(operand_general_constraint_met_p): Add case for
	AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
	(aarch64_print_operand): Likewise.
	* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
	(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
	for both offset and pre/post indexed versions.
	(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_operands): Add switch case for
	AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
	(fix_insn): Likewise.
	(warn_unpredictable_ldst): Exempt STGP.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
	stzg, stz2g and stgp.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12 13:09:55 +00:00
Sudakshina Das
b731bc3b1b [BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch add support to the Pointer Arithmetic instructions from
MTE. These are the following instructions added in this patch:
- SUBP <Xd>, <Xn|SP>, <Xm|SP>
- SUBPS <Xd>, <Xn|SP>, <Xm|SP>
- CMPP <Xn|SP>, <Xm|SP>
where CMPP is an alias to SUBPS XZR, <Xn|SP>, <Xm|SP>

where
<Xd> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
<Xm|SP> : Is the 64-bit second source GPR or Stack pointer.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for subp,
	subps and cmpp.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12 12:59:42 +00:00
Sudakshina Das
193614f2b9 [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch add support to the Tag generation instructions from
MTE. These are the following instructions added in this patch:
- IRG <Xd|SP>, <Xn|SP>{, Xm}
- ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- GMI <Xd>, <Xn|SP>, <Xm>

where
<Xd|SP> : Is the 64-bit destination GPR or Stack pointer.
<Xn|SP> : Is the 64-bit source GPR or Stack pointer.
<uimm6> : Is the unsigned immediate, a multiple of 16
in the range 0 to 1008.
<uimm4> : Is the unsigned immediate, in the range 0 to 15.

*** include/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (aarch64_opnd): Add
	AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
	(OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
	* aarch64-opc.c (fields): Add entry for imm4_3.
	(operand_general_constraint_met_p): Add cases for
	AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
	(aarch64_print_operand): Likewise.
	* aarch64-tbl.h (QL_ADDG): New.
	(aarch64_opcode_table): Add addg, subg, irg and gmi.
	(AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
	* aarch64-asm.c (aarch64_ins_imm): Add case for
	operand_need_shift_by_four.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_operands): Add switch case for
	AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.d: Likewise.
2018-11-12 12:59:22 +00:00
Sudakshina Das
73b605ec3f [BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions. Memory Tagging Extension is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds the new command line option and the new feature macros.

*** include/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (aarch64_feature_memtag): New.
	(MEMTAG, MEMTAG_INSN): New.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "memtag"
	as a new option.
	* doc/c-aarch64.texi: Document the same.
2018-11-12 12:45:30 +00:00
Sudakshina Das
0632eeea6e [BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros.
This patch addresses the following
1) Adding ARMv8.5-A in select_arm_features.
2) Updating the feature macro so that the new ARM_EXT2_* features for
Armv8.5-A are moved to ARM_AEXT2_V8_5A.

*** opcodes/ChangeLog ***

2018-11-06  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (select_arm_features): Update bfd_mach_arm_8
	with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.

*** include/ChangeLog ***

2018-11-06  Sudakshina Das  <sudi.das@arm.com>

	* opcode/arm.h (ARM_ARCH_V8_5A): Move ARM_EXT2_PREDRES and
	ARM_EXT2_SB to ...
	(ARM_AEXT2_V8_5A): Here.
2018-11-06 12:13:45 +00:00
Alan Modra
715537181e PowerPC instruction mask checks
The instruction mask bits should never overlap any of the operands,
nor should operand bits overlap, but some operands weren't checked.
This patch arranges to check the omitted operands, using a mask
returned by the operand->insert function.  Some tweaking of various
insert functions is needed to support this: The error case must set
field bits.

Since I was looking at the insert functions, I tidied some dead code
and simplified some of the powerpc_operands entries.

gas/
	* config/tc-ppc.c (insn_validate): Don't ignore mask in
	PPC_OPSHIFT_INV case.  Call the insert function to calculate
	a mask.
opcodes/
	* ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
	(insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
	(insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
	(insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
	Don't return zero on error, insert mask bits instead.
	(insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
	(insert_sh6, extract_sh6): Delete dead code.
	(insert_sprbat, insert_sprg): Use unsigned comparisions.
	(powerpc_operands <OIMM>): Set shift count rather than using
	PPC_OPSHIFT_INV.
	<SE_SDH, SE_SDW>: Likewise.  Don't use insert/extract functions.
2018-11-06 21:17:28 +10:30
Jan Beulich
4dd4e63945 x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit mode
For the flavor having a GPR operand EVEX.W is ignored outside of 64-bit
mode. The mnemonic should therefore not be VPBROADCASTQ.
2018-11-06 11:45:49 +01:00
Jan Beulich
9819647a63 x86: correctly handle VMOVD with EVEX.W set outside of 64-bit mode
For the flavors having a GPR operand EVEX.W is ignored outside of 64-bit
mode. The mnemonic should therefore not be KMOVQ, the GPR operand should
not name a non-existing 64-bit register, just like is already the case
for the AVX counterparts, and the Disp8 scaling factor should be 4
rather than 8.
2018-11-06 11:45:11 +01:00
Jan Beulich
58a211d260 x86: correctly handle KMOVD with VEX.W set outside of 64-bit mode
For the flavors having a GPR operand VEX.W is ignored outside of 64-bit
mode. The mnemonic should therefore not be KMOVQ.
2018-11-06 11:44:31 +01:00
Jan Beulich
b50c9f3166 x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*
PEXTR{B,W} and PINSR{B,W}, just like for AVX512BW, are WIG, no matter
that the SDM uses a nonstandard description of that fact.

PEXTRD, even with EVEX.W set, ignores that bit outside of 64-bit mode,
just like its AVX counterpart.
2018-11-06 11:43:55 +01:00
Jan Beulich
931d03b75a x86: adjust {,E}VEX.W handling outside of 64-bit mode
Many VEX-/EVEX-encoded instructions accessing GPRs become WIG outside of
64-bit mode. The respective templates should specify neither VexWIG nor
VexW0, but instead the setting of the bit should be determined from
- REX.W in 64-bit mode,
- the setting established through -mvexwig= / -mevexwig= otherwise.
This implies that the evex-wig2 testcase needs to go away, as being
wrong altogether.

A few test additions desirable here will only happen in later patches,
as the disassembler needs adjustments first.

Once again SSE2AVX templates are left alone, for it being unclear what
the behavior there should be.
2018-11-06 11:42:54 +01:00
Jan Beulich
fd71a3756e x86: fix various non-LIG templates
Quite a few templates were marked LIG while really the insns aren't.
Introduce descriptive shorthands once again, instead of continuing to
use the less legible original forms.
2018-11-06 11:42:08 +01:00
Jan Beulich
563c7eef61 x86: allow {store} to select alternative {,}PEXTRW encoding
The 0F C5 encoding is indeed a load type one (just that memory operands
are not permitted), while the 0F 3A 15 encoding is obviously a store.
Allow the pseudo prefixes to be used to select between them.

Also move (without any change) the secondary AVX512BW templates next to
the primary one.
2018-11-06 11:40:25 +01:00
Jan Beulich
0aaca1d90a x86: add more VexWIG
Commits 6865c0435a ("x86: Support VEX/EVEX WIG encoding") and 6fa52824c3
("x86: Replace VexW=3 with VexWIG") omitted quite a few templates, oddly
enough in some cases despite testcases getting added (which then were
recorded with wrong expected output).

Also adjust VPMAXUB's attributes in the AVX512BW case to match ordering
of that of neighboring templates.

For the moment SSE2AVX templates are left alone, as it isn't clear
whether they were intentionally left untouched by the original commits
(the descriptions don't say either way).

In this context I question the decision in commit 0375113302 ("x86: Add
-mvexwig=[0|1] option to assembler") to move the logic to determine the
value of the W bit ahead of the decision whether to use 2-byte VEX:
While I can see this as one possible interpretation of -mvexwig=, the
other alternative (setting the value of the bit only if it actually
exists in the encoding) looks as reasonable to me, and perhaps even more
in line with us generally trying to pick the shortest encoding.
2018-11-06 11:39:42 +01:00
Jan Beulich
bbae6b11eb x86: XOP VPHADD* / VPHSUB* are VEX.W0
Also avoid introducing further uses of VexW=1, by introducing and using
VexW0 at this occasion. Move the marker past all #define-s.
2018-11-06 11:38:47 +01:00
John Darrington
192c2bfbd7 S12Z: Disassembly: Fallback to show the address if the symbol table is empty.
* opcodes/s12z-dis.c (decode_possible_symbol): Add fallback case.
  (rel_15_7): Likewise.
2018-10-22 20:53:15 +02:00