When --gsframe is specified, the assembler will generate a .sframe
section from the CFI directives in the assembly.
ChangeLog:
* gas/as.c (parse_args): Parse args and set flag_gen_sframe.
* gas/as.h: Introduce skeleton for --gsframe.
* gas/doc/as.texi: document --gsframe.
Without commit b66e671854, this:
.p2align 4
nop
.p2align 3
nop
results in an error when coff_frob_section attempts to pad out the
section to a 16-byte boundary. Due to miscalculating the pad pattern
repeat count, write.c:write_contents attempts to shove 16 bytes of
padding into the remaining 4 bytes of the .text section.
* config/obj-coff.c (coff_frob_section): Correct fill count.
Don't pad after errors.
Attributes which aren't used together in any single insn template can be
converted from individual booleans to a single enum, as was done for a few
other attributes before. This is more space efficient. Collect together
all attributes which express special operand constraints (and which fit
the criteria for folding).
This patch adds the assembler support for the new unwinder
directive ".pacspval" and encodes this directives with opcode
"0xb5". This opcode indicates the unwinder to use effective
vsp as modifier for PAC validation.
gas/ChangeLog:
2022-11-07 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* doc/c-arm.texi: Document directive.
* config/tc-arm.c (s_arm_unwind_pacspval): Define function.
(md_pseudo_table): Add entry for pacspval directive.
* testsuite/gas/arm/ehabi-pacbti-m.d: New test.
* testsuite/gas/arm/ehabi-pacbti-m.s: Likewise.
This tidies SEC_RELOC handling in bfd, in the process fixing a bug
with objcopy when renaming sections.
bfd/
* reloc.c (_bfd_generic_set_reloc): Set/clear SEC_RELOC depending
on reloc count.
* elf64-sparc.c (elf64_sparc_set_reloc): Likewise.
binutils/
* objcopy.c (copy_relocations_in_section): Remove now unnecessary
clearing of SEC_RELOC.
* testsuite/binutils-all/rename-section-01.d: New test.
* testsuite/binutils-all/objcopy.exp: Run it.
gas/
* write.c (size_seg): Remove unneccesary twiddle of SEC_RELOC.
(write_relocs): Likewise. Always call bfd_set_reloc.
On a testcase like
pla 8,foo@pcrel
disassembled with -Mpower10 results in
0: 00 00 10 06 pla r8,0 # 0
4: 00 00 00 39
0: R_PPC64_PCREL34 foo
but with -Mpower10 -Mraw
0: 00 00 10 06 .long 0x6100000
0: R_PPC64_PCREL34 foo
4: 00 00 00 39 addi r8,0,0
The instruction is unrecognised due to the hack we have in
extract_pcrel0 in order to disassemble paddi with RA0=0 and R=1 as
pla. I could have just added "&& !(dialect & PPC_OPCODE_RAW)" to the
condition in extract_pcrel0 under which *invalid is set, but went for
this larger patch that reorders the extended insn pla to the more
usual place before its underlying machine insn. (la is after addi
because we never disassemble to la.)
gas/
* testsuite/gas/ppc/raw.d,
* testsuite/gas/ppc/raw.s: Add pla.
opcodes/
* ppc-opc.c (extract_pcrel1): Rename from extract_pcrel0 and
invert *invalid logic.
(PCREL1): Rename from PCREL0.
(prefix_opcodes): Sort pla before paddi, adjusting R operand
for pla, paddi and psubi.
While .linefile is generally intended for gas internal use only, its use
in a source file would better not result in an internal error. Give use
of it outside of any macro(-like) construct the meaning of restoring the
original (physical) input file name.
(%dx) isn't a valid memory address in any modes. It is used as a special
memory operand for input/output port address in AT&T syntax and should
only be used with input/output instructions. Update i386_att_operand to
set i.input_output_operand to true for (%dx) and issue an error if (%dx)
is used with non-input/output instructions.
PR gas/29751
* config/tc-i386.c (_i386_insn): Add input_output_operand.
(md_assemble): Issue an error if input/output memory operand is
used with non-input/output instructions.
(i386_att_operand): Set i.input_output_operand to true for
(%dx).
* testsuite/gas/i386/inval.l: Updated.
* testsuite/gas/i386/x86-64-inval.l: Likewise.
* testsuite/gas/i386/inval.s: Add tests for invalid (%dx) usage.
* testsuite/gas/i386/x86-64-inval.s: Likewise.
Operand swapping was mistakenly suppressed when the first two operands
were immediate ones, not taking into account overall operand count. This
way EXTRQ / INSERTQ would have been accepted also with kind-of-AT&T
operand order.
For the testcase being extended, in order to not move around "GAS
LISTING" expectations, suppress pagination.
Although the encoding for scalar and fp registers is identical,
we should follow common pratice and use fp register names
when referencing fp registers.
The xtheadmemidx extension consists of indirect load/store instructions
which all load to or store from fp registers.
Let's use fp register names in this case and adjust the test cases
accordingly.
gas/
* testsuite/gas/riscv/x-thead-fmemidx-fail.l: Updated since rd need to
be float register.
* testsuite/gas/riscv/x-thead-fmemidx-fail.s: Likewise.
* testsuite/gas/riscv/x-thead-fmemidx.d: Likewise.
* testsuite/gas/riscv/x-thead-fmemidx.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Updated since rd need to be float register.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas uses ZSTD_compressStream2 which is only available with libzstd >=
1.4.0, leading to build errors when an older version is installed.
This patch updates the check libzstd presence to check its version is
>= 1.4.0. However, since gas seems to be the only component requiring
such a recent version this may imply that we disable ZSTD support for
all components although some would still benefit from an older
version.
I ran 'autoreconf -f' in all directories containing a configure.ac
file, using vanilla autoconf-2.69 and automake-1.15.1. I noticed
several errors from autoheader in readline, as well as warnings in
intl, but they are unrelated to this patch.
This should fix some of the buildbots.
OK for trunk?
Thanks,
Christophe
Despite that the RISC-V ISA Manual version 2.2 prohibited "RV32EF", later
versions beginning with the version 20190608-Base-Ratified removed this
restriction. Because the 'E' extension is still a draft, the author chose
to *just* remove the conflict (not checking the ISA version).
Note that, because RV32E is only used with a soft-float calling convention,
there's no valid official ABI for RV32EF. It means, even if we can assemble
a program with -march=rv32ef -mabi=ilp32e, floating-point registers are kept
in an unmanaged state (outside ABI management).
The purpose of this commit is to suppress unnecessary errors while parsing
an ISA string and/or disassembling, not to allow hard-float with RVE.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Accept RV32EF
because only older specifications disallowed it.
gas/ChangeLog:
* testsuite/gas/riscv/march-fail-rv32ef.d: Remove as not directly
prohibited.
* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
This patch is based on MULTIPLE_FRAME_SECTIONS and EH_FRAME_LINKONCE,
it allows backend to enable this feature and use '--gc-sections' simply.
* gas/dw2gencfi.h (TARGET_MULTIPLE_EH_FRAME_SECTIONS): New.
(MULTIPLE_FRAME_SECTIONS): Add TARGET_MULTIPLE_EH_FRAME_SECTIONS.
* gas/dw2gencfi.c (EH_FRAME_LINKONCE): Add TARGET_MULTIPLE_EH_FRAME_SECTIONS.
(is_now_linkonce_segment): Likewise.
(get_cfi_seg): Create relocation info between .eh_frame.* and .text.* section.
* bfd/elf-bfd.h (elf_backend_can_make_multiple_eh_frame): New.
* bfd/elfxx-target.h (elf_backend_can_make_multiple_eh_frame): Likewise.
* bfd/elflink.c (_bfd_elf_default_action_discarded): Add checking for
elf_backend_can_make_multiple_eh_frame.
Comparing the sum of the relevant .imm<N> fields against a constant imo
makes more obvious what is actually meant. It allows dropping of two
static variables, with a 3rd drop requiring two more minor adjustments
elsewhere, utilizing that "i" is zeroed first thing in md_assemble().
This also increases the chances of the compiler doing the calculations
all in registers.
Consider the case,
.option arch, rv32i
.option norelax
.option arch, +c
.byte 1
.align 2
addi a0, zero, 1
Assembler adds $d for the odd .byte, and then adds $x+arch for the
alignment. Since norelax, riscv_add_odd_padding_symbol will add the
$d and $x for the odd alignment, but accidently remove the $x+arch because
it has the same address as $d. Therefore, we will get the unexpected result
before applying this patch,
.byte 1 # $d
.align 2 # odd alignment, $xrv32ic replaced by $d + $x
After this patch, the expected result should be,
.byte 1 # $d
.align 2 # odd alignment, $xrv32ic replaced by $d + $xrv32ic
gas/
* config/tc-riscv.c (make_mapping_symbol): If we are adding mapping symbol
for odd alignment, then we probably will remove the $x+arch by accidently
when it has the same address of $d. Try to add the removed $x+arch back
after the $d rather than just $x.
(riscv_mapping_state): Updated since parameters of make_mapping_symbol are
changed.
(riscv_add_odd_padding_symbol): Likewise.
(riscv_remove_mapping_symbol): Removed and moved the code into the
riscv_check_mapping_symbols.
(riscv_check_mapping_symbols): Updated.
* testsuite/gas/riscv/mapping-dis.d: Updated and added new testcase.
* testsuite/gas/riscv/mapping-symbols.d: Likewise.
* testsuite/gas/riscv/mapping.s: Likewise.
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
Earlier tidying still missed an opportunity: There's no need for the
"anyimm" static variable. Instead of using it in the loop to mask
"allowed" (which is necessary to satisfy operand_type_or()'s assertions)
simply use "mask", requiring it to be calculated first. That way the
post-loop masking by "mask" ahead of the operand_type_all_zero() can be
dropped.
Silence GCC 12 warning on tc-i386.c:
gas/config/tc-i386.c: In function ‘md_assemble’:
gas/config/tc-i386.c:5039:16: error: too many arguments for format [-Werror=format-extra-args]
5039 | as_warn (_("only support RIP-relative address"), i.tm.name);
* config/tc-i386.c (md_assemble): Print mnemonic in RIP-relative
warning.
* estsuite/gas/i386/x86-64-prefetchi-warn.l: Updated.
Before figuring out the suppress rule of mapping symbol with architecture
(changed back to $x), always generate them at the start of the sections.
gas/
* config/tc-riscv.c (need_arch_map_symbol): Removed.
(riscv_mapping_state): Updated.
(riscv_check_mapping_symbols): Updated.
* testsuite/gas/riscv/mapping-non-arch.d: Removed.
* testsuite/gas/riscv/mapping-non-arch.s: Likewise.
We don't support instructions longer than 64-bits yet. Still, we can
modify validate_riscv_insn function to prevent unexpected behavior by
limiting the "length" of an instruction to 64-bit (or less).
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Fix function
description comment based on current spec. Limit instruction
length up to 64-bit for now. Make sure that required_bits does
not corrupt even if unsigned long long is longer than 64-bit.
Some versions of gcc warn by default about shadowed outer-scope
declarations. This affects frag_align_code, which is declared in
frags.h. Rename the offending function parameter. While there also
switch to using true/false at the function call sites.
Commit 40f1a1a456 ("RISC-V: Output mapping symbols with ISA string.")
caused a build failure on GCC 12 as follows:
make[3]: Entering directory '$(builddir)/gas'
CC config/tc-riscv.o
In file included from $(srcdir)/gas/config/tc-riscv.c:23:
$(srcdir)/gas/as.h: In function ‘make_mapping_symbol’:
$(srcdir)/gas/as.h:123:15: error: ‘buff’ may be used uninitialized [-Werror=maybe-uninitialized]
123 | #define xfree free
| ^~~~
$(srcdir)/gas/config/tc-riscv.c:487:9: note: ‘buff’ was declared here
487 | char *buff;
| ^~~~
cc1: all warnings being treated as errors
make[3]: *** [Makefile:1425: config/tc-riscv.o] Error 1
This is caused by a false positive of "maybe uninitialized" variable
detection (-Wmaybe-uninitialized). To avoid this error, this commit
initializes the local variable buff to NULL first in all cases.
gas/ChangeLog:
* config/tc-riscv.c (make_mapping_symbol): Initialize variable
buff with NULL to avoid build failure caused by a GCC's false
positive of maybe uninitialized variable detection.
RISC-V Psabi pr196,
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196
bfd/
* elfxx-riscv.c (riscv_release_subset_list): Free arch_str if needed.
(riscv_copy_subset_list): Copy arch_str as well.
* elfxx-riscv.h (riscv_subset_list_t): Store arch_str for each subset list.
gas/
* config/tc-riscv.c (riscv_reset_subsets_list_arch_str): Update the
architecture string in the subset_list.
(riscv_set_arch): Call riscv_reset_subsets_list_arch_str after parsing new
architecture string.
(s_riscv_option): Likewise.
(need_arch_map_symbol): New boolean, used to indicate if .option
directives do affect instructions.
(make_mapping_symbol): New boolean parameter reset_seg_arch_str. Need to
generate $x+arch for MAP_INSN, and then store it into tc_segment_info_data
if reset_seg_arch_str is true.
(riscv_mapping_state): Decide if we need to add $x+arch for MAP_INSN. For
now, only add $x+arch if the architecture strings in subset list and segment
are different. Besides, always add $x+arch at the start of section, and do
not add $x+arch for code alignment, since rvc for alignment can be judged
from addend of R_RISCV_ALIGN.
(riscv_remove_mapping_symbol): If current and previous mapping symbol have
same value, then remove the current $x only if the previous is $x+arch;
Otherwise, always remove previous.
(riscv_add_odd_padding_symbol): Updated.
(riscv_check_mapping_symbols): Don't need to add any $x+arch if
need_arch_map_symbol is false, so changed them to $x.
(riscv_frag_align_code): Updated since riscv_mapping_state is changed.
(riscv_init_frag): Likewise.
(s_riscv_insn): Likewise.
(riscv_elf_final_processing): Call riscv_release_subset_list to release
subset_list of riscv_rps_as, rather than only release arch_str in the
riscv_write_out_attrs.
(riscv_write_out_attrs): No need to call riscv_arch_str, just get arch_str
from subset_list of riscv_rps_as.
* config/tc-riscv.h (riscv_segment_info_type): Record current $x+arch mapping
symbol of each segment.
* testsuite/gas/riscv/mapping-0*: Merged and replaced by mapping.s.
* testsuite/gas/riscv/mapping.s: New testcase, to test most of the cases in
one file.
* testsuite/gas/riscv/mapping-symbols.d: Likewise.
* testsuite/gas/riscv/mapping-dis.d: Likewise.
* testsuite/gas/riscv/mapping-non-arch.s: New testcase for the case that
does need any $x+arch.
* testsuite/gas/riscv/mapping-non-arch.d: Likewise.
* testsuite/gas/riscv/option-arch-01a.d: Updated.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Set riscv_fpr_names back to
riscv_fpr_names_abi or riscv_fpr_names_numeric when zfinx is disabled
for some specfic code region.
(riscv_get_map_state): Recognized mapping symbols $x+arch, and then reset
the architecture string once the ISA is different.
There's little point in having Intel syntax disassembler tests when the
purpose of a test is assembler functionality: Drop all
*avx512*_vpclmulqdq-wig1-intel.
For *avx512*_vpclmulqdq-wig1 share source with *avx512*_vpclmulqdq.
Finally put in place similar tests for -mvexwig=1.
There's little point in having Intel syntax disassembler tests when the
purpose of a test is assembler functionality: Drop all
*avx512*_vaes-wig1-intel.
For *avx512*_vaes-wig1 share source with *avx512*_vaes. This in
particular makes sure that the 32-bit VL test actually tests any EVEX
encodings in the first place.
Finally put in place similar tests for -mvexwig=1.
When no AVX512-specific functionality is in use, the disassembly of
AVX512VL insns is indistinguishable from their AVX counterparts (if such
exist). Emit the {evex} pseudo-prefix in such cases.
Where applicable drop stray uses of PREFIX_OPCODE from table entries.
Since
commit 837e225ba1
Author: Jan Beulich <jbeulich@suse.com>
Date: Thu Oct 20 10:01:12 2022 +0200
x86: re-work AVX-VNNI support
moved AVX-VNNI after AVX512-VNNI, vector Disp8 is applied even when VEX
encoding is selected. Check VEX/EVEX encoding before checking vector
operands to avoid vector Disp8 with VEX encoding.
PR gas/29708
* config/tc-i386.c (match_template): Check VEX/EVEX encoding
before checking vector operands.
* testsuite/gas/i386/avx-vnni.d: Updated.
* testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
* testsuite/gas/i386/avx-vnni.s: Add a Disp32 test.
* testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
By putting the templates after their AVX512 counterparts, the AVX512
flavors will be picked by default. That way the need to always use {vex}
ceases to exist once respective CPU features (AVX512-VNNI or AVX512VL as
a whole) have been disabled. This way the need for the PseudoVexPrefix
attribute also disappears.
Allows aarch64-pe to be targeted natively, not having to use objcopy to convert it from ELF to PE.
Based on initial work by Jedidiah Thompson
Co-authored-by: Jedidiah Thompson <wej22007@outlook.com>
Co-authored-by: Zac Walker <zac.walker@linaro.org>
As of commit ae89daecb1 ("x86: generalize disabling of sub-
architectures") there's no arbitrary subset of ISAs which can also be
disabled. This should have been reflected in documentation right away.
Since I failed to do so, correct this now.
Omitting predicate size specifier in vector form of {sq, uq, }{decp, incp} is deprecated and will be prohibited in a future release of the aarch64,
see https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions/DECP--vector---Decrement-vector-by-count-of-true-predicate-elements-.
This allows explicit size specifier, e.g. `decp z0.h, p0.h`, for predicate operand of these SVE instructions.
The existing behaviour of not requiring the specifier is preserved.
And the disasembly is with the specifier with this patch.
The GAS tests passed under our local tests.
opcodes/
* aarch64-asm.c: Modify `sve_size_hsd` encoding.
* aarch64-tbl.h (aarch64_opcode_table): Add QUALS's type OP_SVE_Vv_HSD
for decp, incp, sqdecp, sqincp, uqdecp and uqincp.
gas/
* testsuite/gas/aarch64/sve-movprfx_23.s: Update movprfx_23 testcase's
test_sametwo macro, where take the predicate size specifier.
* testsuite/gas/aarch64/sve-movprfx_23.d: Update movprfx_23 testcase's
expected disassembly.
* testsuite/gas/aarch64/sve-movprfx_23.l: Update movprfx_23 testcase's
expected assembler messages.
* testsuite/gas/aarch64/sve.s: Add sve testcase's instructions for
decp, incp, sqdecp, sqincp, uqdecp and uqincp, which take the
predicate size specifier.
* testsuite/gas/aarch64/sve.d: Update sve testcase's expected
disassembly.
Signed-off-by: CaiJingtao <caijingtao@huawei.com>
I noticed recently that se_rfmci, a VLE mode instruction, was being
accepted by non-VLE cpus, and also that se_rfmci by itself in a
section did not cause SHF_PPC_VLE to be set. ie. both testcases added
by this patch fail without the changes to tc-ppc.c here.
Also, VLE, SPE2 and LSP insns were not accepted by the assembler with
-many nor were SPE2 and LSP being disassembled with -Many.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Wrap long lines. Add
vle_opcodes when PPC_OPCODE_VLE or PPC_OPCODE_ANY. Simplify
disassembler index segment checks. Add LSP and SPE2 opcodes
when PPC_OPCODE_ANY too.
(md_assemble): Correct logic adding PPC_APUINFO_VLE and
SHF_PPC_VLE.
* testsuite/gas/ppc/se_rfmci.s
* testsuite/gas/ppc/se_rfmci.d,
* testsuite/gas/ppc/se_rfmci_bad.d: New tests.
* testsuite/gas/ppc/ppc.exp: Run them.
opcodes/
* ppc-dis.c (print_insn_powerpc): Disassemble SPE2 and LSP insn
when -Many.
* ppc-opc.c (vle_opcodes <se_rfmci>): Comment.
Where sub and subf forms of an instruction exist we generally
disassemble to the extended insn sub form rather than the underlying
machine subf instruction. Do so for SPE evsubw and evsubiw too.
spe_ambiguous.d always was a bit too optimistic. There is no sensible
way to disassemble identical bytes back to different and original
source. Instead change the test to check -Mraw results.
gas/
* testsuite/gas/ppc/ppc.exp: Run spe_ambiguous test.
* testsuite/gas/ppc/spe.d: Expect evsubw and evsubiw rather than
evsubfw and evsubifw.
* testsuite/gas/ppc/spe_ambiguous.s: Test evnor form equivalent
to evnot.
* testsuite/gas/ppc/spe_ambiguous.d: Test Mraw.
opcodes/
* ppc-opc.c (powerpc_opcodes): Move evsubw before evsubfw and
evsubiw before evsubifw and mark EXT.
It has bothered me for a long time that we have disabled LSP (and SPE)
tests. Also the LSP test comment indicating there is something wrong
with get_powerpc_dialect. I don't think there is. Decoding of a VLE
instruction depends on whether the processor is in VLE mode (some
processors support both VLE and standard PPC) which we flag per
section with SHF_PPC_VLE for decoding when disassembling.
Background: Some versions of powerpc e200 have "Lightweight Signal
Processing" support, examples being e200z215 and e200z425. As far as
I can tell, LSP and SPE are mutually exclusive. This seems to be
borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw"
have the same encoding. So none of the processor descriptions in
ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we
want disassembly to work. I also could not find anything to suggest
that the LSP insns are enabled only in VLE mode, which means the LSP
insns should not be in vle_opcodes.
Fix all this by moving the LSP insns to their own table, and add a new
e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from
-mvle. (Yes, I know, as I said above some of the e200z4 processors
have LSP. Others have SPE. It's hard to choose good options. Think
of z2 as meaning earlier, z4 as later.) Also add -mlsp to allow
adding the LSP insn set.
include/
* opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare.
(LSP_OP_TO_SEG): Define.
binutils/
* doc/binutils.texi: Update ppc docs.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash.
* doc/c-ppc.texi: Document e200 and lsp.
* testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2.
* testsuite/gas/ppc/lsp.d: Likewise, disassembly too.
* testsuite/gas/ppc/ppc.exp: Don't xfail lsp test.
opcodes/
* ppc-dis.c (ppc_opts): Add e200z2 and lsp. Don't set
PPC_OPCODE_LSP for e200z4 or vle.
(ppc_parse_cpu): Mutually exclude LSP and SPE.
(LSP_OPCD_SEGS): Define.
(lsp_opcd_indices): New array.
(disassemble_init_powerpc): Init lsp_opcd_indices.
(lookup_lsp): New function.
(print_insn_powerpc): Call it.
* ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout.
(vle_opcodes): Move LSP opcodes to..
(lsp_opcodes): ..here, and sort.
(lsp_num_opcodes): New.
'H', 'Smstateen', 'Sscofpmf' and 'Sstc' are four privileged extensions with
their CSR definitions and 'Smepmp' is a privileged extension with additional
CSR bits.
Volume II: Privileged Architecture of the RISC-V ISA Manual states that the
privileged architecture requires the 'Zicsr' extension. However, current
GNU Binutils has no direct way whether the program has dependency to the
privileged architecture itself.
As a workaround, we should add implications from privileged extensions that
either add new CSRs, extend existing CSRs or depends on using CSRs.
This commit adds such implications for existing privileged extensions that
satisfy this condition.
gas/ChangeLog:
* testsuite/gas/riscv/march-imply-h.d: New test, at least for 'H'.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zicsr'
implicications for privileged extensions 'H', 'Smstateen',
'Sscofpmf', 'Sstc' and 'Smepmp'.
* symbols.c (S_GET_VALUE): If the unresolved symbol is the fake
label provide a more helpful error message to the user.
(S_GET_VALUE_WHERE): Like S_GET_VALUE, but includes a file/line
number for error reporting purposes.
* symbols.h (S_GET_VALUE_WHERE): Prototype.
* write.c (fixup_segment): Use S_GET_VALUE_WHERE.
bfd/ChangeLog:
* bfd-in.h (bfd_hash_set_default_size): Add COMPRESS_UNKNOWN
enum value.
(struct compressed_type_tuple): New.
* bfd-in2.h (bfd_hash_set_default_size): Regenerate.
(struct compressed_type_tuple): Likewise.
* libbfd.c (ARRAY_SIZE): New macro.
(bfd_get_compression_algorithm): New function.
(bfd_get_compression_algorithm_name): Likewise.
gas/ChangeLog:
* as.c: Do not special-case, use the new functions.
ld/ChangeLog:
* emultempl/elf.em: Do not special-case, use the new functions.
* lexsup.c (elf_static_list_options): Likewise.
An earlier attempt (e68c3d59ac ["x86: better respect quotes in
parse_operands()"]) needed undoing (cc0f96357e ["x86: permit
parenthesized expressions again as addressing scale factor"]) as far its
effect here went. As indicated back then, the issue is the backwards
scanning of the operand string to find the matching opening parenthesis.
Switch to forward scanning, finding the last outermost unquoted opening
parenthesis (which is the one matching the trailing closing one).
Enable zlib-gnu compression for .gnu.debuglto_.debug_*. This differs
from zlib-gnu for .debug_* where the name is changed to .zdebug_*.
The name change isn't really needed.
bfd/
* elf.c (elf_fake_sections): Replace "." with ".z" in debug
section names only when name was ".d*", ie. ".debug_*".
(_bfd_elf_assign_file_positions_for_non_load): Likewise.
gas/
* write.c (compress_debug): Compress .gnu.debuglto_.debug_*
for zlib-gnu too. Compress .gnu.linkonce.wi.*.
Right now, when using LTO, the intermediate object files do contain
debug info in sections starting with .gnu.debuglto_ prefix and are
not compressed when --compress-debug-sections is used.
It's a mistake and we can save quite some disk space. The following
example comes from tramp3d when the corresponding LTO sections
are compressed with zlib:
$ bloaty tramp3d-v4-v2.o -- tramp3d-v4.o
FILE SIZE VM SIZE
-------------- --------------
+83% +10 [ = ] 0 [Unmapped]
-68.0% -441 [ = ] 0 .gnu.debuglto_.debug_line
-52.3% -759 [ = ] 0 .gnu.debuglto_.debug_line_str
-62.4% -3.24Ki [ = ] 0 .gnu.debuglto_.debug_abbrev
-64.8% -1.12Mi [ = ] 0 .gnu.debuglto_.debug_info
-88.8% -4.58Mi [ = ] 0 .gnu.debuglto_.debug_str
-27.7% -5.70Mi [ = ] 0 TOTAL
bfd/ChangeLog:
* elf.c (_bfd_elf_make_section_from_shdr): Compress all debug
info sections.
gas/ChangeLog:
* write.c (compress_debug): Compress also ".gnu.debuglto_.debug_"
if the compression algorithm is different from zlib-gnu.
There's no need for such workarounds anymore now that we use C99
uniformly. This addresses several testsuite failures encountered when
(cross-)building on a 32-bit host.
Although it had csr-dw-regnums.d (for CSRs), it didn't have DWARF register
number test for GPRs/FPRs.
This commit adds dw-regnums.{s,d} to test such registers.
gas/ChangeLog:
* testsuite/gas/riscv/dw-regnums.s: New DWARF register number test
for GPRs/FPRs.
* testsuite/gas/riscv/dw-regnums.d: Likewise.
This commit relaxes requirements to "fmv.s" instructions from 'F' to ('F'
or 'Zfinx'). The same applies to "fmv.d" and "fmv.q". Note that 'Zhinx'
extension already contains "fmv.h" instruction (as well as 'Zfh').
gas/ChangeLog:
* testsuite/gas/riscv/zfinx.s: Add "fmv.s" instruction.
* testsuite/gas/riscv/zfinx.d: Likewise.
* testsuite/gas/riscv/zdinx.s: Add "fmv.d" instruction.
* testsuite/gas/riscv/zdinx.d: Likewise.
* testsuite/gas/riscv/zqinx.d: Add "fmv.q" instruction.
* testsuite/gas/riscv/zqinx.s: Likewise.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Relax requirements to "fmv.[sdq]"
instructions to support those in 'Zfinx'/'Zdinx'/'Zqinx'.
This commit adds certain test cases for 'Zfinx'/'Zdinx'/'Zqinx' extensions
and reorganizes them, fixing coding style while improving coverage.
This is partially based on jiawei's 'Zhinx' testcases.
gas/ChangeLog:
* testsuite/gas/riscv/zfinx.s: Use different registers for
better encode space testing. Make indentation consistent.
Add tests for instruction with rounding mode. Change march
to minimum required extensions. Remove source line.
* testsuite/gas/riscv/zfinx.d: Likewise.
* testsuite/gas/riscv/zdinx.s: Likewise.
* testsuite/gas/riscv/zdinx.d: Likewise.
* testsuite/gas/riscv/zqinx.s: Likewise.
Also use even-numbered registers to use valid register pairs.
* testsuite/gas/riscv/zqinx.d: Likewise.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Signed-off-by: jiawei <jiawei@iscas.ac.cn>
Pre- and post-increment/decrement are side effects, the behavior of
which is undefined when combined with passing an address of the accessed
variable in the same function invocation. There's no need for the
increments here - simply adding 1 achieves the intended effect without
triggering compiler diagnostics (which are fatal with -Werror).
FENCE.TSO isn't an alias. ZIP and UNZIP in the long run likely are, but
presently they aren't. This fixes disassembly of these insns with
-Mno-aliases.
For disassembly to pick up aliases in favor of underlying insns (helping
readability in the common case), the aliases need to come ahead of the
"base" insns. Slightly more code movement is needed because of insns
with the same name needing to stay next to each other.
Note that the "rorw" alias entry also has the missing INSN_ALIAS added
here.
Clone a few testcases to exercise -Mno-aliases some more, better
covering the differences between the default and that disassembly mode.
At the example of
extractps $0, %xmm0, %xmm0
insertps $0, %xmm0, %eax
(both having respectively the same mistake of using the wrong kind of
destination register) it is easy to see that current behavior is far
from ideal: The former results in "unsupported instruction" for 32-bit
code simply because the 2nd template we have is a Cpu64 one. Instead we
should aim at emitting the "best" possible error, which will typically
be the one where we passed the largest number of checks. Generalize the
original "specific_error" approach by making it apply to the entire
matching loop, utilizing that line numbers increase as we pass further
checks.
While in some cases deriving an AT&T-style suffix from an Intel syntax
memory operand size specifier is necessary, in many cases this is not
only pointless, but has led to the introduction of various workarounds:
Excessive use of IgnoreSize and NoRex64 as well as the ToDword and
ToQword attributes. Suppress suffix derivation when we can clearly tell
that the memory operand's size isn't going to be needed to infer the
possible need for the low byte/word opcode bit or an operand size prefix
(0x66 or REX.W).
As a result ToDword and ToQword can be dropped entirely, plus a fair
number of IgnoreSize and NoRex64 can also be got rid of. Note that
IgnoreSize needs to remain on legacy encoded SIMD insns with GPR
operand, to avoid emitting an operand size prefix in 16-bit mode. (Since
16-bit code using SIMD insns isn't well tested, clone an existing
testcase just enough to cover a few insns which are potentially
problematic but are being touched here.)
Note that while folding the VCVT{,T}S{S,D}2SI templates, VCVT{,T}SH2SI
isn't included there. This is to fulfill the request of not allowing L
and Q suffixes there, despite the inconsistency with VCVT{,T}S{S,D}2SI.
PR29397 PR29563: Add new configure option --with-zstd which defaults to
auto. If pkgconfig/libzstd.pc is found, define HAVE_ZSTD and support
zstd compressed debug sections for most tools.
* bfd: for addr2line, objdump --dwarf, gdb, etc
* gas: support --compress-debug-sections=zstd
* ld: support ELFCOMPRESS_ZSTD input and --compress-debug-sections=zstd
* objcopy: support ELFCOMPRESS_ZSTD input for
--decompress-debug-sections and --compress-debug-sections=zstd
* gdb: support ELFCOMPRESS_ZSTD input. The bfd change references zstd
symbols, so gdb has to link against -lzstd in this patch.
If zstd is not supported, ELFCOMPRESS_ZSTD input triggers an error. We
can avoid HAVE_ZSTD if binutils-gdb imports zstd/ like zlib/, but this
is too heavyweight, so don't do it for now.
```
% ld/ld-new a.o
ld/ld-new: a.o: section .debug_abbrev is compressed with zstd, but BFD is not built with zstd support
...
% ld/ld-new a.o --compress-debug-sections=zstd
ld/ld-new: --compress-debug-sections=zstd: ld is not built with zstd support
% binutils/objcopy --compress-debug-sections=zstd a.o b.o
binutils/objcopy: --compress-debug-sections=zstd: binutils is not built with zstd support
% binutils/objcopy b.o --decompress-debug-sections
binutils/objcopy: zstd.o: section .debug_abbrev is compressed with zstd, but BFD is not built with zstd support
...
```
This patch adds support for the Zawrs ISA extension
("wrs.nto" and "wrs.sto" instructions).
The specification can be found here:
https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemPair extension, a collection of T-Head specific
two-GP-register memory operations.
The 'th' prefix and the "XTheadMemPair" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch introduces support for arbitrary literal instruction
arguments, that are not encoded in the opcode.
A typical use case for this feature would be an instruction that
applies an implicit shift by a constant value on an immediate
(that is a real operand). With this patch it is possible to make
this shift visible in the dissasembly and support such artificial
parameter as part of the asssembly code.
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemIdx extension, a collection of T-Head specific
GPR memory access instructions.
The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 44 instructions
(BU,HU,WU only for loads (zero-extend instead of sign-extend)):
* {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2
* {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
* {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadFMemIdx extension, a collection of
T-Head-specific floating-point memory access instructions.
The 'th' prefix and the "XTheadFMemIdx" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMac extension, a collection of
T-Head-specific multiply-accumulate instructions.
The 'th' prefix and the "XTheadMac" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadCondMov extension, a collection of
T-Head-specific conditional move instructions.
The 'th' prefix and the "XTheadCondMov" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XThead{Ba,Bb,Bs} extensions, a collection of
T-Head-specific bitmanipulation instructions.
The 'th' prefix and the "XThead{Ba,Bb,Bs}" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch introduces support for arbitrary signed or unsigned immediate
encoding formats. The formats have the form "XsN@S" and "XuN@S" with N
being the number of bits and S the LSB position.
For example an immediate field of 5 bytes that encodes a signed value
and is stored in the bits 24-20 of the instruction word can use the
format specifier "Xs5@20".
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadSync extension, a collection of
T-Head-specific multi-processor synchronization instructions.
The 'th' prefix and the "XTheadSync" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadCmo extension, a collection of T-Head specific
cache management operations.
The 'th' prefix and the "XTheadCmo" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 21 instructions:
* DCACHE.{C,CI,I}ALL
* DCACHE.{C,CI,I}{PA,VA,SW} rs1
* DCACHE.C{PAL1,VAL1} rs1
* ICACHE.I{ALL,ALLS}
* ICACHE.I{PA,VA} rs1
* L2CACHE.{C,CI,I}ALL
Contrary to Zicbom, the XTheadCmo instructions don't have a constant
displacement, therefore we have a different syntax for the arguments.
To clarify this is intended behaviour, there is a set of negative test
for Zicbom-style arguments in x-thead-cmo-fail.s.
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
v2:
- Add missing DECLARE_INSN() list
- Fix ordering
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch introduces changes that allow the integration of vendor ISA
extensions:
* Define a list of vendor extensions (riscv_supported_vendor_x_ext)
where vendor extensions can be added
* Introduce a section with a table in the documentation where vendor
extensions can be added
To add a vendor extension that consists of instructions only,
the following things need to be done:
* Add the extension to the riscv_supported_vendor_x_ext list
* Add lookup entry in riscv_multi_subset_supports
* Documenting the extension in c-riscv.texti
* Add test cases for all instructions
* Add MATCH*/MASK* constants and DECLARE_INSN() for all instructions
* Add new instruction class to enum riscv_insn_class
* Define the instructions in riscv_opcodes
* Additional changes if necessary (depending on the instructions)
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Although they are not (and should not be) reachable, following macro-only
operands are parsed in the `validate_riscv_insn' function and ignored.
That function also notes that they are macro-only.
- "A"
- "B"
- "I"
Following this convention, this commit adds three remaining macro-only
operands to this function. By doing this, we could instead choose to reject
those operands from appearing in regular instructions later.
- "c" (used by call, tail and jump macros)
- "VM" (used by vmsge.vx and vmsgeu.vx macros)
- "VT" (likewise)
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Add "c", "VM" and "VT"
macro-only operand types.
To avoid -Werror=strict-prototypes, this commit changes () to (void).
This is because "()" possibly means a function prototype with indeterminate
arguments on old C standards.
gas/ChangeLog:
* config/tc-riscv.c (riscv_set_tso): Fix declaration.
This is a minor fix to commit 96462b0129
("RISC-V: Implement Ztso extension"). Currently, it sets EF_RISCV_TSO ELF
flag when initial ISA string contains the 'Ztso' extension. However, GAS
has a way to update the ISA string: ".option arch".
When the architecture is updated by ".option arch", EF_RISCV_RVC ELF flag
is set when the 'C' extension is detected. Analogously, this commit sets
the EF_RISCV_TSO when the 'Ztso' extension is detected.
gas/ChangeLog:
* config/tc-riscv.c (s_riscv_option): Set TSO ELF flag if the
'Ztso' extension is specified via ".option arch" directive.
This patch support ZTSO extension. It will turn on the tso flag for elf_flags
once we have enabled Ztso extension. This is intended to implement v0.1 of
the proposed specification which can be found in Chapter 25 of,
https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf.
bfd\ChangeLog:
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag.
* elfxx-riscv.c: Add Ztso's arch.
binutils\ChangeLog:
* readelf.c (get_machine_flags): Set TSO flag.
gas\ChangeLog:
* config/tc-riscv.c (riscv_set_tso): Ditto.
(riscv_set_arch): Ditto.
* testsuite/gas/riscv/ztso.d: New test.
include\ChangeLog:
* elf/riscv.h (EF_RISCV_TSO): Ditto.
Since we have the same behaviors of CALL and CALL_PLT relocs in linker for now,
3b1450b38c
And the psabi already deprecate the CALL reloc,
a0dced8501
Therefore, we should always generate R_RISCV_CALL_PLT reloc for call, even if
it has @plt postfix. I believe LLVM (https://reviews.llvm.org/D132530) already
support this, so GNU as should do the same thing.
gas/
* config/tc-riscv.c (riscv_ip): Always generate CALL_PLT reloc for
call, even if it has @plt postfix.
* testsuite/gas/riscv/no-relax-reloc.d: Updated CALL to CALL_PLT.
* testsuite/gas/riscv/relax-reloc.d: Likewise.
ld/
* testsuite/ld-riscv-elf/variant_cc-r.d: Updated CALL to CALL_PLT.
The last patch wasn't all that shiny. There are rather a lot more
relocations that can hit the assertion in md_apply_fix if the symbol
is local or absolute. Fix them all.
* config/tc-ppc.c (ppc_force_relocation): Add all relocs that
expect a symbol in md_apply_fix. Remove tls pcrel relocs
already covered in general tls match range.
Not that anyone would want to indirect via the GOT when an address can
be loaded directly with pla, the following:
pld 3,x@got@pcrel
x:
leads to "Internal error in md_apply_fix", because the generic parts
of assembler fixup handling convert the fx_pcrel fixup to one without
a symbol. Stop that happening.
* config/tc-ppc.c (ppc_force_relocation): Add PLT_PCREL34 and
assorted GOT_PCREL34 relocs.
Clang generates a warning on unused (technically, written but not read
thereafter) variables. By the default configuration (with "-Werror"), it
causes a build failure (unless "--disable-werror" is specified).
This commit adds ATTRIBUTE_UNUSED attribute to some of them, which means
they are *possibly* unused (can be used but no warnings occur when
unused) and removes others.
bfd/ChangeLog:
* elf32-lm32.c (lm32_elf_size_dynamic_sections): Mark unused
rgot_count variable.
* elf32-nds32.c (elf32_nds32_unify_relax_group): Remove unused
count variable.
* mmo.c (mmo_scan): Mark unused lineno variable.
binutils/ChangeLog:
* windmc.c (write_rc): Remove unused i variable.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Remove unused argnum variable.
ld/ChangeLog:
* pe-dll.c (generate_reloc): Remove unused bi and page_count
variables.
Some components of GNU Binutils will pass "-Wstack-usage=262144" when
"GCC >= 5.0" is detected. However, Clang does not support "-Wstack-usage",
despite that related configuration part in bfd/warning.m4 handles the latest
Clang (15.0.0 as of this writing) as "GCC >= 5.0".
The option "-Wstack-usage" was ignored when the first version of Clang is
released but even this "ignoring" behavior is removed before Clang 4.0.0.
So, if we give Clang "-Wstack-usage=262144", it generates a warning, making
the build failure.
This commit checks "__clang__" macro to prevent adding the option if the
compiler is identified as Clang.
bfd/ChangeLog:
* warning.m4: Stop appending "-Wstack-usage=262144" option when
compiled with Clang.
* configure: Regenerate.
binutils/ChangeLog:
* configure: Regenerate.
gas/ChangeLog:
* configure: Regenerate.
gold/ChangeLog:
* configure: Regenerate.
gprof/ChangeLog:
* configure: Regenerate.
ld/ChangeLog:
* configure: Regenerate.
opcodes/ChangeLog:
* configure: Regenerate.
The -mfuture and -Mfuture options which are used for adding potential
new ISA instructions were not documented. They also lacked a bitmask
so new instructions could not be enabled by those options. Fixed.
binutils/
* doc/binutils.texi: Document -Mfuture.
gas/
* config/tc-ppc.c: Document -mfuture
* doc/c-ppc.texi: Likewise.
include/
* opcode/ppc.h (PPC_OPCODE_FUTURE): Define.
opcodes/
* ppc-dis.c (ppc_opts) <future>: Use it.
* ppc-opc.c (FUTURE): Define.
It looks like I copied the SIZE init across from
binutils/testsuite/config/default.exp without some necessary editing.
* testsuite/config/default.exp (SIZE): Adjust relative path.
Vector CSRs are also required on smaller vector subsets.
Not only that the most of vector CSRs are general purpose (and must be
accessible for every vector subsets), current minimum vector subset 'Zve32x'
requires fixed point arithmetic, making remaining non-general purpose
(fixed point arithmetic only) CSRs mandatory for such subsets.
So, those CSRs must be accessible from 'Zve32x', not just from 'V'.
This commit fixes this issue which caused CSR accessibility warnings.
gas/ChangeLog:
* config/tc-riscv.c (riscv_csr_address): Change vector CSR
requirement from 'V' to 'Zve32x'.
* testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR
requirement from 'V' to 'Zve32x'.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
PR 29559
* dwarf2dbg.c (out_debug_info): Place DW_TAG_unspecified_type at
the end of the list of children, not at the start of the CU
information.
* testsuite/gas/elf/dwarf-3-func.d: Update expected output.
* testsuite/gas/elf/dwarf-5-func-global.d: Likewise.
* testsuite/gas/elf/dwarf-5-func-local.d: Likewise.
* testsuite/gas/elf/dwarf-5-func.d: Likewise.
This patch makes possible to print the highest address (-1) and the addresses
related to gp which value is -1. This is particularly useful if the highest
address space is used for I/O registers and corresponding symbols are defined.
Besides, despite that it is very rare to have GP the highest address, it would
be nice because we enabled highest address printing on regular cases.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-topaddr.s: New test for the top
address (-1) printing.
* testsuite/gas/riscv/dis-addr-topaddr-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-64.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp.s: New test for
GP-relative addressing when GP is the highest address (-1).
* testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise.
opcodes/ChangeLog:
* riscv-dis.c (struct riscv_private_data): Add `to_print_addr' to
enable printing the highest address.
(maybe_print_address): Utilize `to_print_addr'.
(riscv_disassemble_insn): Likewise.
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an
incorrectly sign-extended address is produced when printing. This commit
fixes this by fitting an address into a 32-bit value on RV32.
Besides, H. Peter Anvin discovered that we have wrong address computation
for JALR instruction (the initial bug is back in 2018). This commit also
fixes that based on the idea of Palmer Dabbelt.
gas/
pr29342
* testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix.
* testsuite/gas/riscv/dis-addr-overflow.s: New testcase.
* testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.
opcodes/
pr29342
* riscv-dis.c (maybe_print_address): Fit address into 32-bit on RV32.
(print_insn_args): Fix JALR address by adding EXTRACT_ITYPE_IMM.
Address sequences involving ADDIW/C.ADDIW instructions require special
handling to sign-extend lower 32-bits of the original result.
This commit tests whether this sign-extension works.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw.s: New to test the address
computation with sign extension as used in ADDIW/C.ADDIW.
* testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0.
* testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw-a.d: New test.
* testsuite/gas/riscv/dis-addr-addiw-b.d: New test.
* testsuite/gas/riscv/dis-addr-addiw.s: New test.
Running configure and make in binutils-gdb.
$ ./configure
$ make
In file included from ./as.h:37,
from ./config/loongarch-lex.l:21,
from config/loongarch-lex-wrapper.c:20:
./config.h:206: error: “PACKAGE” redefined [-Werror]
#define PACKAGE "gas"
...
gas/config
* loongarch-lex-wrapper.c
Three-part patch set from Tsukasa OI to support zmmul in assembler.
The 'Zmmul' is a RISC-V extension consisting of only multiply instructions
(a subset of 'M' which has multiply and divide instructions).
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'.
(riscv_supported_std_z_ext): Add 'Zmmul' extension.
(riscv_multi_subset_supports): Add handling for new instruction class.
gas/
* testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'.
* testsuite/gas/riscv/option-arch-02.d: Likewise.
* testsuite/gas/riscv/m-ext.s: New test.
* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
* testsuite/gas/riscv/zmmul-32.d: New expected output.
* testsuite/gas/riscv/zmmul-64.d: Likewise.
* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
by using RV64-only instructions in RV32).
* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test
(RV32 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test
(RV64 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test
(no Zmmul or M).
* testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise.
include/
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in
these testcases, so just replaced m by a.
* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed.
opcodes/
* riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
out_inc_line_addr and relax_inc_line_addr are passed INT_MAX as
line_delta to flag end of section. This filters its way down to
size_inc_line_addr and emit_inc_line_addr. Pass line_delta on to
scale_addr_delta where it can be used to omit an unaligned opcode
error.
PR 29494
* dwarf2dbg.c (scale_addr_delta): Delete unnecessary forward decl.
Add line_delta param. Don't print error at end of section, just
round the address down.
(size_inc_line_addr, emit_inc_line_addr): Adjust calls.
PR 29517
* dwarf2dbg.c (GAS_ABBREV_COMP_UNIT): New defined constant.
(GAS_ABBREV_SUBPROG): New defined constant.
(GAS_ABBREV_NO_TYPE): New defined constant.
(out_debug_abbrev): Use the new defined constants when emitting
abbreviation numbers. Generate an abbreviation for an unspecified
type.
(out_debug_info): Use the new defined constants when referring to
abbreviations. Generate a use of the no_type abbreviation.
Reference the use when generating DIEs for functions.
* testsuite/gas/elf/dwarf-3-func.d: Update to allow for newly
extended output from the assembler.
* testsuite/gas/elf/dwarf-5-func-global.d: Likewise.
* testsuite/gas/elf/dwarf-5-func-local.d: Likewise.
* testsuite/gas/elf/dwarf-5-func.d: Likewise.
PR 29519
* config/tc-aarch64.c (s_unreq): Use find_end_of_line().
(s_aarch64_cpu): Likewise.
(s_aarch64_arch): Likewise.
(s_aarch64_arch_extension): Likewise.
* testsuite/gas/aarch64/pr29519.d: New test driver file.
* testsuite/gas/aarch64/pr29519.s: New test source file.
There's been a long-standing bug in the arm backend where
target-specific directives did not correctly handle lines with
multiple statements. This patch fixes the issue for all the cases
I've been able to find.
It does result in a slight change in behaviour when errors are
encountered: where, previously,
.cpu arm6 bar
would result in the error "junk at end of line, first unrecognized
character is `b'", we now get "unknown cpu `arm6 bar'", which I think
is slightly more helpful anyway. Similar errors are generated for
other directives.
Instructions that can load immediate support using constant
variable like ".equ var, 123 li.w/d resgister, var".
gas/
* config/loongarch-parse.y
* config/tc-loongarch.c
Add four testcases.One is a program using constant variable,
one test using label is unsupported, and another two test
almost instructions that can load immediate.
gas/
* testsuite/gas/loongarch/li.d
* testsuite/gas/loongarch/li.s
* testsuite/gas/loongarch/imm_ins_label-fail.d
* testsuite/gas/loongarch/imm_ins_label-fail.l
* testsuite/gas/loongarch/imm_ins_label-fail.s
* testsuite/gas/loongarch/imm_ins.d
* testsuite/gas/loongarch/imm_ins.s
* testsuite/gas/loongarch/imm_ins_32.d
* testsuite/gas/loongarch/imm_ins_32.s
Emitting this warning for every insn, including ones having actual
errors, is annoying. Introduce a boolean variable to emit the warning
just once on the first insn after .arch may have changed the things, and
move the warning to output_insn(). (I didn't want to go as far as
checking whether the .arch actually turned off the i386 bit, but doing
so would be an option.)
When displaying operands, invalid opcodes may overflow operand buffer
due to additional styling characters. Each style is encoded with 3
bytes. Define MAX_OPERAND_BUFFER_SIZE for operand buffer size and
increase it from 100 bytes to 128 bytes to accommodate 9 sets of styles
in an operand.
gas/
PR binutils/29483
* testsuite/gas/i386/i386.exp: Run pr29483.
* testsuite/gas/i386/pr29483.d: New file.
* testsuite/gas/i386/pr29483.s: Likewise.
opcodes/
PR binutils/29483
* i386-dis.c (MAX_OPERAND_BUFFER_SIZE): New.
(obuf): Replace 100 with MAX_OPERAND_BUFFER_SIZE.
(staging_area): Likewise.
(op_out): Likewise.
This changes readelf output a little, removing the 0x prefix on hex
output when the value is 0, except in cases where a fixed field
width is shown. %#010x is not a good replacement for 0x%08x.
svstep and svshape instructions subtract 1 before encoding some of the
operands. Obviously zero is not supported for these operands. Whilst
PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be
incremented, there is no flag which marks the fact that zero values are
not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this
purpose.
This patch adds support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
For more details, visit https://libre-soc.org.
Commit 53f2b36a54 exposed a bug in sb_scrub_and_add_sb that could
result in losing input. If scrubbing results in expansion past the
holding capacity of do_scrub_chars output buffer, then do_scrub_chars
stashes the extra input for the next call. That call never came
because sb_scrub_and_add_sb wrongly decided it was done. Fix that by
allowing sb_scrub_and_add_sb to see whether there is pending input.
Also allow a little extra space so that in most cases we won't need
to resize the output buffer.
sb_scrub_and_add_sb also limited output to the size of the input,
rather than the actual output buffer size. Fixing that resulted in a
fail of gas/testsuite/macros/dot with an extra warning: "end of file
not at end of a line; newline inserted". OK, so the macro in dot.s
really does finish without end-of-line. Apparently the macro
expansion code relied on do_scrub_chars returning early. So fix that
too by adding a newline if needed in macro_expand_body.
PR 29466
* app.c (do_scrub_pending): New function.
* as.h: Declare it.
* input-scrub.c (input_scrub_include_sb): Add extra space for
two .linefile directives.
* sb.c (sb_scrub_and_add_sb): Take into account pending input.
Allow output to max.
* macro.c (macro_expand_body): Add terminating newline.
* testsuite/config/default.exp (SIZE, SIZEFLAGS): Define.
* testsuite/gas/macros/app5.d,
* testsuite/gas/macros/app5.s: New test.
* testsuite/gas/macros/macros.exp: Run it.
PR gas/29451
While out_debug_abbrev() properly skips such functions, out_debug_info()
mistakenly didn't. It needs to calculate the high_pc expression ahead of
time, in order to skip emitting any data for the function if the value
is zero.
The one case which would still leave a zero-size entry is when
symbol_get_obj(symp)->size ends up evaluating to zero. I hope we can
expect that to not be the case, otherwise we'd need to have a way to
post-process .debug_info contents between resolving expressions and
actually writing the data out to the file. Even then it wouldn't be
entirely obvious in which way to alter the data.
It is unclear to me why the corresponding MOV (no Q suffix) can be
issued without REX.W, but MOVQ has to have that prefix (bit). Add
NoRex64 and in exchange drop Size64.
While the x/y/z suffix isn't necessary to use in this case, it is still
odd that these forms don't support broadcast (unlike their AVX512F /
AVX512DQ counterparts). The lack thereof can e.g. make macro-ized
programming more difficult.
The commit 1369522f36 ("Recognize the new ELF
compression type for ZSTD.") added the new ELF compression type but it
accidentally broke a GAS testcase. Since testing for the section type
"2048" (SHF_COMPRESSED) is not going to be portable in the long term, it
now tests SHF_LINK_ORDER ("128") instead.
Using SHF_LINK_ORDER (with possibly sh_link == 0) is an idea by Jan Beulich.
gas/ChangeLog:
* testsuite/gas/elf/section10.s: Use SHF_LINK_ORDER to test
mixed numeric and alpha values.
* testsuite/gas/elf/section10.d: Reflect the change above.
BFD_VMA_FMT can't be used in format strings that need to be
translated, because the translation won't work when the type of
bfd_vma differs from the machine used to compile .pot files. We've
known about this for a long time, but patches slip through review.
So just get rid of BFD_VMA_FMT, instead using the appropriate PRId64,
PRIu64, PRIx64 or PRIo64 and SCN variants for scanf. The patch is
mostly mechanical, the only thing requiring any thought is casts
needed to preserve PRId64 output from bfd_vma values, or to preserve
one of the unsigned output formats from bfd_signed_vma values.
- Drop the rounding type check: We're past template matching, and none
of the involved insns support embedded rounding.
- Drop the extension opcode check: None of the involved opcodes have
variants with it being other than None.
- Instead check opcode space, even if just to be on the safe side going
forward.
- Reduce the number of comparisons by folding two groups.
First of all rename the meanwhile misleading Opcode_SIMD_FloatD, as it
has also been used for KMOV* and BNDMOV. Then simplify the condition
selecting which form if "reversing" to use - except for the MOV to/from
control/debug/test registers all extended opcode space insns use bit 0
(rather than bit 1) to indicate the direction (from/to memory) of an
operation. With that, D can simply be set on the first of the two
templates, while the other can be dropped.
This patch extends assembler support for the use of register names to
allow for pseudo-registers, e.g. ra_auth_code register.
This is done particularly with CFI directives in mind, allowing for
expressions of the type:
.cfi_register ra_auth_code, 12
gas/Changelog:
* config/tc-arm.c (tc_arm_regname_to_dw2regnum): Add
REG_TYPE_PSEUDO handling.
* testsuite/gas/arm/cfi-pacbti-m-readelf.d: New.
* testsuite/gas/arm/cfi-pacbti-m.s: New.
This patch modifies the internal `struct reg_entry' numbering of DWARF
pseudo-registers to match values assigned in DWARF standards (see "4.1
DWARF register names" in [1])so ra_auth_code goes from 12 to 143 and
amends the unwinder .save directive-processing code to correctly handle
mixed register-type save directives.
The mechanism for splitting the register list is also re-written to
comply with register ordering on push statements, being that registers
are stored on the stack in numerical order, with the lowest numbered
register at the lowest address [2].
Consequently, the parsing of the hypothetical directive
.save{r4-r7, r10, ra_auth_core, lr}
has been changed such as rather than producing
.save{r4-r7, r10}
.save{ra_auth_code}
.save{lr}
as was the case with previous implementation, now produces:
.save{lr}
.save{ra_auth_code}
.save{r4-r7, r10}
[1] <https://github.com/ARM-software/abi-aa/blob/main/aadwarf32/aadwarf32.rst>
[2] <https://developer.arm.com/documentation/dui0473/j/arm-and-thumb-instructions/push>
gas/Changelog:
* config/tc-arm.c (REG_RA_AUTH_CODE): New.
(parse_dot_save): Likewise.
(parse_reg_list): Remove obsolete code.
(reg_names): Set ra_auth_code to 143.
(s_arm_unwind_save): Handle core and pseudo-register lists via
parse_dot_save.
(s_arm_unwind_save_mixed): Deleted.
(s_arm_unwind_save_pseudo): Handle one register at a time.
* testsuite/gas/arm/unwind-pacbti-m-readelf.d: Fix test.
* testsuite/gas/arm/unwind-pacbti-m.d: Likewise.
This syntactic sugar is present in both classical and emerging
architectures, like Alpha, SPARC and RISC-V, and assembler macros
doing the same thing can already be found in the wild e.g. [1], proving
the feature's popularity. It's better to provide support directly in the
assembler so downstream users wouldn't have to re-invent this over and
over again.
[1]: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/unix/sysv/linux/loongarch/sysdep.h;h=c586df819cd90;hb=HEAD#l28
Also re-order the jump/branch opcodes while at it, so that insns are
sorted in ascending order according to opcodes, and the label form
preceding the real definition.
These two macros print either a 16 digit hex number or an 8 digit
hex number. Unfortunately they depend on both target and host, which
means that the output for 32-bit targets may be either 8 or 16 hex
digits.
Replace them in most cases with code that prints a bfd_vma using
PRIx64. In some cases, deliberately lose the leading zeros.
This change some output, notably in base/offset fields of m68k
disassembly which I think looks better that way, and in error
messages. I've kept leading zeros in symbol dumps (objdump -t)
and in PE header dumps.
bfd/
* bfd-in.h (fprintf_vma, sprintf_vma, printf_vma): Delete.
* bfd-in2.h: Regenerate.
* bfd.c (bfd_sprintf_vma): Don't use sprintf_vma.
(bfd_fprintf_vma): Don't use fprintf_vma.
* coff-rs6000.c (xcoff_reloc_type_tls): Don't use sprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(xcoff_ppc_relocate_section): Likewise.
* cofflink.c (_bfd_coff_write_global_sym): Likewise.
* mmo.c (mmo_write_symbols_and_terminator): Likewise.
* srec.c (srec_write_symbols): Likewise.
* elf32-xtensa.c (print_r_reloc): Similarly for fprintf_vma.
* pei-x86_64.c (pex64_dump_xdata): Likewise.
(pex64_bfd_print_pdata_section): Likewise.
* som.c (som_print_symbol): Likewise.
* ecoff.c (_bfd_ecoff_print_symbol): Use bfd_fprintf_vma.
opcodes/
* dis-buf.c (perror_memory, generic_print_address): Don't use
sprintf_vma. Instead use PRIx64 to print bfd_vma values.
* i386-dis.c (print_operand_value, print_displacement): Likewise.
* m68k-dis.c (print_base, print_indexed): Likewise.
* ns32k-dis.c (print_insn_arg): Likewise.
* ia64-gen.c (_opcode_int64_low, _opcode_int64_high): Delete.
(opcode_fprintf_vma): Delete.
(print_main_table): Use PRIx64 to print opcode.
binutils/
* od-macho.c: Replace all uses of printf_vma with bfd_printf_vma.
* objcopy.c (copy_object): Don't use sprintf_vma. Instead use
PRIx64 to print bfd_vma values.
(copy_main): Likewise.
* readelf.c (CHECK_ENTSIZE_VALUES): Likewise.
(dynamic_section_mips_val): Likewise.
(print_vma): Don't use printf_vma. Instead use PRIx64 to print
bfd_vma values.
(dump_ia64_vms_dynamic_fixups): Likewise.
(process_version_sections): Likewise.
* rddbg.c (stab_context): Likewise.
gas/
* config/tc-i386.c (offset_in_range): Don't use sprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(md_assemble): Likewise.
* config/tc-mips.c (load_register, macro): Likewise.
* messages.c (as_internal_value_out_of_range): Likewise.
* read.c (emit_expr_with_reloc): Likewise.
* config/tc-ia64.c (note_register_values): Don't use fprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(print_dependency): Likewise.
* listing.c (list_symbol_table): Use bfd_sprintf_vma.
* symbols.c (print_symbol_value_1): Use %p to print pointers.
(print_binary): Likewise.
(print_expr_1): Use PRIx64 to print bfd_vma values.
* write.c (print_fixup): Use %p to print pointers. Don't use
fprintf_vma.
* testsuite/gas/all/overflow.l: Update expected output.
* testsuite/gas/m68k/mcf-mov3q.d: Likewise.
* testsuite/gas/m68k/operands.d: Likewise.
* testsuite/gas/s12z/truncated.d: Likewise.
ld/
* deffilep.y (def_file_print): Don't use fprintf_vma. Instead
use PRIx64 to print bfd_vma values.
* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Don't use
sprintf_vma. Instead use PRIx64 to print bfd_vma values.
* emultempl/pe.em (gld${EMULATION_NAME}_finish): Likewise.
* ldlang.c (lang_map): Use %V to print region origin.
(lang_one_common): Don't use sprintf_vma.
* ldmisc.c (vfinfo): Don't use fprintf_vma or sprintf_vma.
* pe-dll.c (pe_dll_generate_def_file): Likewise.
gdb/
* remote.c (remote_target::trace_set_readonly_regions): Replace
uses of sprintf_vma with bfd_sprintf_vma.
This commit enables disassembler styling for AArch64. After this
commit it is possible to have objdump style AArch64 disassembler
output (using --disassembler-color option). Once the required GDB
patches are merged, GDB will also style the disassembler output.
The changes to support styling are mostly split between two files
opcodes/aarch64-dis.c and opcodes/aarch64-opc.c.
The entry point for the AArch64 disassembler can be found in
aarch64-dis.c, this file handles printing the instruction mnemonics,
and assembler directives (e.g. '.byte', '.word', etc). Some operands,
mostly relating to assembler directives are also printed from this
file. This commit changes all of this to pass through suitable
styling information.
However, for most "normal" instructions, the instruction operands are
printed using a two step process. From aarch64-dis.c, in the
print_operands function, the function aarch64_print_operand is called,
this function is in aarch64-opc.c, and converts an instruction operand
into a string. Then, back in print_operands (aarch64-dis.c), the
operand string is printed.
Unfortunately, the string returned by aarch64_print_operand can be
quite complex, it will include syntax elements, like '[' and ']', in
addition to register names and immediate values. In some cases, a
single operand will expand into what will appear (to the user) as
multiple operands separated with a ','.
This makes the task of styling more complex, all these different
components need to by styled differently, so we need to get the
styling information out of aarch64_print_operand in some way.
The solution that I propose here is similar to the solution that I
used for the i386 disassembler.
Currently, aarch64_print_operand uses snprintf to write the operand
text into a buffer provided by the caller.
What I propose is that we pass an extra argument to the
aarch64_print_operand function, this argument will be a structure, the
structure contains a callback function and some state.
When aarch64_print_operand needs to format part of its output this can
be done by using the callback function within the new structure, this
callback returns a string with special embedded markers that indicate
which mode should be used for each piece of text. Back in
aarch64-dis.c we can spot these special style markers and use this to
split the disassembler output up and apply the correct style to each
piece.
To make aarch64-opc.c clearer a series of new static functions have
been added, e.g. 'style_reg', 'style_imm', etc. Each of these
functions formats a piece of text in a different style, 'register' and
'immediate' in this case.
Here's an example taken from aarch64-opc.c of the new functions in
use:
snprintf (buf, size, "[%s, %s]!",
style_reg (styler, base),
style_imm (styler, "#%d", opnd->addr.offset.imm));
The aarch64_print_operand function is also called from the assembler
to aid in printing diagnostic messages. Right now I have no plans to
add styling to the assembler output, and so, the callback function
used in the assembler ignores the styling information and just returns
an plain string.
I've used the source files in gas/testsuite/gas/aarch64/ for testing,
and have manually gone through and checked that the styling looks
reasonable, however, I'm not an AArch64 expert, so it is possible that
the odd piece is styled incorrectly. Please point out any mistakes
I've made.
With objdump disassembler color turned off, there should be no change
in the output after this commit.
The original approach has resulted in anomalies when . is involved in an
operand of one of the affected insns. We cannot leave . unresolved, or
else it'll be resolved at the end of assembly, then pointing to the
address of a section rather than at the insn of interest. Undo part of
the original change and instead check whether a relocation cannot be
omitted in md_apply_fix().
By resolving the expressions again, equates (see the adjustment of the
respective testcase) will now be evaluated, and hence relocations
against absolute addresses be emitted. This ought to be okay as long as
the equates aren't global (and hence can't be overridden). If a need
for such arises, quite likely the only way to address this would be to
invent yet another expression evaluation mode, leaving everything
_except_ . un-evaluated.
There's a further anomaly in how transitive equates are handled. In
.set x, 0x12345678
.eqv bar, x
foo:
adrp x0, x
add x0, x0, :lo12:x
adrp x0, bar
add x0, x0, :lo12:bar
the first two relocations are now against *ABS*:0x12345678 (as said
above), whereas the latter two relocations would be against x. (Before
the change here, the first two relocations are against x and the latter
two against bar.) But this is an issue seen elsewhere as well, and would
likely require adjustments in the target-independent parts of the
assembler instead of trying to hack around this for every target.
This commit adds `OP_V' (OP-V: vector instruction opcode for now
ratified `V' extension) to .insn opcode name list. Although vector
instruction encoding is not implemented in `.insn' directive, it will
help future implementation of custom vector `.insn'.
gas/ChangeLog:
* config/tc-riscv.c (opcode_name_list): Add `OP_V'.
* testsuite/gas/riscv/insn.s: Add testcase.
* testsuite/gas/riscv/insn.d: Likewise.
* testsuite/gas/riscv/insn-dwarf.d: Reflect insn.s update.
I clearly screwed up in 6ff00b5e12 ("x86/Intel: correct permitted
operand sizes for AVX512 scatter/gather") giving all AVX512F scatter
insns Dword element size. Update testcases (also their gather parts),
utilizing that there previously were two identical lines each (for no
apparent reason).
Assuming GMSD is a special operand, marked as O_md1, the code:
.set VREG, GMSD
.set REG, VREG
extsw REG, 2
...fails upon attempts to resolve the value of the symbol. This happens
since machine-dependent values are not handled in the giant op switch.
We introduce a custom md_resolve_symbol macro; the ports can use this
macro to customize the behavior when resolve_symbol_value hits O_md
operand.
The ciphers 5,7, and 9 are missing when parsing an assembly
instruction leading to errors when those ciphers are
used.
gas/config
* tc-arc.c (md_assembly): Update strspn string with the
missing ciphers.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
Both forms were missing VexW0 (thus allowing Evex.W=1 to be encoded by
suitable means, which would cause #UD). The memory operand form further
was using the wrong Masking value, thus allowing zeroing-masking to be
encoded for the store form (which would again cause #UD).
I meant to make this change before committing, to let compilers know
the code on the false branch of md_parse_name is dead.
* config/tc-ppc.c (ppc_parse_name): Return void.
* config/tc-ppc.h (md_parse_name): Always true.
(ppc_parse_name): Update prototype.
Allows register names to appear in symbol assignments, so for example
tocp = %r2
mr %r3,tocp
now assembles.
* gas/config/tc-ppc.c (REG_NAME_CNT): Delete, replace uses with
ARRAY_SIZE.
(register_name): Rename to..
(md_operand): ..this. Only handle %reg.
(cr_names): Rename to..
(cr_cond): ..this. Just keep conditions.
(ppc_parse_name): Add mode param. Search both cr_cond and
pre_defined_registers. Handle absolute and register symbol
values here rather than in expr.c:operand().
(md_assemble): Don't special case register name matching in
operands, except to set cr_operand as appropriate.
* gas/config/tc-ppc.h (md_operand): Don't define.
(md_parse_name, ppc_parse_name): Update.
* read.c (pseudo_set): Copy over entire O_register value.
* testsuite/gas/ppc/regsyms.d.
* testsuite/gas/ppc/regsyms.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
It might be possible to hit md_end before md_begin is called, don't
segfault if so. Also, remove a useless check.
* gas/config/tc-ppc.c (insn_calloc): Remove needless overflow
check.
(ppc_md_end): Check ppc_hash before deleting. Clear ppc_hash.
Cleaning up the subsym_hash memory is a real pain. Keys and values
entered into the table are quite diverse. In some cases the key is
allocated and thus needs to be freed, in others the key is a const
string. Values are similar, and in some cases not even a string.
Tidy this by inserting a new subsym_ent_t that describes key/value
type. This meant the math_hash table was no longer needed. The patch
also tidies how math functions are called, those that are supposed to
return int now no longer return their value in a float.
* config/tc-tic54x.c (math_hash): Delete.
(subsym_proc_entry): Move earlier, make proc a union, merge with..
(math_proc_entry): ..this. Delete type.
(math_procs): Merge into subsym_procs.
(subsym_ent_t): New. Use this type in subsym_hash..
(stag_add_field_symbols, tic54x_var, tic54x_macro_info): ..here..
(md_begin, subsym_create_or_replace, subsym_lookup): ..and here..
(subsym_substitute): ..and here. Adjust subsym_proc_entry
function calls. Free replacement when not returned.
(subsym_get_arg): Adjust subsym_lookup.
(free_subsym_ent, subsym_htab_create ): New functions, use when
creating subsym_hash.
(free_local_label_ent, local_label_htab_create): Similarly.
(tic54x_remove_local_label): Delete.
(tic54x_clear_local_labels): Simplify.
(tic54x_asg): Use notes obstack to dup strings.
(tic54x_eval): Likewise.
(subsym_ismember): Likewise.
(math_cvi, math_int, math_sgn): Return int.
(tic54x_macro_start): Decrement macro_level before calling as_fatal.
(tic54x_md_end): New function.
* config/tc-tic54h.c (tic54x_md_end): Declare.
(md_end): Define.
Using notes_calloc means all of the string hash table memory should
now be freed before gas exits, even though htab_delete isn't called.
This also means that the hash table free_f and del_f must be NULL,
because freeing notes obstack memory results in all more recently
allocated notes memory being freed too. So hash table resizing won't
free any memory, and will be a little faster. Also, htab_delete won't
do anything (and be quick about it).
Since htab_traverse can also resize hash tables (to make another
traversal faster if the table is largely empty), stop that happening
when only one traversal is done.
* as.h: Reorder hash.h after symbols.h for notes_calloc decl.
* hash.h (str_htab_create): Use notes_calloc. Do not free.
* symbols.c (resolve_local_symbol_values): Don't resize
during hash table traversal.
* config/obj-elf.c (elf_frob_file_after_relocs): Likewise.
* config/tc-ia64.c (ia64_adjust_symtab, ia64_frob_file): Likewise.
* config/tc-nds32.c (nds32_elf_analysis_relax_hint): Likewise.
This allocates entries added to the string hash tables on the notes
obstack, so that at least those do not leak. A followup patch will
switch over the str_hash allocation to notes_calloc, which is why I
haven't implemented deleting all the target string hash tables.
* config/obj-coff-seh.c (get_pxdata_name, alloc_pxdata_item): Use
notes obstack for string hash table entries.
* config/tc-alpha.c (get_alpha_reloc_tag, md_begin): Likewise.
* config/tc-h8300.c (md_begin): Likewise.
* config/tc-ia64.c (dot_rot, dot_pred_rel, dot_alias): Likewise.
* config/tc-nds32.c (nds32_relax_hint): Likewise.
* config/tc-riscv.c (riscv_init_csr_hash): Likewise.
* config/tc-score.c (s3_insert_reg): Likewise.
(s3_build_score_ops_hsh, s3_build_dependency_insn_hsh): Likewise.
* config/tc-score7.c (s7_build_score_ops_hsh): Likewise.
(s7_build_dependency_insn_hsh): Likewise.
* config/tc-tic4x.c (tic4x_asg): Likewise.
The arc opcode hash table has entries that have a realloc'd field.
This doesn't lend itself to obstack allocation, so freeing must be
done with a purpose built hashtab del_f.
* config/tc-arc.c (arc_opcode_free): New function.
(md_begin): Pass the above as del_f to htab_create_alloc.
(arc_md_end): New function.
* config/tc-arc.h (arc_md_end): Declare.
(md_end): Define.
This tidies memory used by the two x86 gas string hash tables before
exiting. I'm using a two-pronged approach, firstly the obvious call
to htab_delete plus telling the libiberty/hashtab.c infrastructure to
free tuples generated by str_hash_insert, and secondly putting the x86
core_optab memory on the notes obstack. It would be possible to free
core_optab memory by using a custom hash table del_f on x86, as I do
for arc, but a later patch will move all the string hash memory to the
notes obstack.
* config/tc-i386.c (md_begin): Use notes_alloc for core_optab.
(386_md_end): New function.
* config/tc-i386.h (386_md_end): Declare.
(md_end): Define.
* hash.h (str_htab_create): Pass free as del_f.
Only inline functions should be defined in hash.h, there's no benefit
in having multiple copies of hash_string_tuple and eq_string_tuple.
Also, use the table alloc_f when allocating tuples to be stored, so
that these functions are usable with different memory allocation
strategies.
* hash.h (struct string_tuple, string_tuple_t): Move earlier.
(string_tuple_alloc): Add table param, allocate using table alloc_f.
(str_hash_insert): Adjust to suit. Call table->free_f when
entry is not used.
(hash_string_tuple, eq_string_tuple): Move to..
* hash.c: ..here.
Currently md_end is typically used for some final actions rather than
freeing memory like other *_end functions. Rename it to md_finish,
and rename target implementation. The renaming of target functions
makes it possible to find them all with "grep md_finish",
eg. md_mips_end is renamed to mips_md_finish, not md_mips_finish.
This patch leaves a number of md_end functions unchanged, those that
either do nothing or deallocate memory, and calls them late.
The idea here is that target maintainers implement md_end functions to
tidy memory, if anyone cares. Freeing persistent memory in gas is
not at all important, except that it can hide more important memory
leaks, those that happen once per some frequent gas operation, amongst
these unimportant memory leaks.
* as.c (main): Rename md_end to md_finish.
* config/tc-alpha.c, * config/tc-alpha.h,
* config/tc-arc.c, * config/tc-arc.h,
* config/tc-arm.c, * config/tc-arm.h,
* config/tc-csky.c, * config/tc-csky.h,
* config/tc-ia64.c, * config/tc-ia64.h,
* config/tc-mcore.c, * config/tc-mcore.h,
* config/tc-mips.c, * config/tc-mips.h,
* config/tc-mmix.c, * config/tc-mmix.h,
* config/tc-msp430.c, * config/tc-msp430.h,
* config/tc-nds32.c, * config/tc-nds32.h,
* config/tc-ppc.c, * config/tc-ppc.h,
* config/tc-pru.c, * config/tc-pru.h,
* config/tc-riscv.c, * config/tc-riscv.h,
* config/tc-s390.c, * config/tc-s390.h,
* config/tc-sparc.c, * config/tc-sparc.h,
* config/tc-tic4x.c, * config/tc-tic4x.h,
* config/tc-tic6x.c, * config/tc-tic6x.h,
* config/tc-v850.c, * config/tc-v850.h,
* config/tc-xtensa.c, * config/tc-xtensa.h,
* config/tc-z80.c, * config/tc-z80.h: Similarly.
* output-file.c (output_file_close): Call md_end.
So that the notes obstack can be used for persistent storage in
parse_args.
* as.c (parse_args): Use notes_alloc and notes_strdup.
(free_notes): New function.
(main): Init notes obstack, and arrange to be freed on exit.
* read.c (read_begin): Don't init notes obstack.
(read_end): Free cond_obstack.
* subsegs.c (subsegs_end): Don't free cond_obstack or notes.
itbl_files seems to be debug code. Get rid of it.
* as.c (struct itbl_file_list): Delete.
(itbl_files): Delete.
(parse_args): Don't keep itbl_files list.
Use notes obstack for dwcfi_hash entries, and free table. Freeing the
table makes memory checkers complain more about "definitely lost"
memory as we've moved some from the "still reachable" category.
That will be fixed with a later patch.
* dw2gencfi.c (get_debugseg_name): Allocate on notes obstack.
(alloc_debugseg_item): Likewise.
(dwcfi_hash_find_or_make): Adjust failure path free.
(cfi_finish): Delete dwfci_hash.
Another case of duplicated hash.h code, the only minor difference
being that macro->format_hash was created with 7 entries vs. str_hash
with 16 entries.
* macro.c (macro_init, define_macro): Use str_htab_create.
(do_formals, define_macro, macro_expand_body): Use str_hash_insert
(macro_expand_body): Use str_hash_find and str_hash_delete.
(delete_macro): Likewise.
(sub_actual, macro_expand, check_macro): Use str_hash_find.
(expand_irp): Use str_htab_create and str_hash_insert.
* macro.h (struct macro_struct): Tidy.
(struct macro_hash_entry, macro_hash_entry_t, hash_macro_entry),
(eq_macro_entry, macro_entry_alloc, macro_entry_find),
(struct formal_hash_entry, formal_hash_entry_t),
(hash_formal_entry, eq_formal_entry, formal_entry_alloc),
(formal_entry_find): Delete.
* config/tc-iq2000.c (iq2000_add_macro): Use str_htab_create
and str_hash_insert.
po_hash code duplicates the str_hash code in hash.h for no good reason.
* read.c (struct po_entry, po_entry_t): Delete.
(hash_po_entry, eq_po_entry, po_entry_alloc, po_entry_find): Delete.
(pop_insert): Use str_hash_insert.
(pobegin): Use str_htab_create.
(read_a_source_file, s_macro): Use str_hash_find.
read_symbol_name mallocs the string it returns. Free it when done.
* read.c (read_symbol_name): Free name on error path.
* config/tc-ppc.c (ppc_GNU_visibility): Free name returned from
read_symbol_name.
(ppc_extern, ppc_globl, ppc_weak): Likewise.
This is mostly a tidy with the aim of being able to free
out_file_name, but it does fix a possible attempt to unlink the output
file twice (not that that matters).
* as.h (keep_it): New global.
* as.c (keep_it): Delete.
(close_output_file): Delete, merged into..
* output-file.c (output_file_close): ..here. Delete parameter.
* output-file.h (output_file_close): Update prototype.
