Commit Graph

22 Commits

Author SHA1 Message Date
Andrew Cagney
7fc5b5adca Report SIGBUS and halt simulation when ld/st detect a misaligned address. 2000-02-09 05:08:42 +00:00
Jason Molenda
c3f6f71df3 import gdb-2000-01-05 snapshot 2000-01-06 03:07:20 +00:00
Jason Molenda
4ce44c668d import gdb-1999-11-16 snapshot 1999-11-17 02:31:06 +00:00
Stan Shebs
c906108c21 Initial creation of sourceware repository 1999-04-16 01:35:26 +00:00
Stan Shebs
071ea11e85 Initial creation of sourceware repository 1999-04-16 01:34:07 +00:00
Andrew Cagney
ac9a7d8a2c Implement separate user (SPU) and interrupt (SPI) stack pointers. 1998-02-13 05:22:49 +00:00
Andrew Cagney
19431a0280 Ensure zero-hardwired bits in DPSW remain zero. 1998-02-11 06:34:30 +00:00
Andrew Cagney
38d0ccc27a Fix typo, REP_S was refering to REP_E register.
Add test.
1997-12-08 23:44:11 +00:00
Andrew Cagney
bc6df23d14 For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping
through an exception may not work correctly.
For GDB reads/writes to the control registers, ensure the cpu state is
updated correctly.
1997-12-08 03:22:58 +00:00
Andrew Cagney
7f48c9fe1d Add DM (bit 4) to PSW. See 7-1 for more info.
Test.
1997-12-04 07:01:30 +00:00
Andrew Cagney
aa49c64f3e * d10v_sim.h (SEXT56): Define.
* simops.c (OP_4201): For "rac", sign extend 56 bit value before
it is shifted.
* d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using
SIGNED64 macro.
1997-12-03 08:03:33 +00:00
Michael Meissner
b30cdd3565 Fix -t option to work with memory mapping; Print PC in some error messages 1996-10-30 22:43:02 +00:00
Martin Hunt
c422ecc7a4 Tue Oct 29 12:13:52 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* interp.c (sim_size): Now allocates unified memory for imap segments
	0,1,2, and 127. Initializes imap0 and imap1 to 0x1000.  Initializes dmap to 0.
	(sim_write): Just call xfer_mem().
	(sim_read): Just call xfer_mem().
	(xfer_mem): New function. Does appropriate memory mapping and copies bytes.
	(dmem_addr): New function. Reads dmap register and translates data
 	addresses to local addresses.
	(pc_addr): New function. Reads imap register and computes local address
	corresponding to contents of the PC.
	(sim_resume): Change to use pc_addr().
	(sim_create_inferior): Change reinitialization code. Also reinitializes
	imap[01] and dmap.
	(sim_fetch_register): Add fake registers 32,33,34 for imap0, imap1, and dmap.
	(sim_store_register): Add fake registers 32,33,34 for imap0, imap1, and dmap.

	* simops.c (MEMPTR): Redefine to use dmem_addr().
	(OP_5F00): Replace references to STate.imem with dmem_addr().

	* d10v-sim.h (State): Remove mem_min and mem_max. Add umem[128].
	(RB,SW,RW,SLW,RLW): Redefine to use dmem_addr().
	(IMAP0,IMAP1,DMAP,SET_IMAP,SET_IMAP1,SET_DMAP): Define.
1996-10-29 20:31:08 +00:00
Michael Meissner
aeb1f26ba8 Provide better statistics, particularly for doing VLIW work; Fix ldb to correctly sign extend 1996-10-22 19:49:37 +00:00
Michael Meissner
d6fe5ca568 Make read/write memory functions inlined 1996-10-16 22:16:21 +00:00
Michael Meissner
5c2556697f Make read/write memory functions inlined 1996-10-16 22:14:23 +00:00
Michael Meissner
7eebfc6296 More debug support; Enable -t/-v to work correctly; Add --enable-sim-cflags configure switch 1996-09-04 17:42:51 +00:00
Michael Meissner
87178dbdf7 Enhance debug support 1996-09-04 15:41:43 +00:00
Martin Hunt
d70b4d426b Wed Aug 28 17:33:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* Makefile.in, d10v_sim.h, interp.c: Fix byte-order problems.
1996-08-29 00:35:11 +00:00
Martin Hunt
4f425a3203 Mon Aug 26 18:30:28 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v_sim.h (SEXT32): Added.
	* interp.c: Commented out printfs.
	* simops.c:  Fixed error in sb and st2w.
1996-08-27 01:32:48 +00:00
Martin Hunt
4c38885c86 Fri Aug 2 17:44:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v_sim.h, simops.c: Snapshot
1996-08-03 00:45:58 +00:00
Martin Hunt
2934d1c925 Thu Aug 1 17:05:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* ChangeLog, Makefile.in, configure, configure.in, d10v_sim.h,
	gencode.c, interp.c, simops.c: Created.
1996-08-02 00:23:31 +00:00