gas/write.c provides a fallback TC_VALIDATE_FIX_SUB define that can be
a problem for some targets, the problem being that a non-zero
definition of TC_VALIDATE_FIX_SUB says that some uses of fx_subsy are
OK, in effect that the target will handle fx_subsy in md_apply_fix
and/or tc_gen_reloc. A lot of targets don't have the necessary
md_apply_fix and tc_gen_reloc support. So a safer default is to
disallow fx_subsy by default.
I've had a good look over target usage of fx_subsy, and think I've
caught all the cases where targets need TC_VALIDATE_FIX_SUB. Possible
failures would be limited to alpha, microblaze, ppc and s390 (the
targets that define UNDEFINED_DIFFERENCE_OK), or targets that generate
fixups with BFD_RELOC_GPREL32/16 and use a syntax explicitly showing
a difference expression.
* write.c (TC_VALIDATE_FIX_SUB): Default to 0.
* config/tc-hppa.h (TC_VALIDATE_FIX_SUB): Define.
* config/tc-microblaze.h (TC_VALIDATE_FIX_SUB): Define.
* config/tc-alpha.h (TC_VALIDATE_FIX_SUB): Define for ECOFF.
* config/tc-ppc.h (TC_VALIDATE_FIX_SUB): Don't define for ELF.
Do define for XCOFF.
DWARF sections have special names on AIX which need be handled
by objdump in order to correctly print them.
This patch also adds the correlation in bfd for future uses.
bfd/
* libxcoff.h (struct xcoff_dwsect_name): Add DWARF name.
* coff-rs6000.c (xcoff_dwsect_names): Update.
* coffcode.h (sec_to_styp_flags): Likewise.
(coff_new_section_hook): Likewise.
binutils/
* dwarf.h (struct dwarf_section): Add XCOFF name.
* dwarf.c (struct dwarf_section_display): Update.
* objdump.c (load_debug_section): Add XCOFF name handler.
(dump_dwarf_section): Likewise.
gas/
* config/tc-ppc.c (ppc_change_debug_section): Update to
match new name's field.
Since gcc commit, 3c70b3ca1ef58f302bf8c16d9e7c7bb8626408bf, we now enable
elf attributes for all riscv targets by default in gcc. Therefore, I
think binutils should have the same behavior, in case users are writing
assembly files. If --enable-default-riscv-attribute isn't set, then we
enable the elf attributes for all riscv targets by default.
ChangLog:
binutils/
* testsuite/binutils-all/readelf.s: Add comments for riscv.
* testsuite/binutils-all/readelf.s-64: Likewise.
* testsuite/binutils-all/readelf.s-64-unused: Likewise.
* testsuite/binutils-all/readelf.ss: Likewise.
* testsuite/binutils-all/readelf.ss-64: Likewise.
* testsuite/binutils-all/readelf.ss-64-unused: Likewise.
gas/
* configure.ac: If --enable-default-riscv-attribute isn't set,
then we enable the elf attributes for all riscv targets by
default.
* configure: Regenerated.
Some extern declarations differ in constnes to their definitions too.
Let's make sure this sort of thing doesn't happen again, but putting
the externs in a header where they belong.
gas/
* config/tc-nds32.c (nds32_keyword_gpr): Don't declare.
(md_begin): Constify k.
opcodes/
* nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
(nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
(nds32_field_table, nds32_opcode_table, nds32_keyword_table),
(nds32_opcodes, nds32_operand_fields, nds32_keywords),
(nds32_keyword_gpr): Move declarations to..
* nds32-asm.h: ..here, constifying to match definitions.
This is exporting the variable "opcodes" as a large writable blob.
This is not a namespace friendly name, so add a "microblaze" prefix,
and then sprinkle const over its definition & use.
Power10 prefixed instructions must not cross 64-byte boundaries.
This is already handled.
However, on XCOFF, the csect must be updated to match the new
alignment.
* config/tc-ppc.c (md_assemble): Update ppc_current_csect
alignment when finding prefixed instructions.
Commit 54758c3e39 made changes to the picojava support based on
https://sourceware.org/pipermail/binutils/2005-November/045136.html
An update from picojava to picojava II, I think. Unfortunately the
patch neglected any changes to the gas testsuite, resulting in
"FAIL: pj" since that date. This patch makes a few relatively simple
changes to cure the regression.
gas/
* config/tc-pj.c (md_apply_fix): Apply PJ_CODE_REL32 relocs.
* testsuite/gas/pj/ops.s: Update jsr, ret, getstatic,
putstatic, getfield, putfield, invokevirtual, invokespecial,
invokestatic, invokeinterface, goto_w, jsr_w assembly. Delete
version 1 picojava opcodes.
* testsuite/gas/pj/ops.d: Match expected output.
opcodes/
* pj-dis.c (print_insn_pj): Don't print trailing tab. Do
print separator for pcrel insns.
A shift count exceeding the size of the value is undefined behaviour,
and so is negating a signed LONG_MIN.
* config/tc-z80.c (signed_overflow, unsigned_overflow): Avoid UB.
The test contained an expression that can't be evaluated unless
expressions are 64-bit.
* testsuite/gas/ppc/raw.s: Use 0 as pli constant.
* testsuite/gas/ppc/raw.d: Update to suit.
When the same such construct is used multiple times in a source file,
there's still no need to emit a separate symbol each time. Under the
assumption that there won't be many of these, use a simple array
lookup method to record previously used symbols.
PR 27904
* config/tc-aarch64.c (ldst_lo12_determine_real_reloc_type):
Generate a syntax error message if the reloc qualifier does not
match the instruction's size.
Latest gcc versions are now generating csects instead of .lcomm
for bss symbols.
Some adjustements are needed in order to handle them.
* config/tc-ppc.c (md_begin): Create bss section with dummy
symbol.
(ppc_frob_symbol): Output XTY_CM for bss csects.
(ppc_fix_adjustable): Adjust condition to avoid bss csects.
AIX ld expects the section contents for relocations BFD_RELOC_PPC_TLSM
or BFD_RELOC_PPC64_TLSM to be zero.
Actually, it seems to be the case for all the TLS relocations
generated by AIX assembly but only these two are mandatory.
* config/tc-ppc.c (md_apply_fix): Adjust addend to nullify
section contents for BFD_RELOC_PPC_TLSM or
BFD_RELOC_PPC64_TLSM.
* testsuite/gas/ppc/xcoff-tlsm-32.d: New test.
* testsuite/gas/ppc/xcoff-tlsm-64.d: New test.
* testsuite/gas/ppc/xcoff-tlsm.s: New test.
* testsuite/gas/ppc/aix.exp: Run new tests.
Unlike for .dc.? the parsing here failed to skip the colon before
calling hex_float(). To avoid both variants of parsing going out of sync
again, introduce a helper used by both.
While the logic in fixup_segment() so far was off by 1 for fixups
dealing with quantities without known signedness, thus failing to report
an overflow when e.g. a byte-sized resulting value is -0x100, the logic
in emit_expr_with_reloc() reported an overflow even on large negative
values when the respective positive ones would not be warned
about, and when fixup_segment() wouldn't do so either. Such diagnostics
all ought to follow a similar pattern of what value range is acceptable.
(If expressions' X_unsigned was reliably set, emit_expr_with_reloc()'s
checking might make sense to tighten based on that flag.)
Note that with commit 80aab57939 ("Changes to let cons handle bignums
like general expressions") having added handling of nbytes >
sizeof(valueT) in the O_constant case, converting to O_big, the setting
to zero of "hibit" had become dead. With "hibit" no longer used, this
code now gets dropped altogether. But additionally a respective know()
gets inserted.
The testsuite uses the output to determine whether BFD64 is in effect.
--x32 is supported for ELF only; don't advertise it for PE/COFF. --64 is
also supported for Mach-O; advertise it. Adjust the testsuite's BFD64
check accordingly.
Also replace "code" by "object", since it's the object format that the
options primarily control. It's also _initial_ code bitness, but this
can be changed by directives.
First of all eliminate the disp{16,32,32s} static variables, which are
used solely for setting a temporary variable in build_modrm_byte(). The
effect there can be had without use of such a temporary and without
operand_type_or(), by just setting the single bit each that needs
setting.
Then use operand_type_and_not(..., anydisp) when all dispNN bits want
clearing together.
Applying a mask with all bits set (or its inverse, with hence all bits
clear) won't alter the result (or won't trigger the warning). Re-arrange
the code to eliminate two more of the somewhat odd (2 << width_minus_1)
constructs.
Certain disp values may trigger "... shortened to ..." warnings when
equivalent imm ones don't. In some of the cases there are also
differences (for non-64-bit code) between BFD64 and !BFD64 builds. The
resulting encodings (i.e. use [or not] of the shorter disp8 / imm8
forms) are also different in some cases. Make this handling consistent.
Note that using equivalent 16-bit mode displacements / immediates
continues to expose entirely different behavior (see the disp-imm-16
testcase added by an earlier patch). This may want to be the subject of
further changes, but it'll then quickly become obvious that e.g. keying
use of extend_to_32bit_address() to non-64-bit mode isn't appropriate
either: Once we allow wrapping operands, we would better do so
consistently, in which case all of this would need to become dependent
upon address or operand size instead of mode.
In case there is something which gets shortened (perhaps only on a BFD64
build targeting a 32-bit binary), seeing the full original value is
often helpful to understand what's actually going wrong. Of course for
non-64-bit binaries we better wouldn't be seeing such warnings at all,
as they're often indicative of a behavioral difference between BFD64 and
!BFD64 builds.
Prior to "gas: drop sprint_value()", which introduced the use of
bfd_sprintf_vma(), the output had other shortcomings.
Just like e.g. 0x10000 triggers a warning for size 2, -0x10000 ought to
as well.
Note that some of the encodings produced aren't ones one would expect,
and hence the generated code is not being checked for in the new
testcases.
The description of e68c3d59ac ("x86: better respect quotes in
parse_operands()") wrongly states:
"In i386_att_operand(), which needs adjustment to remain in sync, besides
respecting double quotes now, also change the logic such that we don't
count parentheses anymore: Finding any opening or closing parenthesis or
any double quote means we're done, because the subsequent parsing code
wouldn't accept (extra) instances of these anyway."
I didn't pay attention to the possibility of the scale factor being
specified as an expression, which may contain parentheses. Thanks to
Martin for pointing this out. Restore prior behavior or matching
parentheses (backwards), while giving the variable a more suitable name.
Note that this simple and immediate fix is not ging to be enough: This
expression could itself involve quoted symbols. However, to address this
backwards parsing needs to be done away with altogether here (such that
parentheses which are part of such a quoted symbol name can also
properly be accounted for), which is going to be a more intrusive
change.
I've been repeatedly confused by, in particular, the .dc.a potable[]
entry being conditional. Grepping in gas/config/ reveals only very few
targets actually #define-ing it. But as of 7be1c4891a the symbol is
always defined, so #ifdef-s are pointless (and, as said, potentially
confusing).
Also adjust documentation to reflect this.
Always define TC_PARSE_CONS_EXPRESSION to properly wrap constants for
all x86 targets.
* config/tc-i386.c (x86_cons): Handle GOT/PLT relocations only
if needed.
* config/tc-i386.h (TC_PARSE_CONS_EXPRESSION): Always define.
We also need to update the riscv_opts.[rvc|rve] for elf attributes.
Otherwise, the following case will fail,
$ cat cadd.s
.attribute arch, "rv64gc"
c.add a0, a1
$ riscv64-unknown-elf-as cadd.s -o cadd.o
cadd.s: Assembler messages:
cadd.s:2: Error: illegal operands `c.add a0,a1
After applying this patch,
$ riscv64-unknown-elf-as cadd.s -o cadd.o
$ riscv64-unknown-elf-objdump -d cadd.o
cadd.o: file format elf64-littleriscv
Disassembly of section .text:
0000000000000000 <.text>:
0: 952e add a0,a0,a1
...
gas/
* config/tc-riscv.c (riscv_set_arch): Call riscv_set_rvc
and riscv_set_rve both for -march and elf attributes.
(riscv_after_parse_args): Likewise.
Despite the comment ahead of the enum explicitly pointing out the need
to also update the corresponding array, 1b8833198c ("Add support for
MVE instructions: vcmp and vpt") failed to do so. Oddly enough the issue
appears to be spotted only by rather old gcc (4.3-ish in my case).
In 16-bit mode a 16-bit address size LEA with a 16-bit displacement and
a 32-bit destination is shorter to encode than the corresponding MOV.
Commit fe134c6569 ("x86: optimize LEA")'s promise was to only do the
transformation when the encoding size wouldn't grow, i.e. it did go a
little too far. Restrict this specific case of the transformation to
-O2.
Follow the pattern found elsewhere when relocations are involved. For
wrap32-data also drop a mistakenly left "ELF" from the test name. (Note
that Darwin, for which the wrap32 tests are also failing, is left as-is,
for there being numerous other failures already anyway, and it hence
being questionable whether that target is actually properly maintained.)
With optimize_disp() adjusting i.types[].bitfield.disp after adjusting
the value to be used as displacement, it better also stores the updated
value, to avoid subsequent "... shortened to ..." warnings. Note how
optimize_imm() already does so.
The -0xffffffff tests being added expose a separate issue: The encoding
chosen should be 1 for ModR/M.mod, not 2. This will want to be taken
care of, but not right here.
This at the same time addresses a similar warning and demonstrates a
similar encoding issue with 16-bit addressing. Since it was omitted
when introducing the lea16-optimize test, add a plain lea16 one to also
cover this.
- Do the zero checking first - there's no point in doing anything else
in this case.
- Drop two pointless & where just before it was checked that the
respective bits are clear already anyway.
When AVX512 support was added, symbol quotation was not paid attention
to. Just like the (base,index,scale) specifier gets parsed from the end
of the expression, the {...} also wants parsing from the end; in no case
is the first { found a guarantee of a masking or broadcasting specifier.
When d02603dc20 ("Allow symbol and label names to be enclosed in
double quotes") added the check for a double quote to the loop body
there, it didn't go quite far enough: Parentheses inside quotes
shouldn't be counted, and character restrictions also shouldn't apply
inside quoted regions.
In i386_att_operand(), which needs adjustment to remain in sync, besides
respecting double quotes now, also change the logic such that we don't
count parentheses anymore: Finding any opening or closing parenthesis or
any double quote means we're done, because the subsequent parsing code
wouldn't accept (extra) instances of these anyway.
Note that in parse_operands() this mimics get_symbol_name()'s
questionable behavior of treating \ specially only when ahead of ". (The
behavior is suspicious because the meaning of \\ then is ambiguous. It
is in particular impossible to have a (quoted) symbol name end in a
single \.) I would have used get_symbol_name() here, if that didn't
require fiddling with input_line_pointer.
So far only - was permitted, but +, !, and ~ ought to be treated the
same.
Rather than adding them to digit_chars[], which was at least odd to have
held - so far, drop this array and its wrapper macro for being used just
once.
While adjusting this logic, also include [ in the characters which may
start a displacement expression - gas generally treats [] as equivalent
to ().
When d02603dc20 ("Allow symbol and label names to be enclosed in
double quotes") added the check for a leading double quote to
i386_att_operand(), it missed a second similar check after having found
a segment override. To avoid the two checks going out of sync again,
introduce an inline helper.
This needs to happen before checking of what may legitimately start a
memory operand (like is done when there's no segment override). Plus a
second '*' shouldn't be permitted when one was already found before the
segment override.
While subsequent processing in AT&T mode relies on this simplistic early
checking, Intel mode hasn't been for quite a long time (or perhaps never
really did).
Neither masking nor broadcast are possible here, and RC/SAE get dealt
with elsewhere.
This also fixes gas crashes (i.e. "Fatal error: unable to continue with
assembly"), since the return path being removed failed to restore
input_line_pointer from save_input_line_pointer.
Non-64-bit code should get handled the same with or without BFD64. This
wasn't the case though in a number of situations (and quite likely there
are more that I haven't spotted yet).
It's not very nice to tie the check in md_apply_fix() to object_64bit,
but afaict at that time we have no record anymore of the mode an insn
was assembled in (it might also have been data). This doesn't look to be
the first inconsistency of this kind, though. In x86_cons() it's even
less clear what the right approach would be: flag_code shouldn't matter
for data emission, but instead we'd need to know from which mode(s) the
data actually gets accessed. On this basis, signed_cons() also gets
adjusted.
Fixes a 16 year old bug report, which even came with a patch.
opcodes/
PR 1202
* mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
Use unsigned int for inst.
gas/
PR 1202
* testsuite/gas/mcore/allinsn.d: Correct loopt expected output.
opcodes/
* ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
Don't special case PPC_OPCODE_RAW.
(lookup_prefix): Likewise.
(lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
(print_insn_powerpc): ..update caller.
* ppc-opc.c (EXT): Define.
(powerpc_opcodes): Mark extended mnemonics with EXT.
(prefix_opcodes, vle_opcodes): Likewise.
(XISEL, XISEL_MASK): Add cr field and simplify.
(powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
all isel variants to where the base mnemonic belongs. Sort dstt,
dststt and dssall.
gas/
* testsuite/gas/ppc/raw.s,
* testsuite/gas/ppc/raw.d: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Add tests for the generic C0, C1, C2, C3 coprocessor instructions.
gas/
* testsuite/gas/mips/c0.d: New test.
* testsuite/gas/mips/mips1@c0.d: New test.
* testsuite/gas/mips/mips2@c0.d: New test.
* testsuite/gas/mips/mips3@c0.d: New test.
* testsuite/gas/mips/mips4@c0.d: New test.
* testsuite/gas/mips/mips5@c0.d: New test.
* testsuite/gas/mips/mips32@c0.d: New test.
* testsuite/gas/mips/mips64@c0.d: New test.
* testsuite/gas/mips/r3000@c0.d: New test.
* testsuite/gas/mips/r3900@c0.d: New test.
* testsuite/gas/mips/r4000@c0.d: New test.
* testsuite/gas/mips/vr5400@c0.d: New test.
* testsuite/gas/mips/r5900@c0.d: New test.
* testsuite/gas/mips/sb1@c0.d: New test.
* testsuite/gas/mips/interaptiv-mr2@c0.d: New test.
* testsuite/gas/mips/octeon@c0.d: New test.
* testsuite/gas/mips/xlr@c0.d: New test.
* testsuite/gas/mips/c1.d: New test.
* testsuite/gas/mips/mips1@c1.d: New test.
* testsuite/gas/mips/mips2@c1.d: New test.
* testsuite/gas/mips/mips3@c1.d: New test.
* testsuite/gas/mips/mips4@c1.d: New test.
* testsuite/gas/mips/mips5@c1.d: New test.
* testsuite/gas/mips/mips32@c1.d: New test.
* testsuite/gas/mips/mips64@c1.d: New test.
* testsuite/gas/mips/mipsr6@c1.d: New test.
* testsuite/gas/mips/r3000@c1.d: New test.
* testsuite/gas/mips/r3900@c1.d: New test.
* testsuite/gas/mips/r4000@c1.d: New test.
* testsuite/gas/mips/vr5400@c1.d: New test.
* testsuite/gas/mips/r5900@c1.d: New test.
* testsuite/gas/mips/sb1@c1.d: New test.
* testsuite/gas/mips/interaptiv-mr2@c1.d: New test.
* testsuite/gas/mips/octeon@c1.d: New test.
* testsuite/gas/mips/xlr@c1.d: New test.
* testsuite/gas/mips/c2.d: New test.
* testsuite/gas/mips/vr5400@c2.d: New test.
* testsuite/gas/mips/r5900@c2.d: New test.
* testsuite/gas/mips/octeon@c2.d: New test.
* testsuite/gas/mips/c3.d: New test.
* testsuite/gas/mips/mips1@c3.d: New test.
* testsuite/gas/mips/mips2@c3.d: New test.
* testsuite/gas/mips/mips32@c3.d: New test.
* testsuite/gas/mips/r3000@c3.d: New test.
* testsuite/gas/mips/r3900@c3.d: New test.
* testsuite/gas/mips/c0.l: New test stderr output.
* testsuite/gas/mips/c2.l: New test stderr output.
* testsuite/gas/mips/c3.l: New test stderr output.
* testsuite/gas/mips/c0.s: New test source.
* testsuite/gas/mips/c1.s: New test source.
* testsuite/gas/mips/c2.s: New test source.
* testsuite/gas/mips/c3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Verify that the RFE instruction is not only accepted where supported,
but rejected where it is not as well.
gas/
* testsuite/gas/mips/mips.exp: Run RFE test across all ISAs.
* testsuite/gas/mips/rfe.d: Update for ISA exclusions.
* testsuite/gas/mips/mips1@rfe.d: New test.
* testsuite/gas/mips/mips2@rfe.d: New test.
* testsuite/gas/mips/r3000@rfe.d: New test.
* testsuite/gas/mips/r3900@rfe.d: New test.
* testsuite/gas/mips/rfe.l: New test stderr output.
Verify that individual coprocessor instructions are not only accepted
where supported, but rejected where they are not as well.
gas/
* testsuite/gas/mips/mips.exp: Run coprocessor tests across all
ISAs.
* testsuite/gas/mips/cp0b.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0bl.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0c.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0m.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3b.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3bl.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3m.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3d.d: Update for ISA exclusions.
* testsuite/gas/mips/mips1@cp0b.d: New test.
* testsuite/gas/mips/mips2@cp0b.d: New test.
* testsuite/gas/mips/mips3@cp0b.d: New test.
* testsuite/gas/mips/r3000@cp0b.d: New test.
* testsuite/gas/mips/r3900@cp0b.d: New test.
* testsuite/gas/mips/r4000@cp0b.d: New test.
* testsuite/gas/mips/r5900@cp0b.d: New test.
* testsuite/gas/mips/mips2@cp0bl.d: New test.
* testsuite/gas/mips/mips3@cp0bl.d: New test.
* testsuite/gas/mips/r3900@cp0bl.d: New test.
* testsuite/gas/mips/r4000@cp0bl.d: New test.
* testsuite/gas/mips/r5900@cp0bl.d: New test.
* testsuite/gas/mips/mips1@cp0c.d: New test.
* testsuite/gas/mips/mips2@cp0c.d: New test.
* testsuite/gas/mips/mips3@cp0c.d: New test.
* testsuite/gas/mips/mips4@cp0c.d: New test.
* testsuite/gas/mips/mips5@cp0c.d: New test.
* testsuite/gas/mips/r3000@cp0c.d: New test.
* testsuite/gas/mips/r3900@cp0c.d: New test.
* testsuite/gas/mips/r4000@cp0c.d: New test.
* testsuite/gas/mips/vr5400@cp0c.d: New test.
* testsuite/gas/mips/r5900@cp0c.d: New test.
* testsuite/gas/mips/mips1@cp0m.d: New test.
* testsuite/gas/mips/r3000@cp0m.d: New test.
* testsuite/gas/mips/octeon@cp2.d: New test.
* testsuite/gas/mips/mipsr6@cp2b.d: New test.
* testsuite/gas/mips/vr5400@cp2b.d: New test.
* testsuite/gas/mips/octeon@cp2b.d: New test.
* testsuite/gas/mips/mips1@cp2bl.d: New test.
* testsuite/gas/mips/mipsr6@cp2bl.d: New test.
* testsuite/gas/mips/r3000@cp2bl.d: New test.
* testsuite/gas/mips/vr5400@cp2bl.d: New test.
* testsuite/gas/mips/octeon@cp2bl.d: New test.
* testsuite/gas/mips/vr5400@cp2m.d: New test.
* testsuite/gas/mips/r5900@cp2m.d: New test.
* testsuite/gas/mips/octeon@cp2m.d: New test.
* testsuite/gas/mips/mips1@cp2d.d: New test.
* testsuite/gas/mips/r3000@cp2d.d: New test.
* testsuite/gas/mips/r3900@cp2d.d: New test.
* testsuite/gas/mips/vr5400@cp2d.d: New test.
* testsuite/gas/mips/r5900@cp2d.d: New test.
* testsuite/gas/mips/octeon@cp2d.d: New test.
* testsuite/gas/mips/mips1@cp2-64.d: New test.
* testsuite/gas/mips/mips2@cp2-64.d: New test.
* testsuite/gas/mips/mips32@cp2-64.d: New test.
* testsuite/gas/mips/mips32r2@cp2-64.d: New test.
* testsuite/gas/mips/mips32r3@cp2-64.d: New test.
* testsuite/gas/mips/mips32r5@cp2-64.d: New test.
* testsuite/gas/mips/mips32r6@cp2-64.d: New test.
* testsuite/gas/mips/r3000@cp2-64.d: New test.
* testsuite/gas/mips/r3900@cp2-64.d: New test.
* testsuite/gas/mips/interaptiv-mr2@cp2-64.d: New test.
* testsuite/gas/mips/mips1@cp3.d: New test.
* testsuite/gas/mips/mips2@cp3.d: New test.
* testsuite/gas/mips/mips32@cp3.d: New test.
* testsuite/gas/mips/r3000@cp3.d: New test.
* testsuite/gas/mips/r3900@cp3.d: New test.
* testsuite/gas/mips/mips1@cp3b.d: New test.
* testsuite/gas/mips/mips2@cp3b.d: New test.
* testsuite/gas/mips/mips32@cp3b.d: New test.
* testsuite/gas/mips/r3000@cp3b.d: New test.
* testsuite/gas/mips/r3900@cp3b.d: New test.
* testsuite/gas/mips/mips2@cp3bl.d: New test.
* testsuite/gas/mips/mips32@cp3bl.d: New test.
* testsuite/gas/mips/r3900@cp3bl.d: New test.
* testsuite/gas/mips/mips1@cp3m.d: New test.
* testsuite/gas/mips/mips2@cp3m.d: New test.
* testsuite/gas/mips/r3000@cp3m.d: New test.
* testsuite/gas/mips/r3900@cp3m.d: New test.
* testsuite/gas/mips/mips2@cp3d.d: New test.
* testsuite/gas/mips/cp0b.l: New test stderr output.
* testsuite/gas/mips/cp0bl.l: New test stderr output.
* testsuite/gas/mips/cp0c.l: New test stderr output.
* testsuite/gas/mips/cp0m.l: New test stderr output.
* testsuite/gas/mips/cp2.l: New test stderr output.
* testsuite/gas/mips/cp2-64.l: New test stderr output.
* testsuite/gas/mips/cp2b.l: New test stderr output.
* testsuite/gas/mips/cp2bl.l: New test stderr output.
* testsuite/gas/mips/cp2m.l: New test stderr output.
* testsuite/gas/mips/cp2d.l: New test stderr output.
* testsuite/gas/mips/cp3.l: New test stderr output.
* testsuite/gas/mips/cp3b.l: New test stderr output.
* testsuite/gas/mips/cp3bl.l: New test stderr output.
* testsuite/gas/mips/cp3m.l: New test stderr output.
* testsuite/gas/mips/cp3d.l: New test stderr output.
Adjust opcode table entries for coprocessor instructions that have been
removed from certain ISA levels or CPU implementations as follows:
- remove CP0 memory access instructions from MIPS II up as the LWC0 and
SWC0 opcodes have been reused for the LL and SC instructions
respectively[1]; strictly speaking LWC0 and SWC0 have never really
been defined in the first place[2], but let's keep them for now in
case an odd implementation did,
- remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as
they have been removed as from those ISAs,
- remove CP0 control register move instructions from MIPS32 up, as they
have been removed as from that ISA[5],
- remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it
has been removed as from those ISAs in favour to ERET,
- remove CP2 instructions from Vr5400 CPUs as their encodings have been
reused for the multimedia instruction set extensions[8] and no CP2
registers exist[9],
- remove CP3 memory access instructions from MIPS III up as coprocessor
3 has been removed as from that ISA[10][11] and from MIPS32 up as the
LWC3 opcode has been reused for the PREF instruction and consequently
all the four memory access instructions removed from the ISA (though
the COP3 opcode has been retained)[12].
Update the testsuite accordingly.
References:
[1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding
- MIPS II Architecture", p. A-178
[2] same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12
[3] "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS
Technologies, Inc., January 29, 1997, Section 14.25 "CP0
Instructions", Subsection "Branch on Coprocessor 0", p. 285
[4] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number:
MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0
Encoding of rs Field", p. 242
[5] same
[6] Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second
Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000
Opcode Bit Encoding", p. A-182
[8] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1",
NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
Section 1.2.3 "CPU Instruction Set Overview", p. 9
[9] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2",
NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
Section 19.2 "Multimedia Instruction Format", p. 681
[10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 -
COP3 and CP3 load/store", p. A-176
[11] same, Table A-39 "CPU Instruction Encoding - MIPS III
Architecture", p. A-179
[12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number:
MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding
of the Opcode Field", p. 241
opcodes/
* mips-opc.c (mips_builtin_opcodes): Update exclusion list for
"ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
"swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
"bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
"bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
"mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
"cop2", and "cop3" entries.
gas/
* testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3
instruction removal.
* testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.
Cover basic CP0, CP2, CP3 branch and branch-likely instructions across
the relevant ISA levels. Omit CP1 branches, covered elsewhere.
gas/
* testsuite/gas/mips/cp0b.d: New test.
* testsuite/gas/mips/cp0bl.d: New test.
* testsuite/gas/mips/cp2b.d: New test.
* testsuite/gas/mips/micromips@cp2b.d: New test.
* testsuite/gas/mips/cp2bl.d: New test.
* testsuite/gas/mips/micromips@cp2bl.d: New test.
* testsuite/gas/mips/cp3b.d: New test.
* testsuite/gas/mips/cp3bl.d: New test.
* testsuite/gas/mips/cp0b.s: New test source.
* testsuite/gas/mips/cp0bl.s: New test source.
* testsuite/gas/mips/cp2b.s: New test source.
* testsuite/gas/mips/cp2bl.s: New test source.
* testsuite/gas/mips/cp3b.s: New test source.
* testsuite/gas/mips/cp3bl.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Fix a commit b015e599c7 ("[MIPS] Add new virtualization instructions"),
<https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression
and bring the disassembly of the RFE instruction back for the relevant
ISA levels.
It is because the "rfe" opcode table entry was incorrectly moved behind
the catch-all generic "c0" entry for CP0 instructions, causing output
like:
00: 42000010 c0 0x10
to be produced rather than:
00: 42000010 rfe
even for ISA levels that do include the RFE instruction.
Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a
suitable test case.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
of "c0".
gas/
* testsuite/gas/mips/rfe.d: New test.
* testsuite/gas/mips/rfe.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
The two CP1 control registers defined by legacy ISAs used to be referred
to by various names, such as FCR0, FCR31, FSR, however their documented
full names have always been the Implementation and Revision, and Control
and Status respectively, so the FIR and FCSR acronyms coming from modern
ISA revisions will be just as unambiguous while improving the clarity of
disassembly. Do not update the TX39 though as it did not have an FPU.
opcodes/
* mips-dis.c (mips_cp1_names_mips): New variable.
(mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
"r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
"r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
"r12000", "r14000", "r16000", "mips5", "loongson2e", and
"loongson2f".
gas/
* testsuite/gas/mips/cp1-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
* testsuite/gas/mips/branch-misc-3.d: Update disassembly
according to changes to opcodes.
* testsuite/gas/mips/cp1-names-r3000.d: Likewise.
* testsuite/gas/mips/cp1-names-r4000.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips1.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips2.d: Likewise.
* testsuite/gas/mips/trunc.d: Likewise.
Cover basic CP0, CP2, CP3 move, load and store instructions across the
relevant ISA levels. Omit CP0 move and CP1 instructions as they are
covered elsewhere.
gas/
* testsuite/gas/mips/cp0c.d: New test.
* testsuite/gas/mips/cp0m.d: New test.
* testsuite/gas/mips/r3900@cp0m.d: New test.
* testsuite/gas/mips/cp2.d: New test.
* testsuite/gas/mips/micromips@cp2.d: New test.
* testsuite/gas/mips/cp2m.d: New test.
* testsuite/gas/mips/mipsr6@cp2m.d: New test.
* testsuite/gas/mips/micromips@cp2m.d: New test.
* testsuite/gas/mips/cp2d.d: New test.
* testsuite/gas/mips/mipsr6@cp2d.d: New test.
* testsuite/gas/mips/micromips@cp2d.d: New test.
* testsuite/gas/mips/cp2-64.d: New test.
* testsuite/gas/mips/micromips@cp2-64.d: New test.
* testsuite/gas/mips/cp3.d: New test.
* testsuite/gas/mips/cp3m.d: New test.
* testsuite/gas/mips/cp3d.d: New test.
* testsuite/gas/mips/cp0c.s: New test source.
* testsuite/gas/mips/cp0m.s: New test source.
* testsuite/gas/mips/cp2.s: New test source.
* testsuite/gas/mips/cp2m.s: New test source.
* testsuite/gas/mips/cp2d.s: New test source.
* testsuite/gas/mips/cp2-64.s: New test source.
* testsuite/gas/mips/cp3.s: New test source.
* testsuite/gas/mips/cp3m.s: New test source.
* testsuite/gas/mips/cp3d.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
The CP0 control register set has never been defined, however encodings
for the CFC0 and CTC0 instructions remained available for implementers
up until the MIPS32 ISA declared them invalid and causing the Reserved
Instruction exception[1]. Therefore we handle them for both assembly
and disassembly, however in the latter case the names of CP0 registers
from the regular set are incorrectly printed if named registers are
requested. This is because we do not define separate operand classes
for coprocessor regular and control registers respectively, which means
the disassembler has no way to tell the two cases apart. Consequently
nonsensical disassembly is produced like:
cfc0 v0,c0_random
Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0
instructions[2] although it failed to document them in the relevant
opcode table until MIPSr6 only.
Correct the issue then by defining a new register class, OP_REG_CONTROL,
and corresponding operand codes, `g' and `y' for the two positions in
the machine instruction a control register operand can take. Adjust the
test cases affected accordingly.
While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries
with each other so that they come in the alphabetical order.
References:
[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of
rs Field", p. 242
[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of
Instructions", pp. 195, 216
include/
* opcode/mips.h: Document `g' and `y' operand codes.
(mips_reg_operand_type): Add OP_REG_CONTROL enumeration
constant.
gas/
* tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G'
operand code.
opcodes/
* mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
handling code over to...
<OP_REG_CONTROL>: ... this new case.
* mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
(mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
"cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
replacing the `G' operand code with `g'. Update "cftc1" and
"cftc2" entries replacing the `E' operand code with `y'.
* micromips-opc.c (decode_micromips_operand) <'g'>: New case.
(micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
entries replacing the `G' operand code with `g'.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0
operand disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
The TX39 core has its distinct set of CP0 registers[1], so it needs a
separate table to hold their names. Add a test case accordingly.
References:
[1] "32-Bit RISC Microprocessor TX39 Family Core Architecture User's
Manual", Toshiba, Jul. 27, 1995, Section 2.2.2 "System control
coprocessor (CP0) registers", pp. 9-10
opcodes/
* mips-dis.c (mips_cp0_names_r3900): New variable.
(mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
for "r3900".
gas/
* testsuite/gas/mips/cp0-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run it.
The DMTC1 instruction operates on a floating-point general register as
its second operand, however in the disassembly of the microMIPS encoding
a floating-point control register is shown instead. This is due to an
incorrect ordering of the two "dmtc1" entries in the opcode table, which
gives precedence to one using the `G' aka coprocessor format over one
using the `S' or floating-point register format.
The coprocessor format, or OP_REG_COPRO, is used so that GAS supports
referring to FPRs by their numbers in assembly, such as $0, $1, etc.
however in the case of CP1/FPU it is also used by the disassembler to
decode those numbers to the names of corresponding control registers.
This in turn causes nonsensical disassembly such as:
dmtc1 a1,c1_fir
in a reference to $f0. It has been like this ever since microMIPS ISA
support has been added.
Correct the ordering of the two entries then by swapping them with each
other, making disassembly output consistent with the regular MIPS DMTC1
instruction as well all the remaining CP1 move instructions. Adjust all
the test cases affected accordingly.
opcodes/
* micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
entries with each other.
gas/
* testsuite/gas/mips/micromips.d: Update disassembly according
to "dmtc1" entry fix with opcodes.
* testsuite/gas/mips/micromips-compact.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips@isa-override-1.d: Likewise.
Fix an issue caused by commit f9419b056f ("MIPS gas: code cleanup"),
<https://sourceware.org/ml/binutils/2002-05/msg00192.html>, and replace
the incorrect use of RA with the CFC1 and CTC1 instructions with FCSR.
While the register referred by its number is $31 in both cases, these
instructions operate on the floating-point control register file rather
than general-purpose registers.
gas/
* config/tc-mips.c (FCSR): New macro.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use it in place of RA.
commit a7664973b2
Author: Jan Beulich <jbeulich@suse.com>
Date: Mon Apr 26 10:41:35 2021 +0200
x86: correct overflow checking for 16-bit PC-relative relocs
caused linker failure when building 16-bit program in a 32-bit ELF
container. Update GNU_PROPERTY_X86_FEATURE_2_USED with
#define GNU_PROPERTY_X86_FEATURE_2_CODE16 (1U << 12)
to indicate that 16-bit mode instructions are used in the input object:
https://groups.google.com/g/x86-64-abi/c/UvvXWeHIGMA
to indicate that 16-bit mode instructions are used in the object to
allow linker to properly perform relocation overflow check for 16-bit
PC-relative relocations in 16-bit mode instructions.
1. Update x86 assembler to always generate the GNU property note with
GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object.
2. Update i386 and x86-64 linkers to use 16-bit PC16 relocations if
input object is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16.
bfd/
PR ld/27905
* elf32-i386.c: Include "libiberty.h".
(elf_howto_table): Add 16-bit R_386_PC16 entry.
(elf_i386_rtype_to_howto): Add a BFD argument. Use 16-bit
R_386_PC16 if input has 16-bit mode instructions.
(elf_i386_info_to_howto_rel): Update elf_i386_rtype_to_howto
call.
(elf_i386_tls_transition): Likewise.
(elf_i386_relocate_section): Likewise.
* elf64-x86-64.c (x86_64_elf_howto_table): Add 16-bit
R_X86_64_PC16 entry.
(elf_x86_64_rtype_to_howto): Use 16-bit R_X86_64_PC16 if input
has 16-bit mode instructions.
* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Set
elf_x86_has_code16 if relocatable input is marked with
GNU_PROPERTY_X86_FEATURE_2_CODE16.
* elfxx-x86.h (elf_x86_obj_tdata): Add has_code16.
(elf_x86_has_code16): New.
binutils/
PR ld/27905
* readelf.c (decode_x86_feature_2): Support
GNU_PROPERTY_X86_FEATURE_2_CODE16.
gas/
PR ld/27905
* config/tc-i386.c (set_code_flag): Update x86_feature_2_used
with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF
object.
(set_16bit_gcc_code_flag): Likewise.
(x86_cleanup): Always generate the GNU property note if
x86_feature_2_used isn't 0.
* testsuite/gas/i386/code16-2.d: New file.
* testsuite/gas/i386/code16-2.s: Likewise.
* testsuite/gas/i386/x86-64-code16-2.d: Likewise.
* testsuite/gas/i386/i386.exp: Run code16-2 and x86-64-code16-2.
include/
PR ld/27905
* elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): New.
ld/
PR ld/27905
* testsuite/ld-i386/code16.d: New file.
* testsuite/ld-i386/code16.t: Likewise.
* testsuite/ld-x86-64/code16.d: Likewise.
* testsuite/ld-x86-64/code16.t: Likewise.
* testsuite/ld-i386/i386.exp: Run code16.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
Since the policies of GNU and llvm toolchain are different for now,
current binutils mainline cannot accept any draft extensions, including
rvv, zfh, .... The Clang/LLVM allows these draft stuff on mainline,
but the GNU ld might be used with them, so this causes the link time
problems.
The patch allows ld to link the objects with unknown prefixed extensions,
which are probably generated by LLVM or customized toolchains.
bfd/
* elfxx-riscv.h (check_unknown_prefixed_ext): New bool.
* elfxx-riscv.c (riscv_parse_prefixed_ext): Do not check the
prefixed extension name if check_unknown_prefixed_ext is false.
* elfnn-riscv.c (riscv_merge_arch_attr_info): Set
check_unknown_prefixed_ext to false for linker.
gas/
* config/tc-riscv.c (riscv_set_arch): Set
check_unknown_prefixed_ext to true for assembler.
When assembling a forward reference the symbol will be unknown and so during
do_t_adr we cannot set the thumb bit. The bit it set so early to prevent
relaxations that are invalid. i.e. relaxing a Thumb2 to Thumb1 insn when the
symbol is Thumb.
But because it's done so early we miss the case for forward references.
This patch changes it so that we additionally check the thumb bit during the
internal relocation processing.
In principle we should be able to only set the bit during reloc processing but
that would require changes to the other relocations that the instruction could
be relaxed to.
This approach still allows early relaxations (which means that we have less
iteration of internal reloc processing) while still fixing the forward reference
case.
gas/ChangeLog:
2021-05-24 Tamar Christina <tamar.christina@arm.com>
PR gas/25235
* config/tc-arm.c (md_convert_frag): Set LSB when Thumb symbol.
(relax_adr): Thumb symbols 4 bytes.
* testsuite/gas/arm/pr25235.d: New test.
* testsuite/gas/arm/pr25235.s: New test.
This patch clarify the following invalid combinations of march and mabi,
* ilp32f/lp64f abi without f extension.
* ilp32d/lp64d abi without d extension.
* ilp32q/lp64q abi without q extension.
* e extension with any abi except ilp32e
GNU assembler reports errors when finding the above invalid combinations.
But LLVM-MC reports warnings and ignores these invalid cases. It help to
set the correct ilp32/lp64/ilp32e abi according to rv32/rv64/rve. This
looks good and convenient, so perhaps we can do the same things. However,
if you don't set the mabi, GNU assembler also try to set the suitable
ABI according to march/elf-attribute. Compared to LLVM-MC, we will choose
double/quad abi if d/f extension is set.
gas/
PR 25212
* config/tc-riscv.c (riscv_set_abi_by_arch): If -mabi isn't set, we
will choose ilp32e abi for rv32e. Besides, report errors for the
invalid march and mabi combinations.
* testsuite/gas/riscv/mabi-attr-rv32e.s: New testcase. Only accept
ilp32e abi for rve extension.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64f.d: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.d: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise.
Renamed all mabi testcases to their march-mabi settings.
* config/tc-z80.c (emit_data_val): Warn on constant overflow.
(signed_overflow): New function.
(unsigned_overflow): New function.
(is_overflow): Use new functions.
(md_apply_fix): Use signed_overflow.
* testsuite/gas/z80/ez80_adl_suf.d: Fix test.
* testsuite/gas/z80/ez80_isuf.s: Likewise.
* testsuite/gas/z80/ez80_z80_suf.d: Likewise.
gas/ChangeLog:
2021-05-19 John Buddery <jvb@cyberscience.com>
PR 25599
* config/tc-ia64.c (emit_one_bundle): Increment fixup offset
by one for PCREL60B relocation on HP-UX.
The initial problem I wanted to fix here is that GAS was rejecting MVE
instructions such as:
vmov q3[2], q3[0], r2, r2
with:
Error: General purpose registers may not be the same -- `vmov q3[2],q3[0],r2,r2'
which is incorrect; such instructions are valid. Note that for moves in
the other direction, e.g.:
vmov r2, r2, q3[2], q3[0]
GAS is correct in rejecting this as it does not make sense to move both
lanes into the same register (the Arm ARM says this is CONSTRAINED
UNPREDICTABLE).
After fixing this issue, I added assembly/disassembly tests for these
vmovs. This revealed several disassembly issues, including incorrectly
marking the moves into vector lanes as UNPREDICTABLE, and disassembling
many of the vmovs as vector loads. These are now fixed.
gas/ChangeLog:
* config/tc-arm.c (do_mve_mov): Only reject vmov if we're moving
into the same GPR twice.
* testsuite/gas/arm/mve-vmov-bad-2.l: Tweak error message.
* testsuite/gas/arm/mve-vmov-3.d: New test.
* testsuite/gas/arm/mve-vmov-3.s: New test.
opcodes/ChangeLog:
* arm-dis.c (mve_opcodes): Fix disassembly of
MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
(is_mve_encoding_conflict): MVE vector loads should not match
when P = W = 0.
(is_mve_unpredictable): It's not unpredictable to use the same
source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
PR 27823
* config/tc-z80.c (emit_ld_r_m): Report an illegal load
instruction.
* testsuite/gas/z80/ill_ops.s: New test source file.
* testsuite/gas/z80/ill_ops.d: New test driver.
* testsuite/gas/z80/ill_ops.l: New test error output.
Use the pattern from other projects where we generate the html pages
in a dir named the same as the project. So now we have:
gas/doc/gas.html - single html page
gas/doc/gas/ - multiple html pages
This works for projects that have a doc/ subdir already, but gprof &
ld require a little tweaking since they generate their docs in their
respective toplevels.
This better matches other GNU projects like autoconf/automake where
the html manual is the single page form. We'll support the multi-page
form in a follow up change.
x86-64 uses rela relocations. The comment next to the field's declaration
says "Non-zero values for ELF USE_RELA targets should be viewed with
suspicion ..." And indeed the fields being non-zero causes section
contents to be accumulated into the final relocated values in addition to
the relocations' addends, which is contrary to the ELF spec.
Surely disp processing should access the disp operand, not an imm one.
This is not an active issue only because imms and disps are, at the
moment, overlapping fields of the same union.
i386_finalize_immediate() is used for both AT&T and Intel immediate
operand handling. Move an AT&T-only check to i386_immediate(), which at
the same time allows it to cover other cases as well, giving an overall
better / more consistent diagnostic.
- Drop a pointless & where just before it was checked that the
respective bits are clear already anyway.
- Avoid a not really necessary operand_type_set() and a redundant
operand_type_or() / operand_type_and() pair.
The gotha() relocation mnemonic will be outputted by OpenRISC GCC when
using the -mcmodel=large option. This relocation is used along with
got() to generate 32-bit GOT offsets. This increases the previous GOT
offset limit from the previous 16-bit (64K) limit.
This is needed on large binaries where the GOT grows larger than 64k.
bfd/ChangeLog:
PR 21464
* bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation.
* elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise.
(or1k_final_link_relocate, or1k_elf_relocate_section,
or1k_elf_check_relocs): Likewise.
* libbfd.h (bfd_reloc_code_real_names): Likewise.
* reloc.c: Likewise.
cpu/ChangeLog:
PR 21464
* or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic
for gotha() relocation.
include/ChangeLog:
PR 21464
* elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number.
opcodes/ChangeLog:
PR 21464
* or1k-asm.c: Regenerate.
gas/ChangeLog:
PR 21464
* testsuite/gas/or1k/reloc-1.s: Add test for new relocation.
* testsuite/gas/or1k/reloc-1.d: Add test result for new
relocation.
Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
fixup reloc, add tests
Now that lex_got() is uniform for all targets using it, permit COFF
targets to also use @secrel32 with, in particular, .long. This is more
natural than the custom .secrel32 directive, and also allows more
flexibility (the "+six" form of the two added test lines doesn't work
with a .secrel32 equivalent, in that it silently produces an unintended
relocation type).
As an extra benefit this also makes sure that data definitions in Intel
syntax mode would get treated like they do for e.g. ELF targets.
I see no reason at all for us to carry two copies of almost identical
code. The differences, apart from the table entries, are benign. And
the #ifdef-ary doesn't really get any worse.
Allow a few more expression forms when the entire expression can be
resolved at assembly time. For this, i386_validate_fix() needs to
arrange for all processing of the relocation to be deferred to
tc_gen_reloc().
