VDUP (neon) instructions can be conditional, but this is not taken into
account in the current master. This commit fixes that by i) fixing the
VDUP instruction masks and ii) adding logic for disassembling
conditional neon instructions.
opcodes * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
(print_insn_neon): Support disassembly of conditional
instructions.
binutils* testsuite/binutils-all/arm/vdup-cond.d: New test for testing that
conditional VDUP instructions are disassembled correctly.
* testsuite/binutils-all/arm/vdup-cond.s: New file used by
vdup-cond.d.
* testsuite/binutils-all/arm/vdup-thumb.d: New test for testing
that VDUP instructions (which are conditional in A32) can be
disassembled in thumb mode.
* testsuite/binutils-all/arm/vdup-cond.s: New file used by
vdup-thumb.d.
Add support for the JMP32 class of eBPF instructions.
cpu/ChangeLog
* bpf.cpu (define-cond-jump-insn): Renamed from djci.
(dcji) New version with support for JMP32
gas/ChangeLog
* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
* testsuite/gas/bpf/jump32.s: New file.
* testsuite/gas/bpf/jump32.d: Likewise.
opcodes/ChangeLog
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Regenerate.
* bpf-opc.h: Likewise.
This patch also had some problems. Calculation of maxlen was wrong,
and the insn arg loop needed rearranging to work with a correct length.
* disassemble.h (opcodes_assert): Declare.
(OPCODES_ASSERT): Define.
* disassemble.c: Don't include assert.h. Include opintl.h.
(opcodes_assert): New function.
* h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
(bfd_h8_disassemble): Reduce size of data array. Correctly
calculate maxlen. Omit insn decoding when insn length exceeds
maxlen. Exit from nibble loop when looking for E, before
accessing next data byte. Move processing of E outside loop.
Replace tests of maxlen in loop with assertions.
git commit beea5cc1bc fixed one use of an uninitialised value but
ignored another one a few lines later.
* arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
* arc-dis.c (find_format): Use ISO C string concatenation rather
than line continuation within a string. Don't access needs_limm
before testing opcode != NULL.
git commit d1e304bc27 was aimed at stopping uninitialised memory
access to the index_offset array. Unfortunately that patch resulted
in a different array being uninitialised for all instructions with
more than two arguments.
* ns32k-dis.c (print_insn_arg): Update comment.
(print_insn_ns32k): Reduce size of index_offset array, and
initialize, passing -1 to print_insn_arg for args that are not
an index. Don't exit arg loop early. Abort on bad arg number.
* nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
Initialize parts of buffer not written when handling a possible
2-byte insn at end of section. Don't attempt decoding of such
an insn by the 4-byte machinery.
We shouldn't really decode a 2-byte left-over at the end of a section
as if the section contains two more bytes of zeros. Not that it
matters very much, but this patch tidies the corner case.
* ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
partially filled buffer. Prevent lookup of 4-byte insns when
only VLE 2-byte insns are possible due to section size. Print
".word" rather than ".long" for 2-byte leftovers.
Since i386-opc.tbl contains '\' to avoid very long lines and i386-gen
requires that each instruction must be in one line, also pass -P to
$(CPP) to inhibit generation of linemarkers in the output from the
preprocessor to support i386-gen.
* Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
* Makefile.in: Regenerated.
These all follow an almost common pattern, again with the exception of
being commutative, which can be easily taken care of.
Note that, as an intended side effect (and in fact one of the reason to
introduce templates), AVX long-form pseudo-ops get introduced alongside
the already existing AVX512 ones.
In order to reduce redundancy as well as the chance of things going out
of sync (see a later patch for an example), make the opcode table
generator capable of recognizing and expanding templated templates. Use
the new capability for compacting the general purpose conditional insns.
Presumably as a result of various changes over the last several months,
and - for some of them - with a generalization of logic in
match_mem_size() plus mirroring of this generalization into the
broadcast handling logic of check_VecOperands(), various register-only
templates can be foled into their respective memory forms. This in
particular then also allows dropping a few more instances of IgnoreSize.
Even after commit dc2be329b9 ("i386: Only check suffix in instruction
mnemonic"), by which many of its uses have become unnecessary (some were
unnecessary even before), IgnoreSize is still used for various slightly
different purposes:
- to suppress emission of an operand size prefix,
- in Intel syntax mode to zap "derived" suffixes in certain cases and to
skip certain checks of remaining "derived" suffixes,
- to suppress ambiguous operand size / missing suffix diagnostics,
- for prefixes to suppress the "stand-alone ... prefix" warning.
Drop entirely unnecessary ones and where possible also replace instances
by the more focused (because of having just a single purpose) NoRex64.
To further restrict when IgnoreSize is needed, also generalize the logic
when to skip a template because of a present or derived L or Q suffix,
by skipping immediate operands. Additionally consider mask registers and
VecSIB there.
Note that for the time being the attribute needs to be kept in place on
MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand
template of them allows for only non-SIMD-register actuals) allowing for
Dword operands - the logic when to emit a data size prefix would need
further adjustment first.
Note also that the memory forms of {,v}pinsrw get their permission for
an L or Q suffix dropped. I can only assume that it being this way was a
cut-and-paste mistake from the register forms, as the latter
specifically have NoRex64 set, and the {,v}pextrw counterparts don't
allow these suffixes either.
Convert VexW= again to their respective VexW* on lines touched anyway.
As of commit dc2be329b9 ("i386: Only check suffix in instruction
mnemonic") these have been accepted even with "qword ptr" operand size
specifier, but in 64-bit mode they're now wrongly having a REX prefix
(with REX.W set) emitted in this case. These aren't Intel syntax
mnemonics, so rather than fixing code generation, let's simply reject
them. As a result, the Qword attribute can then be dropped, too.
When the template specifies any of the possible VexW settings, we can
use this instead of a separate NoRex64 to suppress the setting of REX_W.
Note that this ends up addressing an inconsistency between VEX- and
EVEX-encoded VEXTRACTPS, VPEXTR{B,W}, and VPINSR{B,W} - while the former
avoided setting VEX.W, the latter pointlessly set EVEX.W when there is a
64-bit GPR operand. Adjust the testcase to cover both cases.
Convert VexW= to their respective VexW* on lines touched anyway.
It is almost entirely redundant with Size64, and the sole case (CRC32)
where direct replacement isn't possible can easily be taken care of in
another way.
Since 16-bit addressing isn't allowed, Disp32 needs to be forced; Disp16
fails to match the templates.
The SDM leaves open whether BNDC[LNU] with a GPR operand require an
operand size override; this aspect is therefore left untouched here.
For proper code generation in 16-bit mode (or to avoid the "same type of
prefix used twice" diagnostic there), IgnoreSize is needed on certain
templates allowing for just 32-(and maybe 64-)bit operands.
Beyond adding tests for the previously broken cases, also add ones for
the previously working cases where IgnoreSize is needed for the same
reason (leaving out MPX for now, as that'll require an assembler change
first). Some minor adjustments to tests get done such that re-use of the
same code for 16-bit code generation testing becomes easier.
Allowing 64-bit registers is misleading here: Elsewhere these get allowed
when there's no difference between either variant, because of 32-bit
destination registers having their upper halves zeroed in 64-bit mode.
Here, however, they're source registers, and hence specifying 64-bit
registers would lead to the ambiguity of whether the upper 32 bits
actually matter.
Additionally, for proper code generation in 16-bit mode, IgnoreSize is
needed on both.
And finally, just like for e.g. MONITOR/MWAIT, add variants with all
input registers explicitly specified.
According to gas manual, suffix in instruction mnemonics isn't always
required:
When there is no sizing suffix and no (suitable) register operands to
deduce the size of memory operands, with a few exceptions and where long
operand size is possible in the first place, operand size will default
to long in 32- and 64-bit modes.
This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
must be allowed without suffix in AT&T syntax.
gas/
PR gas/25622
* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
x86-64-default-suffix-avx.
* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
* testsuite/gas/i386/noreg64.d: Updated.
* testsuite/gas/i386/noreg64.l: Likewise.
* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
opcodes/
PR gas/25622
* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
* i386-tbl.h: Regenerated.
INT_VECTOR_BASE auxiliary register is available across all ARC
architectures.
xxxx-xx-xx Claudiu Zissulescu <claziss@gmail.com>
* arc-regs.h (int_vector_base): Make it available for all ARC
CPUs.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information. We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option. Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.
gas/
* config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
whether or not this CSR is legal in the current ISA string.
(struct riscv_csr_extra): New structure to hold all extra information
of CSR.
(riscv_init_csr_hash): New function. According to the DECLARE_CSR and
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
Call hash_reg_name to insert CSR address into reg_names_hash.
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
Decide whether the CSR is valid according to the csr_extra_hash.
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
not a boolean. This is same as riscv_init_csr_hash, so keep the
consistent usage.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
f-ext CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
source file is `priv-reg.s`, and the ISA is rv64if, so the
rv32-only CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
include/
* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
record riscv_csr_class.
opcodes/
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
gdb/
* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
* riscv-tdep.h: Likewise.
* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
rv32-only CSR.
* features/riscv/64bit-csr.xml: Regernated.
binutils/
* dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
gas/
* testsuite/gas/riscv/c-add-addi.d: New testcase.
* testsuite/gas/riscv/c-add-addi.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
c.mv/c.li if rs1 is zero.
Change-Id: Id939b5e6db80d267a832545f3ffef7b9ba881f7d
AMD ABM has 2 instructions: popcnt and lzcnt. ABM CPUID feature bit has
been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt
which used to be the part of SSE4.2. This patch removes CpuABM and adds
CpuPOPCNT. It changes ABM to enable both lzcnt and popcnt, changes SSE4.2
to also enable popcnt.
gas/
* config/tc-i386.c (cpu_arch): Add .popcnt.
* doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt.
Add a tab before @samp{.sse4a}.
opcodes/
* i386-gen.c (cpu_flag_init): Replace CpuABM with
CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
CPU_POPCNT_FLAGS.
(cpu_flags): Remove CpuABM. Add CpuPOPCNT.
* i386-opc.h (CpuABM): Removed.
(CpuPOPCNT): New.
(i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
popcnt. Remove CpuABM from lzcnt.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
There don't really need to be separate Cpu64 and CpuNo64 templates for
these. One small issue with this is that slightly strange code
.intel_syntax noprefix
.code16
.arch i286
.arch .avx
vcvtsi2sd xmm0, xmm0, dword ptr [bx]
vcvtsi2sd xmm0, xmm0, qword ptr [bx]
vcvtsi2sd xmm0, xmm0, ebx
vcvtsi2sd xmm0, xmm0, rbx
now will match in behavior with the AVX512 counterparts in that not
only the 2nd vcvtsi2sd won't assemble, but also the first. The last
two, otoh, will continue to assemble fine (due to the lack of any
memory operand size specifier). As a result, another way to make
things behave more consistently would be to avoid the folding and
add IgnoreSize to the CpuNo64 AVX512 variants. A 3rd way to do so
would be to add Cpu386 to any such insn template.
While doing this also make the usual cosmetic adjustments for the
insns touched anyway. Additionally drop the redundant Cpu64 from
the SAE forms of VCVT{,U}SI2SD - they won't assemble outside of
64-bit mode due to there not being anything to match the Reg64
operand.
There's no need to have separate Cpu64 and CpuNo64 templates: There
already is special logic handling the attribute, and all that's needed
is rejecting 16-bit address registers in 64-bit mode. Suppress suffix
guessing and group all involved logic together, outside of suffix
processing (arguably it doesn't even belong in process_suffix()).
Also, since no AddrPrefixOpReg template permits any suffixes, move the
No_*Suf specifiers for them to a central place. Along with this drop
the no longer relevant NoRex64 from there.
Conversions which shrink element size and which have a memory source
can't be disambiguated between their 128- and 256-bit variants by
looking at the register operand. "operand size mismatch", however, is a
pretty misleading diagnostic. Generalize the logic introduced for
VFPCLASSP{S,D} such that, with suitable similar adjustments to the
respective templates, it'll cover these cases too.
For VCVTNEPS2BF16 also fold the two previously separate AVX512VL
templates to achieve the intended effect. This is then also accompanied
by a respective addition to the inval-avx512f testcase.
Since SSE3 is independent of SSE4a, don't disable SSE3 when disabling
SSE4a.
* i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
CPU_ANY_SSE4A_FLAGS.
commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is
a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel
SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also
adds .sse4a and nosse4a.
gas/
* config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore
nosse4.
* doc/c-i386.texi: Document sse4a and nosse4a.
opcodes/
* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
CPU_ANY_SSE4_FLAGS.
Since movsx and movzx are valid mnemonic in AT&T syntax, remove Intel
syntax comments on movsx and movzx to avoid confusing other readers.
* i386-opc.tbl (movsx): Remove Intel syntax comments.
(movzx): Likewise.
For these to get treatment consistent with other operand size checking
the special logic shouldn't live in md_assemble(), but process_suffix().
And there's more logic involved than simply zapping the suffix.
Note however that MOVS[BW]* and MOVZ[BW]* still won't be fully
consistent, due to the objection to fold MOVS* templates just like was
done for MOVZ* in c07315e0c6 ("x86: allow suffix-less movzw and 64-bit
movzb").
Note further that it is against my own intentions to have MOVSX/MOVZX
silently default to a byte source in AT&T mode. This should happen only
when the destination register is a 16-bit one. In all other cases there
is an ambiguity, and the user should be warned. But it was explicitly
requested for this to be done in a way inconsistent with everything
else.
Note finally that the assembler change points out (and this patch fixes)
a wrong Intel syntax test introduced by bc31405ebb ("x86-64: Properly
encode and decode movsxd"): When source code specifies a 16-bit
destination register, disassembly expectations shouldn't have been to
find a 32-bit one.
With AVX512VL disabled (e.g. when writing code for the Knights family
of processors) these insns aren't ambiguous when used with a memory
source, and hence should be accepted without suffix or operand size
specifier. When AVX512VL is enabled, to be consistent with this as
well as other ambiguous operand size handling it would seem better to
just warn about the ambiguity in AT&T mode, and still default to 512-bit
operands (on the assumption that the code may have been written without
AVX512VL in mind yet), but it was requested to leave AT&T syntax mode
alone here.
Now that the AMD64 check in match_template() applies to 64-bit code
only, the non-64-bit and the Amd64 template can be folded, as being
otherwise compatible with one another. (Oddly enough the same doesn't
apply to CALL, due to the suffixes it permits, while JMP doesn't
allow for any.)
