Commit Graph

9552 Commits

Author SHA1 Message Date
Nick Clifton
9546e03d55 Remove spurious text in changelog entry 2020-08-10 17:24:45 +01:00
Przemyslaw Wirkus
f7cb161ea6 [aarch64] GAS doesn't validate the architecture version for any tlbi registers. Fixed with this patch.
* gas/config/tc-aarch64.c (parse_sys_reg): Call to
	aarch64_sys_ins_reg_supported_p instead of aarch64_sys_reg_supported_p.
	(parse_sys_ins_reg): Add aarch64_sys_reg_deprecated_p check.
	* include/opcode/aarch64.h (aarch64_sys_reg_deprecated_p): Functions
	paramaters changed.
	(aarch64_sys_reg_supported_p): Function removed.
	(aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
	* opcodes/aarch64-opc.c (aarch64_print_operand):
	(aarch64_sys_reg_deprecated_p): Functions paramaters changed.
	(aarch64_sys_reg_supported_p): Function removed.
	(aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
	(aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
	into this function.
	* gas/testsuite/gas/aarch64/illegal-sysreg-5.d: New test.
	* gas/testsuite/gas/aarch64/illegal-sysreg-5.l: New test.
	* gas/testsuite/gas/aarch64/sysreg-5.s: New test.
2020-08-10 16:20:17 +01:00
Alan Modra
8b2742a156 Implement missing powerpc extended mnemonics
gas/
	* testsuite/gas/ppc/power8.d,
	* testsuite/gas/ppc/power8.s: Add miso.
	* testsuite/gas/ppc/power9.d,
	* testsuite/gas/ppc/power8.s: Add exser, msgsndu, msgclru.
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
	Enable icbt for power5, miso for power8.
2020-08-10 21:52:17 +09:30
Alan Modra
5fbec329ec Prioritise mtfprd and mtvrd over mtvsrd in PowerPC disassembly
gas/
	* testsuite/gas/ppc/power8.d: Update.
	* testsuite/gas/ppc/vsx2.d: Update.
opcodes/
	* ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
	mtvsrd, and similarly for mfvsrd.
2020-08-10 21:52:17 +09:30
Alan Modra
86c0f617ac Error on lmw, lswi and related PowerPC insns when LE
* config/tc-ppc.c (md_assemble): Error for lmw, stmw, lswi, lswx,
	stswi, or stswx in little-endian mode.
	* testsuite/gas/ppc/476.d,
	* testsuite/gas/ppc/476.s: Delete lmw, stmw, lswi, lswx, stswi, stswx.
	* testsuite/gas/ppc/a2.d,
	* testsuite/gas/ppc/a2.s: Move lmw, stmw, lswi, lswx, stswi, stswx..
	* testsuite/gas/ppc/be.d,
	* testsuite/gas/ppc/be.s: ..to here, new big-endian only test.
	* testsuite/gas/ppc/le_error.d,
	* testsuite/gas/ppc/le_error.l: New little-endian test.
	* testsuite/gas/ppc/ppc.exp: Run new tests.
2020-08-10 21:52:17 +09:30
H.J. Lu
7bb178ecf8 as: Ignore rest of line on overflow error
* read.c (read_a_source_file): Ignore rest of line on overflow
	error.
2020-08-07 06:47:56 -07:00
Alex Coplan
d27aad4ec3 gas: Fix internal error on long local labels
Prior to this commit, on an input such as "88888888888:", GAS hits a
signed integer overflow and likely an assertion failure. I see:

$ echo "88888888888:" | bin/aarch64-none-elf-as
{standard input}: Assembler messages:
{standard input}:1: Internal error in fb_label_name at ../gas/symbols.c:2049.
Please report this bug.

To fix this issue, I've taken two steps:

1. Change the type used for processing local labels in
   read_a_source_file() from int to long, to allow representing more
   local labels, and also since all uses of this variable (temp) are
   actually of type long.

2. Detect if we would overflow and bail out with an error message
   instead of actually overflowing and hitting the assertion in
   fb_label_name().

gas/ChangeLog:

2020-08-06  Alex Coplan  <alex.coplan@arm.com>

	* read.c (read_a_source_file): Use long for local labels, detect
	overflow and raise an error for overly-long labels.
	* testsuite/gas/all/gas.exp: Add local-label-overflow test.
	* testsuite/gas/all/local-label-overflow.d: New test.
	* testsuite/gas/all/local-label-overflow.l: Error output.
	* testsuite/gas/all/local-label-overflow.s: Input.
2020-08-06 17:39:03 +01:00
Christian Groessler
563a322515 Z8k: fix sout/soudb opcodes with direct address
Problem found by Tadashi G. Takaoka.

2020-08-04  Christian Groessler  <chris@groessler.org>
     Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>

 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
 opcodes (special "out" to absolute address).
 * z8k-opc.h: Regenerate.

2020-08-04  Christian Groessler  <chris@groessler.org>

 * gas/testsuite/gas/z8k/inout.d: Adapt to correct encoding of
 "sout/soutb #imm,reg"
2020-08-04 22:31:42 +02:00
H.J. Lu
789198ca95 gas/NEWS: Mention {disp16} pseudo prefix
* NEWS: Mention {disp16} pseudo prefix.
2020-08-04 05:55:31 -07:00
H.J. Lu
b0a72f49df gas: Revert an accidental change in x86-64-pseudos.d
Revert an accidental change in

commit 41eb8e8885
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Thu Jul 30 16:13:02 2020 -0700

    x86: Add {disp16} pseudo prefix

@@ -304,7 +308,7 @@ Disassembly of section .text:
  +[a-f0-9]+:  40 d3 e0                rex shl %cl,%eax
  +[a-f0-9]+:  40 a0 01 00 00 00 00 00 00 00    rex movabs 0x1,%al
  +[a-f0-9]+:  40 38 ca                rex cmp %cl,%dl
- +[a-f0-9]+:  40 b3 01                rex mov \$(0x)?1,%bl
+ +[a-f0-9]+:  40 b3 01                rex mov \$(0x)1,%bl
  +[a-f0-9]+:  f2 40 0f 38 f0 c1       rex crc32 %cl,%eax
  +[a-f0-9]+:  40 89 c3                rex mov %eax,%ebx
  +[a-f0-9]+:  41 89 c6                mov    %eax,%r14d

	PR gas/26305
	* testsuite/gas/i386/x86-64-pseudos.d: Revert an accidental
	change.
2020-08-04 05:50:23 -07:00
Mark Wielaard
6b9a135d72 gas: Use udata for DW_AT_high_pc when emitting DWARF4
For DWARF4 DW_AT_high_pc can be expressed as constant offset from
DW_AT_low_pc which saves a relocation. Use DW_FORM_udate (uleb128)
to keep the constant value as small as possible.

gas/ChangeLog:

       * dwarf2dbg.c (out_debug_abbrev): When DWARF2_VERSION >= 4, use
       DW_FORM_udata for DW_AT_high_pc.
       (out_debug_info): Use emit_leb128_expr for DW_AT_high_pc, when
       DWARF2_VERSION >= 4.
       * read.c (emit_leb128_exp): No longer static.
       * read.h (emit_leb128_exp): Define.
2020-08-04 11:42:53 +02:00
Mark Wielaard
f63d03dde0 gas: Make sure .debug_line file table contains a zero filename and dir
For DWARF5 the zero file list entry in the .debug_line table represents
the compile unit main file. It can be set with .file 0 when -gdwarf-5
is given. But since this directive is illegal for older versions, this
is almost never set. To make sure it is always set (so DW_AT_name of
the compile unit can be set) use file (and dir) 1 if that is defined
(otherwise fall back to pwd, to match DW_AT_comp_dir).

gas/ChangeLog:

	* gas/dwarf2dbg.c (out_dir_and_file_list): For DWARF5 emit at
	least one directory if there is at least one file. Use dirs[1]
	if dirs[0] is not set, or if there is no dirs[1] the current
	working directory. Use files[1] filename, when files[0] filename
	isn't set.
2020-08-04 11:28:39 +02:00
Mark Wielaard
a3b3e8586d gas: Fix .debug_info CU header for --gdwarf-5
DWARF5 CU headers have a new unit type field and move the abbrev offset
to the end of the header.

gas/ChangeLog:

	* dwarf2dbg.c (out_debug_info): Emit unit type and abbrev offset
	for DWARF5.
	* gas/testsuite/gas/elf/dwarf-4-cu.d: New file.
	* gas/testsuite/gas/elf/dwarf-4-cu.s: Likewise.
	* gas/testsuite/gas/elf/dwarf-5-cu.d: Likewise.
	* gas/testsuite/gas/elf/dwarf-5-cu.s: Likewise.
	* testsuite/gas/elf/elf.exp: Run dwarf-4-cu and dwarf-5-cu.
2020-08-04 11:28:39 +02:00
Mark Wielaard
25b1f10d9b gas: Fix as.texi typo infortmation
gas/ChangeLog:

	* doc/as.texi (--gdwarf-[345]): Fix typo.
2020-08-04 11:28:39 +02:00
Jozef Lawrynowicz
e4ae357fe8 MSP430: Remove unused -md GAS option
The MSP430 GAS option "-md" is supposed to indicate that the CRT startup
code should copy data from ROM to RAM at startup. However, this option
has no effect; GAS handles the related behaviour automatically by
looking for the presence of certain symbols in the input file.

gas/ChangeLog:

	* config/tc-msp430.c (OPTION_MOVE_DATA): Remove.
	(md_parse_option): Remove case for OPTION_MOVE_DATA.
	(md_longopts): Remove "md" entry.
	(md_show_usage): Likewise.
2020-08-03 16:05:48 +01:00
H.J. Lu
41eb8e8885 x86: Add {disp16} pseudo prefix
Use Prefix_XXX for pseudo prefixes.  Add {disp16} pseudo prefix and
replace {disp32} pseudo prefix with {disp16} in 16-bit mode test.
Check invalid {disp16}/{disp32} pseudo prefixes.

gas/

	PR gas/26305
	* config/tc-i386.c (_i386_insn::disp_encoding): Add
	disp_encoding_16bit.
	(parse_insn): Check Prefix_XXX for pseudo prefixes.  Handle
	{disp16}.
	(build_modrm_byte): Handle {disp16}.
	(i386_index_check): Check invalid {disp16} and {disp32} pseudo
	prefixes.
	* doc/c-i386.texi: Update {disp32} documentation and document
	{disp16}.
	* testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo.
	* testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16}
	tests.
	* testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps
	tests with 128-byte displacement.  Add {disp16} tests.
	* testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32}
	vmovaps test.  Add (%r13)/(%r13d) tests.
	* testsuite/gas/i386/x86-64-inval-pseudo.l: New file.
	* testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise.
	* testsuite/gas/i386/inval-pseudo.l: Updated.
	* testsuite/gas/i386/pseudos.d: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.d: Likewise.

opcodes/

	PR gas/26305
	* i386-opc.h (Prefix_Disp8): New.
	(Prefix_Disp16): Likewise.
	(Prefix_Disp32): Likewise.
	(Prefix_Load): Likewise.
	(Prefix_Store): Likewise.
	(Prefix_VEX): Likewise.
	(Prefix_VEX3): Likewise.
	(Prefix_EVEX): Likewise.
	(Prefix_REX): Likewise.
	(Prefix_NoOptimize): Likewise.
	* i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
	* i386-tbl.h: Regenerated.
2020-07-30 16:13:17 -07:00
Nick Clifton
3f853ba383 Strange - my previous commit to as.c to set the default dwarf level to 3 seems to have disappeared. So here is the commit again. 2020-07-30 16:23:09 +01:00
Nick Clifton
f291783b26 Default to DWARF level 3 for the assembler.
* as.c (dwarf_level): Initialise to 3 in case this is not set on
	the command line.
2020-07-30 14:59:39 +01:00
Rainer Orth
c8693053f8 Unify Solaris procfs and largefile handling
GDB currently doesn't build on 32-bit Solaris:

* On Solaris 11.4/x86:

In file included from /usr/include/sys/procfs.h:26,
                 from /vol/src/gnu/gdb/hg/master/dist/gdb/i386-sol2-nat.c:24:
/usr/include/sys/old_procfs.h:31:2: error: #error "Cannot use procfs in the large file compilation environment"
 #error "Cannot use procfs in the large file compilation environment"
  ^~~~~

* On Solaris 11.3/x86 there are several more instances of this.

The interaction between procfs and large-file support historically has
been a royal mess on Solaris:

* There are two versions of the procfs interface:

** The old ioctl-based /proc, deprecated and not used any longer in
   either gdb or binutils.

** The `new' (introduced in Solaris 2.6, 1997) structured /proc.

* There are two headers one can possibly include:

** <procfs.h> which only provides the structured /proc, definining
   _STRUCTURED_PROC=1 and then including ...

** <sys/procfs.h> which defaults to _STRUCTURED_PROC=0, the ioctl-based
   /proc, but provides structured /proc if _STRUCTURED_PROC == 1.

* procfs and the large-file environment didn't go well together:

** Until Solaris 11.3, <sys/procfs.h> would always #error in 32-bit
   compilations when the large-file environment was active
   (_FILE_OFFSET_BITS == 64).

** In both Solaris 11.4 and Illumos, this restriction was lifted for
   structured /proc.

So one has to be careful always to define _STRUCTURED_PROC=1 when
testing for or using <sys/procfs.h> on Solaris.  As the errors above
show, this isn't always the case in binutils-gdb right now.

Also one may need to disable large-file support for 32-bit compilations
on Solaris.  config/largefile.m4 meant to do this by wrapping the
AC_SYS_LARGEFILE autoconf macro with appropriate checks, yielding
ACX_LARGEFILE.  Unfortunately the macro doesn't always succeed because
it neglects the _STRUCTURED_PROC part.

To make things even worse, since GCC 9 g++ predefines
_FILE_OFFSET_BITS=64 on Solaris.  So even if largefile.m4 deciced not to
enable large-file support, this has no effect, breaking the gdb build.

This patch addresses all this as follows:

* All tests for the <sys/procfs.h> header are made with
  _STRUCTURED_PROC=1, the definition going into the various config.h
  files instead of having to make them (and sometimes failing) in the
  affected sources.

* To cope with the g++ predefine of _FILE_OFFSET_BITS=64,
  -U_FILE_OFFSET_BITS is added to various *_CPPFLAGS variables.  It had
  been far easier to have just

  #undef _FILE_OFFSET_BITS

  in config.h, but unfortunately such a construct in config.in is
  commented by config.status irrespective of indentation and whitespace
  if large-file support is disabled.  I found no way around this and
  putting the #undef in several global headers for bfd, binutils, ld,
  and gdb seemed way more invasive.

* Last, the applicability check in largefile.m4 was modified only to
  disable largefile support if really needed.  To do so, it checks if
  <sys/procfs.h> compiles with _FILE_OFFSET_BITS=64 defined.  If it
  doesn't, the disabling only happens if gdb exists in-tree and isn't
  disabled, otherwise (building binutils from a tarball), there's no
  conflict.

  What initially confused me was the check for $plugins here, which
  originally caused the disabling not to take place.  Since AC_PLUGINGS
  does enable plugin support if <dlfcn.h> exists (which it does on
  Solaris), the disabling never happened.

  I could find no explanation why the linker plugin needs large-file
  support but thought it would be enough if gld and GCC's lto-plugin
  agreed on the _FILE_OFFSET_BITS value.  Unfortunately, that's not
  enough: lto-plugin uses the simple-object interface from libiberty,
  which includes off_t arguments.  So to fully disable large-file
  support would mean also disabling it in libiberty and its users: gcc
  and libstdc++-v3.  This seems highly undesirable, so I decided to
  disable the linker plugin instead if large-file support won't work.

The patch allows binutils+gdb to build on i386-pc-solaris2.11 (both
Solaris 11.3 and 11.4, using GCC 9.3.0 which is the worst case due to
predefined _FILE_OFFSET_BITS=64).  Also regtested on
amd64-pc-solaris2.11 (again on Solaris 11.3 and 11.4),
x86_64-pc-linux-gnu and i686-pc-linux-gnu.

	config:
	* largefile.m4 (ACX_LARGEFILE) <sparc-*-solaris*|i?86-*-solaris*>:
	Check for <sys/procfs.h> incompatilibity with large-file support
	on Solaris.
	Only disable large-file support and perhaps plugins if needed.
	Set, substitute LARGEFILE_CPPFLAGS if so.

	bfd:
	* bfd.m4 (BFD_SYS_PROCFS_H): New macro.
	(BFD_HAVE_SYS_PROCFS_TYPE): Require BFD_SYS_PROCFS_H.
	Don't define _STRUCTURED_PROC.
	(BFD_HAVE_SYS_PROCFS_TYPE_MEMBER): Likewise.
	* elf.c [HAVE_SYS_PROCFS_H] (_STRUCTURED_PROC): Don't define.
	* configure.ac: Use BFD_SYS_PROCFS_H to check for <sys/procfs.h>.
	* configure, config.in: Regenerate.
	* Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* Makefile.in, doc/Makefile.in: Regenerate.

	binutils:
	* Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* Makefile.in, doc/Makefile.in: Regenerate.
	* configure: Regenerate.

	gas:
	* Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* Makefile.in, doc/Makefile.in: Regenerate.
	* configure: Regenerate.

	gdb:
	* proc-api.c (_STRUCTURED_PROC): Don't define.
	* proc-events.c: Likewise.
	* proc-flags.c: Likewise.
	* proc-why.c: Likewise.
	* procfs.c: Likewise.

	* Makefile.in (INTERNAL_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* configure, config.in: Regenerate.

	gdbserver:
	* configure, config.in: Regenerate.

	gdbsupport:
	* Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* common.m4 (GDB_AC_COMMON): Use BFD_SYS_PROCFS_H to check for
	<sys/procfs.h>.
	* Makefile.in: Regenerate.
	* configure, config.in: Regenerate.

	gnulib:
	* configure.ac: Run ACX_LARGEFILE before gl_EARLY.
	* configure: Regenerate.

	gprof:
	* Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

	ld:
	* Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
2020-07-30 15:41:50 +02:00
H.J. Lu
ac2599c447 x86: Pass --gdwarf-3 to assembler
Pass --gdwarf-3 to assembler for

commit 4d8ee86073
Author: Nick Clifton <nickc@redhat.com>
Date:   Thu Jul 30 08:39:14 2020 +0100

    Prevent the generation of DWARF level 0 line number tables...

binutils/

	* testsuite/binutils-all/i386/compressed-1a.d: Pass --gdwarf-3
	to assembler.
	* testsuite/binutils-all/i386/compressed-1b.d: Likewise.
	* testsuite/binutils-all/i386/compressed-1c.d: Likewise.
	* testsuite/binutils-all/x86-64/compressed-1a.d: Likewise.
	* testsuite/binutils-all/x86-64/compressed-1b.d: Likewise.
	* testsuite/binutils-all/x86-64/compressed-1c.d: Likewise.

gas/

	* testsuite/gas/elf/dwarf2-3.d:Pass --gdwarf-3 to assembler.
	* testsuite/gas/elf/dwarf2-5.d: Likewise.
	* testsuite/gas/i386/dw2-compress-3a.d: Likewise.
	* testsuite/gas/i386/dw2-compress-3b.d: Likewise.
	* testsuite/gas/i386/dw2-compressed-3a.d: Likewise.
	* testsuite/gas/i386/dw2-compressed-3b.d: Likewise.
2020-07-30 04:56:46 -07:00
Nick Clifton
4d8ee86073 Prevent the generation of DWARF level 0 line number tables...
* as.c (dwarf_level): Initialise to 4 in case this is not set on
	the command line.
2020-07-30 08:39:14 +01:00
Maciej W. Rozycki
c77cb2a09c MIPS: Make the IRIX naming of local section symbols consistent
Make the MIPS/IRIX naming of local section symbols consistent between
files produced by generic ELF code and ELF linker code, complementing
commit 174fd7f955 ("New bfd elf hook: force naming of local section
symbols"), <https://sourceware.org/ml/binutils/2004-02/msg00072.html>.

Local section symbols have no names in the standard ELF gABI, however
the lack of a name causes problems with IRIX's MIPSpro linker.  To work
around the issue we give them names, however we do that in generic ELF
code only, based on what the `elf_backend_name_local_section_symbols'
hook returns if present.  That makes objects created by GAS or `objdump'
work correctly, however not ones created by `ld -r'.  That would not
normally cause issues with IRIX systems using GAS and `objdump' only
with the MIPSpro linker, however if GNU LD was used for whatever reason
in producing objects later fed to IRIX's MIPSpro linker, then things
would break.

Modify ELF linker code accordingly then, using the same hook.  Adjust
the `ld-elf/64ksec-r' test accordingly so that it also accepts a section
symbol with a name.

Also modify the hook itself so that only actual ET_REL objects have
names assigned to local section symbols.  Other kinds of ELF files are
not ever supposed to be relocated with the MIPSpro linker, so we can
afford producing more standard output.

Add suitable GAS, LD and `objcopy' test cases to the relevant testsuites
to keep these tools consistently verified.  This change also fixes:

FAIL: objcopy executable (pr25662)

across MIPS targets using the IRIX compatibility mode.

	bfd/
	* elflink.c (bfd_elf_final_link): Give local symbols a name if
	so requested.
	* elfxx-mips.c (_bfd_mips_elf_name_local_section_symbols): Only
	return TRUE if making ET_REL output.

	binutils/
	* testsuite/binutils-all/mips/global-local-symtab-sort-o32.d:
	New test.
	* testsuite/binutils-all/mips/global-local-symtab-sort-o32t.d:
	New test.
	* testsuite/binutils-all/mips/global-local-symtab-sort-n32.d:
	New test.
	* testsuite/binutils-all/mips/global-local-symtab-sort-n32t.d:
	New test.
	* testsuite/binutils-all/mips/global-local-symtab-sort-n64.d:
	New test.
	* testsuite/binutils-all/mips/global-local-symtab-sort-n64t.d:
	New test.
	* testsuite/binutils-all/mips/global-local-symtab-final-o32.d:
	New test.
	* testsuite/binutils-all/mips/global-local-symtab-final-n32.d:
	New test.
	* testsuite/binutils-all/mips/global-local-symtab-final-n64.d:
	New test.
	* testsuite/binutils-all/mips/mips.exp: Run the new tests.

	gas/
	* testsuite/gas/mips/global-local-symtab-sort-o32.d: New test.
	* testsuite/gas/mips/global-local-symtab-sort-o32t.d: New test.
	* testsuite/gas/mips/global-local-symtab-sort-n32.d: New test.
	* testsuite/gas/mips/global-local-symtab-sort-n32t.d: New test.
	* testsuite/gas/mips/global-local-symtab-sort-n64.d: New test.
	* testsuite/gas/mips/global-local-symtab-sort-n64t.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-elf/sec64k.exp: Also accept a section symbol with
	a name.
	* testsuite/ld-mips-elf/global-local-symtab-sort-o32.d: New
	test.
	* testsuite/ld-mips-elf/global-local-symtab-sort-o32t.d: New
	test.
	* testsuite/ld-mips-elf/global-local-symtab-sort-n32.d: New
	test.
	* testsuite/ld-mips-elf/global-local-symtab-sort-n32t.d: New
	test.
	* testsuite/ld-mips-elf/global-local-symtab-sort-n64.d: New
	test.
	* testsuite/ld-mips-elf/global-local-symtab-sort-n64t.d: New
	test.
	* testsuite/ld-mips-elf/global-local-symtab-final-o32.d: New
	test.
	* testsuite/ld-mips-elf/global-local-symtab-final-n32.d: New
	test.
	* testsuite/ld-mips-elf/global-local-symtab-final-n64.d: New
	test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2020-07-29 20:56:41 +01:00
Maciej W. Rozycki
3f1b17bbf0 MIPS/LD: Set symtab's `sh_info' correctly for IRIX emulations
Correct ELF linker code so as to set the `sh_info' value of the static
symbol table section according to the section symbols vs other symbols
split where required by the selection of the IRIX compatibility mode for
MIPS target.  Add a `elf_backend_elfsym_local_is_section' hook for that
purpose, returning TRUE if it is only STB_LOCAL/STT_SECTION symbols that
are to be considered local for the purpose of this split rather than all
STB_LOCAL symbols.

We do it already in generic ELF code, and have done it since 1993, with
the `elf_backend_sym_is_global' hook, affecting GAS and `objcopy', so
these tools produce correct ELF output in the IRIX compatibility mode,
however if such output is fed as input to `ld -r', then the linker's
output is no longer valid for that mode.  The relevant changes to
generic ELF code are:

commit 062189c6ea
Author: Ian Lance Taylor <ian@airs.com>
Date:   Thu Nov 18 17:12:47 1993 +0000

and:

commit 6e07e54f1b
Author: Ian Lance Taylor <ian@airs.com>
Date:   Thu Jan 6 20:01:42 1994 +0000

(split across two GIT commits likely due to repository conversion
peculiarities).

The `elf_backend_sym_is_global' hook however operates on BFD rather than
ELF symbols, making it unsuitable for the ELF linker as the linker does
not convert any symbol tables processed into the BFD format.  Converting
the hook to operate on ELF symbols would in principle be possible, but
it would still require a considerable rewrite of `bfd_elf_final_link' to
adapt to the interface.

Therefore, especially given that no new use for the IRIX compatibility
mode is expected, minimize changes made to the ELF linker code and just
add an entirely new hook, and wire it in the o32 and n32 MIPS backends
accordingly; the n64 backend never uses the IRIX compatibility mode.

Since we have no coverage here at all add suitable GAS, LD and `objcopy'
test cases to the relevant testsuites to keep these tools consistently
verified.

	bfd/
	* elf-bfd.h (elf_backend_data): Add
	`elf_backend_elfsym_local_is_section' member.
	* elfxx-target.h (elf_backend_elfsym_local_is_section): New
	macro.
	(elfNN_bed): Add `elf_backend_elfsym_local_is_section' member.
	* elflink.c (bfd_elf_final_link): Use it to determine whether
	set the `.symtab' section's `sh_info' value to the index of the
	first non-local or non-section symbol.
	* elf32-mips.c (mips_elf32_elfsym_local_is_section): New
	function.
	(elf_backend_elfsym_local_is_section): New macro.
	* elfn32-mips.c (mips_elf_n32_elfsym_local_is_section): New
	function.
	(elf_backend_elfsym_local_is_section): New macro.

	binutils/
	* testsuite/binutils-all/mips/global-local-symtab-o32.d: New
	test.
	* testsuite/binutils-all/mips/global-local-symtab-o32t.d: New
	test.
	* testsuite/binutils-all/mips/global-local-symtab-n32.d: New
	test.
	* testsuite/binutils-all/mips/global-local-symtab-n32t.d: New
	test.
	* testsuite/binutils-all/mips/global-local-symtab-n64.d: New
	test.
	* testsuite/binutils-all/mips/mips.exp: Run the new tests.

	gas/
	* testsuite/gas/mips/global-local-symtab-o32.d: New test.
	* testsuite/gas/mips/global-local-symtab-o32t.d: New test.
	* testsuite/gas/mips/global-local-symtab-n32.d: New test.
	* testsuite/gas/mips/global-local-symtab-n32t.d: New test.
	* testsuite/gas/mips/global-local-symtab-n64.d: New test.
	* testsuite/gas/mips/global-local-symtab.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/global-local-symtab-o32.d: New test.
	* testsuite/ld-mips-elf/global-local-symtab-o32t.d: New test.
	* testsuite/ld-mips-elf/global-local-symtab-n32.d: New test.
	* testsuite/ld-mips-elf/global-local-symtab-n32t.d: New test.
	* testsuite/ld-mips-elf/global-local-symtab-n64.d: New test.
	* testsuite/ld-mips-elf/global-local-symtab.ld: New test linker
	script.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2020-07-29 20:56:41 +01:00
H.J. Lu
1a02d6b0ff x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp)
Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use
disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}.

Note: Since there is no disp32 on 0(%bp), use disp16 instead.

	PR gas/26305
	* config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on
	(%bp)/(%ebp)/(%rbp) for {disp32}.
	* doc/c-i386.texi: Update {disp32} documentation.
	* testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests.
	* testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests.
	* testsuite/gas/i386/pseudos.d: Updated.
	* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
2020-07-28 03:55:53 -07:00
H.J. Lu
608d61c202 doc: Replace preceeded with preceded
binutils/

	* doc/binutils.texi: Replace preceeded with preceded.

gas/

	* doc/as.texi: Replace preceeded with preceded.
2020-07-27 05:52:14 -07:00
Maciej W. Rozycki
39fdda0744 MIPS/GAS/testsuite: Fix JALR relocation tests for IRIX targets
With IRIX targets the JALR hint relocation is not produced for the o32
ABI, where it is considered a GNU extension.  Consequently several tests
fail as the output produced by GAS fails to match patterns expecting the
relocation to be present where appropriate, even though output produced
is indeed correct.

As the absence of the relocation is expected, fix the tests by providing
respective alternative dump patterns with any JALR relocations removed,
removing numerous failures with `*-*-irix*' targets:

FAIL: MIPS jal-svr4pic (interaptiv-mr2)
FAIL: MIPS jal-svr4pic (micromips)
FAIL: MIPS jal-svr4pic (mips1)
FAIL: MIPS jal-svr4pic (mips2)
FAIL: MIPS jal-svr4pic (mips3)
FAIL: MIPS jal-svr4pic (mips4)
FAIL: MIPS jal-svr4pic (mips5)
FAIL: MIPS jal-svr4pic (mips32)
FAIL: MIPS jal-svr4pic (mips32r2)
FAIL: MIPS jal-svr4pic (mips32r3)
FAIL: MIPS jal-svr4pic (mips32r5)
FAIL: MIPS jal-svr4pic (mips32r6)
FAIL: MIPS jal-svr4pic (mips64)
FAIL: MIPS jal-svr4pic (mips64r2)
FAIL: MIPS jal-svr4pic (mips64r3)
FAIL: MIPS jal-svr4pic (mips64r5)
FAIL: MIPS jal-svr4pic (mips64r6)
FAIL: MIPS jal-svr4pic (octeon)
FAIL: MIPS jal-svr4pic (octeon2)
FAIL: MIPS jal-svr4pic (octeon3)
FAIL: MIPS jal-svr4pic (octeonp)
FAIL: MIPS jal-svr4pic (r3000)
FAIL: MIPS jal-svr4pic (r3900)
FAIL: MIPS jal-svr4pic (r4000)
FAIL: MIPS jal-svr4pic (r5900)
FAIL: MIPS jal-svr4pic (sb1)
FAIL: MIPS jal-svr4pic (vr5400)
FAIL: MIPS jal-svr4pic (xlr)
FAIL: MIPS jal-svr4pic noreorder (interaptiv-mr2)
FAIL: MIPS jal-svr4pic noreorder (micromips)
FAIL: MIPS jal-svr4pic noreorder (mips1)
FAIL: MIPS jal-svr4pic noreorder (mips2)
FAIL: MIPS jal-svr4pic noreorder (mips3)
FAIL: MIPS jal-svr4pic noreorder (mips4)
FAIL: MIPS jal-svr4pic noreorder (mips5)
FAIL: MIPS jal-svr4pic noreorder (mips32)
FAIL: MIPS jal-svr4pic noreorder (mips32r2)
FAIL: MIPS jal-svr4pic noreorder (mips32r3)
FAIL: MIPS jal-svr4pic noreorder (mips32r5)
FAIL: MIPS jal-svr4pic noreorder (mips32r6)
FAIL: MIPS jal-svr4pic noreorder (mips64)
FAIL: MIPS jal-svr4pic noreorder (mips64r2)
FAIL: MIPS jal-svr4pic noreorder (mips64r3)
FAIL: MIPS jal-svr4pic noreorder (mips64r5)
FAIL: MIPS jal-svr4pic noreorder (mips64r6)
FAIL: MIPS jal-svr4pic noreorder (octeon)
FAIL: MIPS jal-svr4pic noreorder (octeon2)
FAIL: MIPS jal-svr4pic noreorder (octeon3)
FAIL: MIPS jal-svr4pic noreorder (octeonp)
FAIL: MIPS jal-svr4pic noreorder (r3000)
FAIL: MIPS jal-svr4pic noreorder (r3900)
FAIL: MIPS jal-svr4pic noreorder (r4000)
FAIL: MIPS jal-svr4pic noreorder (r5900)
FAIL: MIPS jal-svr4pic noreorder (sb1)
FAIL: MIPS jal-svr4pic noreorder (vr5400)
FAIL: MIPS jal-svr4pic noreorder (xlr)
FAIL: MIPS R3000 jal-xgot
FAIL: MIPS -mabi=32 test 2 (SVR4 PIC)
FAIL: gas/mips/jalr2
FAIL: Relax microMIPS branches (pic)
FAIL: Relax microMIPS branches (insn32 mode, pic)

Strictly speaking no MIPSr6 or microMIPS target is supported by IRIX,
but GAS supports such configurations on the basis of uniformity, so
provide the relevant patterns too rather than excluding the combinations
from testing.

	gas/
	* testsuite/gas/mips/jal-svr4pic-irix.d: New file.
	* testsuite/gas/mips/mips1@jal-svr4pic-irix.d: New file.
	* testsuite/gas/mips/mipsr6@jal-svr4pic-irix.d: New file.
	* testsuite/gas/mips/micromips@jal-svr4pic-irix.d: New file.
	* testsuite/gas/mips/r3000@jal-svr4pic-irix.d: New file.
	* testsuite/gas/mips/jal-svr4pic-local-irix.d: New file.
	* testsuite/gas/mips/mips1@jal-svr4pic-local-irix.d: New file.
	* testsuite/gas/mips/micromips@jal-svr4pic-local-irix.d: New
	file.
	* testsuite/gas/mips/r3000@jal-svr4pic-local-irix.d: New file.
	* testsuite/gas/mips/jal-svr4pic-noreorder-irix.d: New file.
	* testsuite/gas/mips/mips1@jal-svr4pic-noreorder-irix.d: New
	file.
	* testsuite/gas/mips/mipsr6@jal-svr4pic-noreorder-irix.d: New
	file.
	* testsuite/gas/mips/micromips@jal-svr4pic-noreorder-irix.d: New
	file.
	* testsuite/gas/mips/r3000@jal-svr4pic-noreorder-irix.d: New
	file.
	* testsuite/gas/mips/jal-xgot-irix.d: New file.
	* testsuite/gas/mips/jalr2-irix.d: New file.
	* testsuite/gas/mips/micromips-branch-relax-insn32-pic-irix.d:
	New file.
	* testsuite/gas/mips/micromips-branch-relax-pic-irix.d: New
	file.
	* testsuite/gas/mips/mips-abi32-pic2-irix.d: New file.
	* testsuite/gas/mips/jal-svr4pic-local.d: Don't exclude
	`*-*-irix*' targets.  Add source file designator.
	* testsuite/gas/mips/mips1@jal-svr4pic-local.d: Don't exclude
	`*-*-irix*' targets.
	* testsuite/gas/mips/r3000@jal-svr4pic-local.d: Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
	* testsuite/gas/mips/jalr2.d: Add name designator.
	* testsuite/gas/mips/mips.exp: Use respective IRIX variants for
	tests involving the JALR relocation throughout.
2020-07-22 12:46:00 +01:00
Maciej W. Rozycki
b83d958fc7 MIPS/GAS/testsuite: Use a helper variable for IRIX/non-IRIX test selection
Define a helper variable for IRIX/non-IRIX test selection and use it
with the PR 14798 test case.

	gas/
	* testsuite/gas/mips/mips.exp: Use a helper variable for
	IRIX/non-IRIX test selection.
2020-07-22 12:46:00 +01:00
Jan Beulich
bf4ba07ca6 Revert "x86: Don't display eiz with no scale"
This reverts commit 04c662e2b6.
In my underlying suggestion I neglected the fact that in those
cases (,%eiz,1) is the only visible indication that 32-bit
addressing is in effect.
2020-07-21 14:20:11 +02:00
Cooper Qu
2b42b0415a Fix Unreasonable arch and cpu conflict warning for ther CSky architecture.
* config/tc-csky.c (md_begin): Fix tests of arch and mach flags.
2020-07-21 11:32:44 +01:00
Jan Beulich
185a798e66 Revert "x86: Replace evex-no-scale.s with evex-no-scale-[32|64].s"
This reverts commit 19449d7c67, addressing
the issue that was run into back then: There was no relationship to i686-*
and/or cross builds on 64-bit hosts. The sole problem was the use of / as
as comment character in certain ELF targets. Instead of division, use a
comparison operation.

At the same time also revert the ELF related part of 99c2d522f7 ("x86:
Update assembler tests for non-ELF targets") by replacing the construct
that's problematic for non-ELF, and by adding the "#pass" patterns to
the expected output files to cover for the tail padding generated into
COFF output.
2020-07-21 11:34:40 +02:00
Maciej W. Rozycki
ec4fcab0ee MIPS/GAS: Remove stale `prev_reloc_op_frag' variable
Ever since commit 4d7206a284 ("Rework MIPS macro relaxation, fix string
merging bug"), <https://sourceware.org/ml/binutils/2004-01/msg00248.html>,
`prev_reloc_op_frag' has only been set and never used.  Remove it then.

	gas/
	* config/tc-mips.c (prev_reloc_op_frag): Remove variable.
	(my_getSmallExpression): Adjust accordingly.
2020-07-21 01:59:24 +01:00
Jan Beulich
b3983e5f53 x86: handle SVR4 escaped binary operators
PR gas/4572

When / is a comment character, its use as binary "divide" operator needs
escaping by a backslash. Besides the scrubber needing to support this
(addressed in an earlier change), there are also a few provisions needed
in target specific operator handling.

As the spec calls for % and * to also be escaped because of being
"overloaded", also recognize these, despite the overloading there not
really preventing their use as operators in most (%) or all (*) cases,
given the way how the rest of the assembler works.

To bring source and testsuite in line, also drop the TE_I386AIX part of
the respective conditional, as i?86-*-aix* support had been removed a
while ago.
2020-07-20 08:57:18 +02:00
Jan Beulich
750e4bf70f gas: generalize comment character escaping recognition
PR gas/4572

Generalize what ab1fadc6b2 ("PR22714, Assembler preprocessor loses
track of \@") did to always honor escaped comment chars. Use this then
to support escaped /, %, and * operators on x86, when / is a comment
char (to match the Sun assembler's behavior).
2020-07-20 08:56:23 +02:00
Jan Beulich
48ef937e91 x86: honor absolute section when emitting code
Various provisions exist for insns to be placed in the absolute section,
yet actually trying to do so didn't work. While data emission (of non-
zero values) is not allowed by generic code, I think this functionality
is useful for the programmer to be able to determine the size of insns.
Therefore, rather than turning the silnet failure into a verbose one,
make things mostly work; the one class of insns not supported (yet) are
branches (JMP and Jcc) with dynamically determined displacement widths.
In this one case, an error now gets reported instead of silently
ignoring the code.

Also avoid recording ISA / feature usage for insns emitted to the
absolute section.
2020-07-20 08:55:48 +02:00
Jan Beulich
693bec1ed6 ix86: enable more ELF tests for VxWorks
The tree-wide is_elf_format predicate excludes VxWorks, but the majority
of ELF specific tests is quite fine for this target.
2020-07-20 08:54:37 +02:00
H.J. Lu
2585b7a5ce x86: Change PLT32 reloc against section to PC32
Commit 292676c1 resolved PLT32 reloc aganst local symbol to section.
Since PLT32 relocation must be against symbols, turn such PLT32
relocation into PC32 relocation.

gas/

	PR gas/26263
	* config/tc-i386.c (i386_validate_fix): Change PLT32 reloc
	against section to PC32 reloc.
	* testsuite/gas/i386/relax-5.d: Updated.
	* testsuite/gas/i386/x86-64-relax-4.d: Likewise.

ld/

	PR gas/26263
	* testsuite/ld-i386/i386.exp: Run PR gas/26263 test.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
	* testsuite/ld-i386/pr26263.d: New file.
	* testsuite/ld-x86-64/pr26263.d: Likewise.
	* testsuite/ld-x86-64/pr26263.s: Likewise.
2020-07-19 06:51:32 -07:00
H.J. Lu
04c662e2b6 x86: Don't display eiz with no scale
Change

67 48 8b 1c 25 ef cd ab 89 	mov    0x89abcdef(,%eiz,1),%rbx

to

67 48 8b 1c 25 ef cd ab 89 	mov    0x89abcdef,%rbx

in AT&T syntax and

67 48 8b 1c 25 ef cd ab 89 	mov    rbx,QWORD PTR [eiz*1+0x89abcdef]

to

67 48 8b 1c 25 ef cd ab 89 	mov    rbx,QWORD PTR ds:0x89abcdef

in Intel syntax.

gas/

	PR gas/26237
	* testsuite/gas/i386/evex-no-scale-64.d: Updated.
	* testsuite/gas/i386/addr32.d: Likewise.
	* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-addr32.d: Likewise.

opcodes/

	PR gas/26237
	* i386-dis.c (OP_E_memory): Don't display eiz with no scale
	without base nor index registers.
2020-07-15 06:57:47 -07:00
Nick Clifton
56c1b507aa Fix the generation of relocs for missing build notes.
* write.c (create_note_reloc): Add desc2_size parameter.  Zero out
	the addend field of REL relocations.  Store the full addend into
	the note for REL relocations.
2020-07-15 12:52:53 +01:00
Jan Beulich
e2e018c340 x86-64: adjust stack insn test case
The value chosen for the 16-/32-bit immediate cases didn't work well
with the subsequent insn's REX prefix - we ought to pick a value the
upper two bytes of which evaluate to a 2-byte insn. Bump the values
accordingly, allowing the subsequent insn to actually have the intended
REX.W.
2020-07-15 08:54:40 +02:00
Jan Beulich
36938cabf0 x86: avoid attaching suffixes to unambiguous insns
"Unambiguous" is is in particular taking as reference the assembler,
which also accepts certain insns - despite them allowing for varying
operand size, and hence in principle being ambiguous - without any
suffix. For example, from the very beginning of the life of x86-64 I had
trouble understanding why a plain and simple RET had to be printed as
RETQ. In case someone really used the 16-bit form, RETW disambiguates
the two quite fine.
2020-07-15 08:53:55 +02:00
H.J. Lu
8e58ef803c x86-64: Zero-extend lower 32 bits displacement to 64 bits
Since the addr32 (0x67) prefix zero-extends the lower 32 bits address to
64 bits, change disassembler to zero-extend the lower 32 bits displacement
to 64 bits when there is no base nor index registers.

gas/

	PR gas/26237
	* testsuite/gas/i386/addr32.s: Add tests for 32-bit wrapped around
	address.
	* testsuite/gas/i386/x86-64-addr32.s: Likewise.
	* testsuite/gas/i386/addr32.d: Updated.
	* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-addr32.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise.

opcodes/

	PR gas/26237
	* i386-dis.c (OP_E_memory): Without base nor index registers,
	32-bit displacement to 64 bits.
2020-07-14 09:58:07 -07:00
Jan Beulich
bfbd943845 x86/Intel: debug registers are named DRn
%db<n> is an AT&T invention; the Intel documentation and MASM have only
ever specified DRn (in line with CRn and TRn). (In principle gas also
shouldn't accept the names in Intel mode, but at least for now I've kept
things as they are. Perhaps as a first step this should just be warned
about.)
2020-07-14 10:43:38 +02:00
Jan Beulich
7531c61332 x86: simplify decode of opcodes valid with (embedded) 66 prefix only
The only valid (embedded or explicit) prefix being the data size one
(which is a fairly common pattern), avoid going through prefix_table[].
Instead extend the "required prefix" logic to also handle PREFIX_DATA
alone in a table entry, now used to identify this case. This requires
moving the (adjusted) ->prefix_requirement logic ahead of the printing
of stray prefixes, as the latter needs to observe the new setting of
PREFIX_DATA in used_prefixes.

Also add PREFIX_OPCODE on related entries when previously there was
mistakenly no decode step through prefix_table[].
2020-07-14 10:33:40 +02:00
Jan Beulich
b24d668c07 x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel mode
The operands don't allow disambiguating the insn in 64-bit mode, and
hence suffixes need to be emitted not just in AT&T mode. Achieve this
by re-using %LQ while dropping PCMPESTR_Fixup().
2020-07-14 10:28:12 +02:00
Jan Beulich
9ab00b61a9 x86: don't disassemble MOVBE with two suffixes
MOVBE_Fixup() is entirely redundant with the S macro already used on the
mnemonics, leading to double suffixes in suffix-always mode. Drop the
function.
2020-07-14 10:26:51 +02:00
Jan Beulich
2875b28aa8 x86: avoid attaching suffix to register-only CRC32
Just like other insns with GPR operands, CRC32 with only register
operands should not get a suffix added unless in suffix-always mode.
Do away with CRC32_Fixup() altogether, using other more generic logic
instead.
2020-07-14 10:25:43 +02:00
Jan Beulich
e184e6110e x86-64: don't hide an empty but meaningless REX prefix
Unlike for non-zero values passed to USED_REX(), where rex_used gets
updated only when the respective bit was actually set in the encoding,
zero getting passed in is not further guarded, yet such a (potentially
"empty") REX prefix takes effect only when there are registers numbered
4 and up.
2020-07-14 10:24:26 +02:00
Jan Beulich
e8b5d5f971 x86: drop dead code from OP_IMREG()
There's only a very limited set of modes that this function gets invoked
with - avoid it being more generic than it needs to be. This may, down
the road, allow actually doing away with the function altogether.

This eliminates a first improperly used "USED_REX (0)".
2020-07-14 10:23:36 +02:00
Jan Beulich
38397794c9 x86-64: fold ILP32 test expectations
Various of the test expectations get adjusted later in this and a
subsequent series, so in order to avoid having to adjust more instances
than necessary fold respective test ILP32 expectations with their main
64-bit counterparts where they're identical anyway.
2020-07-14 10:22:45 +02:00
H.J. Lu
7a70531559 x86: Remove 32-bit sign extension in offset_in_range
When encoding a 32-bit offset, there is no need to sign-extend it to 64
bits since only the lower 32 bits are used.

	* config/tc-i386.c (offset_in_range): Remove 32-bit sign
	extension.
2020-07-13 10:32:15 -07:00
Nick Clifton
0a5c31d1ac Updated French translation for the gas/ and binutils/ sub-directories 2020-07-13 14:49:58 +01:00
Alan Modra
8884c29c0f gas DWARF2 test XPASSes
git commit af2b318648 introduced a number of XPASSes.  This removes
them.  (It also introduces a FAIL on ft32-elf but the comment in the
.d file didn't adequately explain why the failure should be expected.)

	* testsuite/gas/elf/dwarf2-7.d: Remove most xfails.
	* testsuite/gas/elf/dwarf2-12.d: Likewise.
	* testsuite/gas/elf/dwarf2-13.d: Likewise.
	* testsuite/gas/elf/dwarf2-14.d: Likewise.
2020-07-13 22:03:59 +09:30
H.J. Lu
a308b89de7 x86: Support GNU_PROPERTY_X86_FEATURE_2_TMM
Support GNU_PROPERTY_X86_FEATURE_2_TMM in

https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/1

 #define GNU_PROPERTY_X86_FEATURE_2_TMM      (1U << 10)

binutils/

	* readelf.c (decode_x86_feature_2): Handle
	GNU_PROPERTY_X86_FEATURE_2_TMM.

gas/

	* config/tc-i386.c (output_insn): Check i.xstate to set
	GNU_PROPERTY_X86_FEATURE_2_TMM.
	* testsuite/gas/i386/i386.exp: Run x86-64-property-7,
	x86-64-property-8 and x86-64-property-9.
	* testsuite/gas/i386/x86-64-property-7.d: New file.
	* testsuite/gas/i386/x86-64-property-7.s: Likewise.
	* testsuite/gas/i386/x86-64-property-8.d: Likewise.
	* testsuite/gas/i386/x86-64-property-8.s: Likewise.
	* testsuite/gas/i386/x86-64-property-9.d: Likewise.
	* testsuite/gas/i386/x86-64-property-9.s: Likewise.

include/

	* elf/common.h (GNU_PROPERTY_X86_FEATURE_2_TMM): New.
2020-07-11 04:04:20 -07:00
H.J. Lu
921eafeada x86: Extract extended states from instruction template
Extract extended states from operand types in instruction template.  Set
xstate_zmm for master register move.

	* config/tc-i386.c (_i386_insn): Remove has_regmmx, has_regxmm,
	has_regymm, has_regzmm and has_regtmm.  Add xstate.
	(md_assemble): Set i.xstate from operand types in instruction
	template.
	(build_modrm_byte): Updated.
	(output_insn): Check i.xstate.
	* testsuite/gas/i386/i386.exp: Run property-6 and
	x86-64-property-6.
	* testsuite/gas/i386/property-6.d: New file.
	* testsuite/gas/i386/property-6.s: Updated.
	* testsuite/gas/i386/x86-64-property-6.d: Likewise.
2020-07-10 08:43:47 -07:00
H.J. Lu
d249bf8670 gas/i386/property-5.d: Correct test name
* testsuite/gas/i386/property-5.d: Correct test name.
2020-07-10 05:58:42 -07:00
Lili Cui
260cd341da x86: Add support for Intel AMX instructions
gas/

	* doc/c-i386.texi: Document amx_int8, amx_bf16 and amx_tile.
	* config/tc-i386.c (i386_error): Add invalid_sib_address.
	(cpu_arch): Add .amx_int8, .amx_bf16 and .amx_tile.
	(cpu_noarch): Add noamx_int8, noamx_bf16 and noamx_tile.
	(match_simd_size): Add tmmword check.
	(operand_type_match): Add tmmword.
	(type_names): Add rTMM.
	(i386_error): Add invalid_tmm_register_set.
	(check_VecOperands): Handle invalid_sib_address and
	invalid_tmm_register_set.
	(match_template): Handle invalid_sib_address.
	(build_modrm_byte): Handle non-vector SIB and zmmword.
	(i386_index_check): Disallow RegIP for non-vector SIB.
	(check_register): Handle zmmword.
	* testsuite/gas/i386/i386.exp: Add AMX new tests.
	* testsuite/gas/i386/intel-regs.d: Add tmm.
	* testsuite/gas/i386/intel-regs.s: Add tmm.
	* testsuite/gas/i386/x86-64-amx-intel.d: New.
	* testsuite/gas/i386/x86-64-amx-inval.l: New.
	* testsuite/gas/i386/x86-64-amx-inval.s: New.
	* testsuite/gas/i386/x86-64-amx.d: New.
	* testsuite/gas/i386/x86-64-amx.s: New.
	* testsuite/gas/i386/x86-64-amx-bad.d: New.
	* testsuite/gas/i386/x86-64-amx-bad.s: New.

opcodes/

	* i386-dis.c (TMM): New.
	(EXtmm): Likewise.
	(VexTmm): Likewise.
	(MVexSIBMEM): Likewise.
	(tmm_mode): Likewise.
	(vex_sibmem_mode): Likewise.
	(REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
	(MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
	(MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
	(MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
	(MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
	(MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
	(MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
	(MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
	(MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
	(MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
	(MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
	(MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
	(RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
	(PREFIX_VEX_0F3849_X86_64): Likewise.
	(PREFIX_VEX_0F384B_X86_64): Likewise.
	(PREFIX_VEX_0F385C_X86_64): Likewise.
	(PREFIX_VEX_0F385E_X86_64): Likewise.
	(X86_64_VEX_0F3849): Likewise.
	(X86_64_VEX_0F384B): Likewise.
	(X86_64_VEX_0F385C): Likewise.
	(X86_64_VEX_0F385E): Likewise.
	(VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
	(VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
	(VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
	(VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
	(VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
	(VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
	(VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
	(VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
	(VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
	(VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
	(VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
	(VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
	(VEX_W_0F3849_X86_64_P_0): Likewise.
	(VEX_W_0F3849_X86_64_P_2): Likewise.
	(VEX_W_0F3849_X86_64_P_3): Likewise.
	(VEX_W_0F384B_X86_64_P_1): Likewise.
	(VEX_W_0F384B_X86_64_P_2): Likewise.
	(VEX_W_0F384B_X86_64_P_3): Likewise.
	(VEX_W_0F385C_X86_64_P_1): Likewise.
	(VEX_W_0F385E_X86_64_P_0): Likewise.
	(VEX_W_0F385E_X86_64_P_1): Likewise.
	(VEX_W_0F385E_X86_64_P_2): Likewise.
	(VEX_W_0F385E_X86_64_P_3): Likewise.
	(names_tmm): Likewise.
	(att_names_tmm): Likewise.
	(intel_operand_size): Handle void_mode.
	(OP_XMM): Handle tmm_mode.
	(OP_EX): Likewise.
	(OP_VEX): Likewise.
	* i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
	CpuAMX_BF16 and CpuAMX_TILE.
	(operand_type_shorthands): Add RegTMM.
	(operand_type_init): Likewise.
	(operand_types): Add Tmmword.
	(cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
	(cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
	* i386-opc.h (CpuAMX_INT8): New.
	(CpuAMX_BF16): Likewise.
	(CpuAMX_TILE): Likewise.
	(SIBMEM): Likewise.
	(Tmmword): Likewise.
	(i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
	(i386_opcode_modifier): Extend width of fields vexvvvv and sib.
	(i386_operand_type): Add tmmword.
	* i386-opc.tbl: Add AMX instructions.
	* i386-reg.tbl: Add AMX registers.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2020-07-10 05:18:34 -07:00
Tom de Vries
af2b318648 [readelf] Fix end_seq entry in -wL. Specifically stop the display of a line number and is_statement/has-view fields for the End of Sequence operator, as these have no meaning.
binutils* dwarf.c (display_debug_lines_decoded): Don't emit meaningless
	information in the end_sequence row.
	* testsuite/binutils-all/dw5.W: Update.
	* testsuite/binutils-all/objdump.WL: Update.

gas	* testsuite/gas/elf/dwarf2-11.d: Update expected output from
	readelf's line table decoding.
	* testsuite/gas/elf/dwarf2-12.d: Likewise.
	* testsuite/gas/elf/dwarf2-13.d: Likewise.
	* testsuite/gas/elf/dwarf2-14.d: Likewise.
	* testsuite/gas/elf/dwarf2-15.d: Likewise.
	* testsuite/gas/elf/dwarf2-16.d: Likewise.
	* testsuite/gas/elf/dwarf2-17.d: Likewise.
	* testsuite/gas/elf/dwarf2-18.d: Likewise.
	* testsuite/gas/elf/dwarf2-19.d: Likewise.
	* testsuite/gas/elf/dwarf2-5.d: Likewise.
	* testsuite/gas/elf/dwarf2-6.d: Likewise.
	* testsuite/gas/elf/dwarf2-7.d: Likewise.
2020-07-10 11:25:44 +01:00
H.J. Lu
39776b1117 x86: Properly set YMM/ZMM features
Since VEX/EVEX vector instructions will always update the full YMM/ZMM
registers, set YMM/ZMM features for VEX/EVEX vector instructions.

	* config/tc-i386.c (output_insn): Set YMM/ZMM features for
	VEX/EVEX vector instructions.
	* testsuite/gas/i386/property-4.d: New file.
	* testsuite/gas/i386/property-4.s: Likewise.
	* testsuite/gas/i386/property-5.d: Likewise.
	* testsuite/gas/i386/property-5.s: Likewise.
	* testsuite/gas/i386/x86-64-property-4.d: Likewise.
	* testsuite/gas/i386/x86-64-property-5.d: Likewise.
2020-07-09 10:33:43 -07:00
H.J. Lu
939b95c77b Linux/x86: Configure gas with --enable-x86-used-note by default
* configure.ac: Configure with --enable-x86-used-note by default
	for Linux/x86.
	* configure: Regenerated.
2020-07-09 08:29:25 -07:00
Alan Modra
fe49679d51 Remove powerpc PE support
Plus some leftover powerpc lynxos support.

bfd/
	* coff-ppc.c: Delete.
	* pe-ppc.c: Delete.
	* pei-ppc.c: Delete.
	* Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Remove PE PPC.
	* coffcode.h (coff_set_arch_mach_hook, coff_set_flags): Remove
	PPCMAGIC code.
	(coff_write_object_contents): Remove PPC_PE code.
	* config.bfd: Move powerpcle-pe to removed targets.
	* configure.ac: Remove powerpc PE entries.
	* libcoff-in.h (ppc_allocate_toc_section): Delete.
	(ppc_process_before_allocation): Delete.
	* peXXigen.c: Remove POWERPC_LE_PE code and comments.
	* targets.c: Remove powerpc PE vectors.
	* po/SRC-POTFILES.in: Regenerate.
	* libcoff.h: Regenerate.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
binutils/
	* dlltool.c: Remove powerpc PE support and comments.
	* configure.ac: Remove powerpc PE dlltool config.
	* configure: Regenerate.
gas/
	* config/obj-coff.h: Remove TE_PE support.
	* config/tc-ppc.c: Likewise.
	* config/tc-ppc.h: Likewise.
	* configure.tgt: Remove powerpc PE and powerpc lynxos.
	* testsuite/gas/cfi/cfi.exp (cfi-common-6): Remove powerpc PE
	condition.
	* testsuite/gas/macros/macros.exp: Don't xfail powerpc PE.
include/
	* coff/powerpc.h: Delete.
ld/
	* emulparams/ppcpe.sh: Delete.
	* scripttempl/ppcpe.sc: Delete.
	* emulparams/ppclynx.sh: Delete.
	* Makefile.am (ALL_EMULATION_SOURCES): Remove ppc PE and lynxos.
	* configure.tgt: Likewise.
	* emultempl/beos.em: Remove powerpc PE support.
	* emultempl/pe.em: Likewise.
	* po/BLD-POTFILES.in: Regenerate.
	* Makefile.in: Regenerate.
2020-07-09 22:58:16 +09:30
Jan Beulich
6384fd9e1d x86: FMA4 scalar insns ignore VEX.L
Just like other VEX-encoded scalar insns do.

Besides a testcase for this behavior also introduce one to verify that
XOP scalar insns don't honor -mavxscalar=256, as they don't ignore
XOP.L.
2020-07-08 11:19:26 +02:00
Claudiu Zissulescu
3128916d88 arc: Improve error messages when assembling
gas/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (find_opcode_match): Add error messages.
	* testsuite/gas/arc/add_s-err.s: Update test.
	* testsuite/gas/arc/asm-errors.err: Likewise.
	* testsuite/gas/arc/cpu-em-err.s: Likewise.
	* testsuite/gas/arc/hregs-err.s: Likewise.
	* testsuite/gas/arc/warn.s: Likewise.
2020-07-07 16:01:48 +03:00
Claudiu Zissulescu
f337259fbd arc: Update vector instructions.
Update vadd2, vadd4h, vmac2h, vmpy2h, vsub4h vector instructions
arguments to discriminate between double/single register operands.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (insert_rbd): New function.
	(RBD): Define.
	(RBDdup): Likewise.
	* arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
	instructions.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2020-07-07 16:01:48 +03:00
H.J. Lu
dbdba9b04d x86: Remove an incorrect AVX2 entry
The upper 16 vector registers were added by AVX512.

	PR gas/26212
	* doc/c-i386.texi: Remove an incorrect AVX2 entry.
2020-07-07 05:06:38 -07:00
Alan Modra
34e7979860 Use is_xcoff_format in gas testsuite
* testsuite/gas/all/gas.exp: Use is_xcoff_format.
	* testsuite/gas/ppc/ppc.exp: Likewise.
	* testsuite/gas/all/weakref1l.d: Likewise.
2020-07-07 18:26:34 +09:30
Nick Clifton
3c6e74ce51 Fix recent failures in the ARM assembler testsuite due to the correction of a spelling mistake.
* testsuite/gas/arm/cde-missing-fp.l: Fix spelling mistake in
	expected output.
2020-07-07 09:37:38 +01:00
Jan Beulich
e74d9fa9cf x86: AVX512 extract/insert insns need to honor EVEX.L'L
Just like their AVX counterparts do for VEX.L.

At this occasion also make EVEX.W have the same effect as VEX.W on the
printing of VPINSR{B,W}'s operands, bringing them also in sync with
VPEXTR{B,W}.
2020-07-06 13:41:27 +02:00
Jan Beulich
39e0f45682 x86: replace EXqScalarS by EXqVexScalarS
There's only a single user, that that one can do fine with the
alternative, as the "Vex" aspect of the other operand kind is meaningful
only on 3-operand insns.

While doing this I noticed that I didn't need to do the same adjustment
in the EVEX tables, and voilà - there was a bug, which gets fixed at the
same time (see the testsuite changes).
2020-07-06 13:35:38 +02:00
Nick Clifton
ddc73fa987 Fix spelling mistakes in some of the binutils sub-directories.
PR 26204
gas	* config/tc-arm.c: Fix spelling mistake.
	* config/tc-riscv.c: Likewise.
	* config/tc-z80.c: Likewise.
	* po/gas.pot: Regenerate.

ld	* lexsup.c: Fix spelling mistake.
	* po/ld.pot: Regenerate.

opcodes	* arc-dis.c: Fix spelling mistake.
	* po/opcodes.pot: Regenerate.
2020-07-06 10:54:36 +01:00
Nick Clifton
17550be7dd Updated translations for various binutils sub-directories 2020-07-06 10:43:35 +01:00
Nick Clifton
b19d852dcf Update version to 2.35.50 and regenerate files 2020-07-04 10:34:23 +01:00
Nick Clifton
b115b9fd3c Add markers for binutils 2.35 branch 2020-07-04 10:16:22 +01:00
Alan Modra
b657622c3e Re: Change readelf's display of symbol names
Fixes some fallout from git commit 0942c7ab94.

	PR 26028
gas/
	* testsuite/gas/ia64/unwind-ilp32.d: Add -T to readelf options.
gold/
	* testsuite/Makefile.am (file_in_many_sections.stdout): Add -W
	to readelf options.
	* testsuite/Makefile.in: Regenerate.
ld/
	* testsuite/ld-arm/arm-elf.exp (vxworks1): Pass --wide to readelf
	when dumping relocs.
	* testsuite/ld-i386/i386.exp (vxworks1): Likewise.
	* testsuite/ld-sh/sh-vxworks.exp (vxworks1): Likewise.
	* testsuite/ld-sparc/sparc.exp (vxworks1): Likewise.
	* testsuite/ld-arm/vxworks1.rd: Adjust to suit.
	* testsuite/ld-i386/vxworks1.rd: Adjust.
	* testsuite/ld-sh/vxworks1.rd: Adjust.
	* testsuite/ld-sparc/vxworks1.rd: Adjust.
2020-07-03 17:15:16 +09:30
H.J. Lu
c2ecccb33c x86: Add SwapSources
We check register-only source operand to decide if two source operands of
VEX encoded instructions should be swapped.  But source operands in AMX
instructions with two source operands swapped are all register-only
operand.  Add SwapSources to indicate two source operands should be
swapped.

gas/

	* config/tc-i386.c (build_modrm_byte): Check vexswapsources to
	swap two source operands.

opcodes/

	* i386-gen.c (opcode_modifiers): Add VexSwapSources.
	* i386-opc.h (VexSwapSources): New.
	(i386_opcode_modifier): Add vexswapsources.
	* i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
	with two source operands swapped.
	* i386-tbl.h: Regenerated.
2020-07-02 08:46:48 -07:00
Nick Clifton
f436f38e7d Skip fill-1 gas test for MeP targets.
* testsuite/gas/all/fill-1.d: Skip for MeP targets.
2020-07-02 14:08:16 +01:00
Alex Coplan
f405494f21 aarch64: Fix segfault on unicode symbols
This patch fixes a segfault which occurs when the AArch64 backend parses
a symbol operand that begins with a register name and ends with a
unicode byte (byte value > 127).

For example, the following input causes the crash:

x0é: udf x0é

gas/ChangeLog:

2020-07-02  Alex Coplan  <alex.coplan@arm.com>

	* config/tc-aarch64.c (reg_name_p): Fix cast so that we don't
	segfault on negative chars.
	* testsuite/gas/aarch64/reglike-label-unicode-segv.d: New test.
	* testsuite/gas/aarch64/reglike-label-unicode-segv.s: Input.
2020-07-02 13:53:07 +01:00
Nick Clifton
0942c7ab94 Change readelf's display of symbol names (when not in --wide mode) so that if they are going to be truncated then "[...]" is displayed at the end. Add a comment line option to disable this enhancement and restore the old behaviour.
PR 26028
binutils* readelf.c (print_symbol): Handle truncation of symbol names.
	(options): Add -T/--silent-truncation option.
	(parse_args): Handle the option.
	(print_dynamic_symbol): Correct calculation of width available to
	display symbol name.
	* doc/binutils.texi: Document the -T option to readelf.
	* NEWS: Mention the new feature.

gas	* testsuite/gas/ia64/group-2.d: Add -T option to readelf
	command line.
	* testsuite/gas/ia64/unwind.d: Likewise.
	* testsuite/gas/mmix/bspec-1.d: Likewise.
	* testsuite/gas/mmix/bspec-2.d: Likewise.
	* testsuite/gas/mmix/comment-1.d: Likewise.
	* testsuite/gas/tic6x/scomm-directive-4.d: Likewise.

ld	* testsuite/ld-powerpc/powerpc.exp: Add -T option to readelf
	command line when running some tests.
	* testsuite/ld-arm/arm-elf.exp: Likewise.
	* testsuite/ld-mips-elf/mips-elf.exp: Likewise.
	* testsuite/ld-mmix/local1.d: Likewise.
	* testsuite/ld-mmix/local3.d: Likewise.
	* testsuite/ld-mmix/local5.d: Likewise.
	* testsuite/ld-mmix/local7.d: Likewise.
	* testsuite/ld-powerpc/powerpc.exp: Likewise.
2020-07-02 11:30:52 +01:00
Alan Modra
3443489c65 obsolete xc16x
The xc16x md_apply_fix code is just so broken that in my opinion the
target should never have been accepted, and from a quick look at
commit logs for the target it appears that no one has ever contributed
fixes for anything.  This target has just been a 14 year burden on
global binutils and cgen maintainers.  That's not how free software is
supposed to work.

bfd/
	* config.bfd: Obsolete xc16x.
gas/
	* config/tc-xc16x.c (md_apply_fix): Add FIXME.
2020-07-01 10:06:43 +09:30
Alan Modra
054b336d9a gas eqv-dot test fails
* testsuite/gas/all/eqv-dot.d: xfail targets that set linkrelax
	in data sections, and mep.
2020-07-01 10:06:40 +09:30
H.J. Lu
bbd19b19e4 Remove x86 NaCl target support
NaCl has been deprecated:

https://developer.chrome.com/native-client/migration

and NaCl will completely disappear in 2021:

https://lists.llvm.org/pipermail/llvm-dev/2020-April/141107.html

Remove x86 NaCl target support from bfd, binutils, gas and ld.

bfd/

	* archures.c (bfd_mach_i386_nacl): Removed.
	(bfd_mach_i386_i386_nacl): Likewise.
	(bfd_mach_x86_64_nacl): Likewise.
	(bfd_mach_x64_32_nacl): Likewise.
	* config.bfd: Remove *-*-nacl* targets.
	* configure.ac: Remove x86 NaCl target vectors.
	* cpu-i386.c (bfd_arch_i386_onebyte_nop_fill): Removed.
	(bfd_x64_32_nacl_arch): Likewise.
	(bfd_x86_64_nacl_arch): Likewise.
	(bfd_i386_nacl_arch): Likewise.
	(bfd_x64_32_arch_intel_syntax): Updated.
	* elf32-i386.c: Don't include "elf-nacl.h".
	(elf_i386_nacl_plt): Removed.
	(elf_i386_nacl_plt0_entry): Likewise.
	(elf_i386_nacl_plt_entry): Likewise.
	(elf_i386_nacl_pic_plt0_entry): Likewise.
	(elf_i386_nacl_pic_plt_entry): Likewise.
	(elf_i386_nacl_eh_frame_plt): Likewise.
	(elf_i386_nacl_plt): Likewise.
	(elf32_i386_nacl_elf_object_p): Likewise.
	(elf_i386_get_synthetic_symtab): Updated.
	(elf_i386_link_setup_gnu_properties): Likewise.
	* elf64-x86-64.c: Don't include "elf-nacl.h".
	(elf_x86_64_nacl_plt): Removed.
	(elf64_x86_64_nacl_elf_object_p): Likewise.
	(elf_x86_64_nacl_plt0_entry): Likewise.
	(elf_x86_64_nacl_plt_entry): Likewise.
	(elf_x86_64_nacl_eh_frame_plt): Likewise.
	(elf_x86_64_nacl_plt): Likewise.
	(elf32_x86_64_nacl_elf_object_p): Likewise.
	(elf_x86_64_get_synthetic_symtab): Updated.
	(elf_x86_64_link_setup_gnu_properties): Likewise.
	* elfxx-x86.c (_bfd_x86_elf_link_setup_gnu_properties): Likewise.
	* targets.c: Remove x86 NaCl target vectors.
	* bfd-in2.h: Regenerated.
	* configure: Likewise.

binutils/

	* NEWS: Mention x86 NaCl target support removal.
	* dwarf.c (init_dwarf_regnames_by_bfd_arch_and_mach): Remove
	x86 NaCl target support.
	* testsuite/binutils-all/elfedit-1.d: Likewise.
	* testsuite/binutils-all/i386/i386.exp: Likewise.
	* testsuite/binutils-all/x86-64/objects.exp: Likewise.
	* testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494a.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494b-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494b.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494c.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494d.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494e.d: Likewise.
	* testsuite/binutils-all/x86-64/x86-64.exp: Likewise.

gas/

	* NEWS: Mention x86 NaCl target support removal.
	* config/tc-i386.c: Remove x86 NaCl target support.
	* config/tc-i386.h: Likewise.
	* configure.tgt: Likewise.
	* testsuite/gas/i386/i386.exp: Likewise.
	* testsuite/gas/i386/iamcu-1.d: Likewise.
	* testsuite/gas/i386/iamcu-2.d: Likewise.
	* testsuite/gas/i386/iamcu-3.d: Likewise.
	* testsuite/gas/i386/iamcu-4.d: Likewise.
	* testsuite/gas/i386/iamcu-5.d: Likewise.
	* testsuite/gas/i386/k1om.d: Likewise.
	* testsuite/gas/i386/l1om.d: Likewise.

ld/

	* Makefile.am (ALL_EMULATION_SOURCES): Remove eelf_i386_nacl.c,
	eelf32_x86_64_nacl.c, eelf_x86_64_nacl.c.
	Remove x86 NaCl dep files.
	* NEWS: Mention x86 NaCl target support removal.
	* configure.tgt: Remove x86 NaCl target support.
	* testsuite/ld-elf/binutils.exp: Likewise.
	* testsuite/ld-elf/elf.exp: Likewise.
	* testsuite/ld-elfvers/vers.exp: Likewise.
	* testsuite/ld-i386/align-branch-1.d: Likewise.
	* testsuite/ld-i386/export-class.exp: Likewise.
	* testsuite/ld-i386/i386.exp: Likewise.
	* testsuite/ld-i386/load1.d: Likewise.
	* testsuite/ld-i386/pie1.d: Likewise.
	* testsuite/ld-i386/pr12570a.d: Likewise.
	* testsuite/ld-i386/pr12570b.d: Likewise.
	* testsuite/ld-i386/pr19636-1d.d: Likewise.
	* testsuite/ld-i386/pr19636-1l.d: Likewise.
	* testsuite/ld-i386/pr19636-2c.d: Likewise.
	* testsuite/ld-i386/pr19636-2d.d: Likewise.
	* testsuite/ld-i386/pr19636-2e.d: Likewise.
	* testsuite/ld-i386/pr20244-1a.d: Likewise.
	* testsuite/ld-i386/pr20244-1b.d: Likewise.
	* testsuite/ld-i386/pr20244-2a.d: Likewise.
	* testsuite/ld-i386/pr20244-2b.d: Likewise.
	* testsuite/ld-i386/pr20244-2c.d: Likewise.
	* testsuite/ld-i386/pr20244-4a.d: Likewise.
	* testsuite/ld-i386/pr20244-4b.d: Likewise.
	* testsuite/ld-i386/pr21884.d: Likewise.
	* testsuite/ld-ifunc/binutils.exp: Likewise.
	* testsuite/ld-ifunc/ifunc-10-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-10-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-11-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-11-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-12-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-12-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-13-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-13-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-14a-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-14a-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-14b-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-14b-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-14c-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-14c-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-14d-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-14d-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-14e-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-14e-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-14f-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-14f-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-15-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-15-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-16-i386-now.d: Likewise.
	* testsuite/ld-ifunc/ifunc-16-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-16-x86-64-now.d: Likewise.
	* testsuite/ld-ifunc/ifunc-16-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-17a-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-17a-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-17b-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-17b-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-18a-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-18a-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-18b-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-18b-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-19a-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-19a-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-19b-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-19b-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-2-i386-now.d: Likewise.
	* testsuite/ld-ifunc/ifunc-2-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-2-local-i386-now.d: Likewise.
	* testsuite/ld-ifunc/ifunc-2-local-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-2-local-x86-64-now.d: Likewise.
	* testsuite/ld-ifunc/ifunc-2-local-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-2-x86-64-now.d: Likewise.
	* testsuite/ld-ifunc/ifunc-2-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-20-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-20-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-21-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-22-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-5a-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-5a-local-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-5a-local-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-5a-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-5b-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-5b-local-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-5b-local-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-5b-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-5r-local-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-6a-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-6a-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-6b-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-6b-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-7a-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-7a-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-7b-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-7b-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-8-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-8-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-9-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-9-x86-64.d: Likewise.
	* testsuite/ld-ifunc/pr17154-i386-now.d: Likewise.
	* testsuite/ld-ifunc/pr17154-i386.d: Likewise.
	* testsuite/ld-ifunc/pr17154-x86-64-now.d: Likewise.
	* testsuite/ld-ifunc/pr17154-x86-64.d: Likewise.
	* testsuite/ld-plugin/lto.exp: Likewise.
	* testsuite/ld-x86-64/align-branch-1.d: Likewise.
	* testsuite/ld-x86-64/dwarfreloc.exp: Likewise.
	* testsuite/ld-x86-64/line.exp: Likewise.
	* testsuite/ld-x86-64/load1a.d: Likewise.
	* testsuite/ld-x86-64/load1b.d: Likewise.
	* testsuite/ld-x86-64/load1c.d: Likewise.
	* testsuite/ld-x86-64/load1d.d: Likewise.
	* testsuite/ld-x86-64/pie3.d: Likewise.
	* testsuite/ld-x86-64/pr18160.d: Likewise.
	* testsuite/ld-x86-64/pr19013-x32.d: Likewise.
	* testsuite/ld-x86-64/pr19013.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2d.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2l.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1b.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1d.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1f.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1h.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1j.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1l.d: Likewise.
	* testsuite/ld-x86-64/pr21884.d: Likewise.
	* testsuite/ld-x86-64/pr22393-3a.rd: Likewise.
	* testsuite/ld-x86-64/pr22393-3b.rd: Likewise.
	* testsuite/ld-x86-64/tlsgd10.dd: Likewise.
	* testsuite/ld-x86-64/tlsgd5.dd: Likewise.
	* testsuite/ld-x86-64/tlsgd8.dd: Likewise.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
	* emulparams/elf32_x86_64_nacl.sh: Removed.
	* emulparams/elf_i386_nacl.sh: Likewise.
	* emulparams/elf_x86_64_nacl.sh: Likewise.
	* testsuite/ld-i386/emit-relocs-nacl.rd: Likewise.
	* testsuite/ld-i386/load1-nacl.d: Likewise.
	* testsuite/ld-i386/pie1-nacl.d: Likewise.
	* testsuite/ld-i386/plt-nacl.pd: Likewise.
	* testsuite/ld-i386/plt-pic-nacl.pd: Likewise.
	* testsuite/ld-i386/pr17709-nacl.rd: Likewise.
	* testsuite/ld-i386/pr19636-1d-nacl.d: Likewise.
	* testsuite/ld-i386/pr19636-2c-nacl.d: Likewise.
	* testsuite/ld-i386/pr19636-2d-nacl.d: Likewise.
	* testsuite/ld-i386/pr19636-2e-nacl.d: Likewise.
	* testsuite/ld-i386/pr19827-nacl.rd: Likewise.
	* testsuite/ld-i386/pr21884-nacl.d: Likewise.
	* testsuite/ld-i386/pr21884-nacl.t: Likewise.
	* testsuite/ld-i386/tlsbin-nacl.rd: Likewise.
	* testsuite/ld-i386/tlsbin2-nacl.rd: Likewise.
	* testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise.
	* testsuite/ld-i386/tlsdesc-nacl.rd: Likewise.
	* testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise.
	* testsuite/ld-i386/tlsnopic-nacl.rd: Likewise.
	* testsuite/ld-i386/tlspic-nacl.rd: Likewise.
	* testsuite/ld-i386/tlspic2-nacl.rd: Likewise.
	* testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise.
	* testsuite/ld-x86-64/load1a-nacl.d: Likewise.
	* testsuite/ld-x86-64/load1b-nacl.d: Likewise.
	* testsuite/ld-x86-64/load1c-nacl.d: Likewise.
	* testsuite/ld-x86-64/load1d-nacl.d: Likewise.
	* testsuite/ld-x86-64/pie3-nacl.d: Likewise.
	* testsuite/ld-x86-64/plt-nacl.pd: Likewise.
	* testsuite/ld-x86-64/pr17709-nacl.rd: Likewise.
	* testsuite/ld-x86-64/pr19013-nacl.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2d-nacl.d: Likewise.
	* testsuite/ld-x86-64/pr19827-nacl.rd: Likewise.
	* testsuite/ld-x86-64/pr21884-nacl.d: Likewise.
	* testsuite/ld-x86-64/pr21884-nacl.t: Likewise.
	* testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise.
	* testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise.
	* testsuite/ld-x86-64/tlsbin2-nacl.rd: Likewise.
	* testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise.
	* testsuite/ld-x86-64/tlsdesc-nacl.pd: Likewise.
	* testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise.
	* testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise.
	* testsuite/ld-x86-64/tlspic-nacl.rd: Likewise.
	* testsuite/ld-x86-64/tlspic2-nacl.rd: Likewise.
	* Makefile.in: Regenerated.
	* po/BLD-POTFILES.in: Likewise.
2020-06-30 08:56:14 -07:00
Nelson Chu
08ccfccf0e RISC-V: Support debug and float CSR as the unprivileged ones.
The unprivileged CSR should be controlled by other specific specs rather
than the privileged spec.  For example, the debug CSR should be controlled
by the debug spec, and the float CSR should be controlled by the float
spec.  User may use assembler options to choose what the debug and other
specs they want, or may encode the versions of specs into the architecture
string directly.  Since we haven't decided which one is better, we set the
defined and aborted versions of unprivileged CSR to PRIV_SPEC_CLASS_NONE
in the include/opcode/riscv-opc.h, to tell assembler don't check priv spec
versions for them.  However, these PRIV_SPEC_CLASS_NONE will be changed
to FLOAT_SPEC_CLASS_* and DEBUG_SPEC_CLASS_* in the future.

	gas/
	* config/tc-riscv.c (riscv_csr_class_check): Removed.  Move the
	checking into riscv_csr_address.
	(riscv_csr_version_check): Likewise.
	(riscv_csr_address): New function.  Return the suitable CSR address
	after checking the ISA dependency and versions.  Issue warnings	if
	we find any conflict and -mcsr-check is set.  CSR_CLASS_F and
	CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
	priv spec versions for them.
	(reg_csr_lookup_internal): Call riscv_csr_address to find the
	suitable CSR address.

	* testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-fext.l:  We don't care the
	priv spec warnings here.  These warnings are added by accident.
	Remove them and only focus on the ISA dependency warnings.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
	dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
	than the privileged ones.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* testsuite/gas/riscv/priv-reg.s: Likewise.  Add missing debug CSR.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.

	include/
	* opcode/riscv-opc.h: Support the unprivileged CSR.  The versions
	of the unprivileged CSR should be PRIV_SPEC_CLASS_NONE for now.
	* opcode/riscv.h (enum riscv_csr_class): Add CSR_CLASS_DEBUG.

	opcodes/
	* riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
	unprivileged CSR can also be initialized.
2020-06-30 09:54:55 +08:00
H.J. Lu
8c190ce038 x86: Support VEX base opcode length > 1
Intel AMX instructions with 8-bit immediate opcode extension without
operands:

tilerelease, 0, 0x49c0, None, 2, CpuAMX_TILE|Cpu64, Vex|VexOpcode=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

Update build_vex_prefix to support VEX base opcode length > 1.

	* tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
	(md_assemble): Don't process ImmExt without operands.
2020-06-29 06:28:46 -07:00
Hans-Peter Nilsson
4e394b28e3 gas/testsuite: test-case for PR25331 (mmix reloc fixup bug)
The bug manifested "only" for a 64-bit host:

pr25331.c: Assembler messages:
pr25331.c:430: Error: internal error: fixup not contained within frag
failed with: <pr25331.c: Assembler messages:
pr25331.c:430: Error: internal error: fixup not contained within frag>, no expected output
FAIL: gas/mmix/pr25331

gas:
	PR gas/25331
	* testsuite/gas/mmix/pr25331.d, testsuite/gas/mmix/pr25331.s: New test.
2020-06-29 05:38:26 +02:00
Hans-Peter Nilsson
b20e7614da gas: Fix mmix fixups and TC_FX_SIZE_SLACK, PR25331
Finally; sorry for the delay.  There were a few false starts, where I
misinterpreted the error-messages and the comment that Alan added:
it's not the fix size that's too large (and the frag too small), it's
stating the wrong size of what will be "fixed up" - that of the actual
target value, not the size of the field that needs to be adjusted.
Comments added for clarity.

Test-suite committed separately.

gas:
	PR gas/25331
	* config/tc-mmix.c (md_assemble) <fixup for
	BFD_RELOC_MMIX_BASE_PLUS_OFFSET>: This fixup affects 1 byte, not 8.
	Also, set its fx_no_overflow.
	(md_convert_frag) <case ENCODE_RELAX (STATE_PUSHJSTUB, STATE_ZERO)>:
	Similarly this fixup affects 4 bytes, not 8 and needs its
	fx_no_overflow set.
	* config/tc-mmix.h (TC_FX_SIZE_SLACK): Don't define.
2020-06-29 05:32:02 +02:00
Alan Modra
279edac53d C++ comments
binutils isn't c99 (yet).  This replaces or removes some C++ style
comments.

bfd/
	* arc-got.h: Use C style comments.
	* coff-z80.c: Likewise.
	* elf32-csky.c: Likewise.
	* peXXigen.c: Likewise.
	* elf32-m32c.c (m32c_elf_relax_delete_bytes): Remove commented out
	code.
binutils/
	* dwarf.c: Use C style comments.
	* resrc.c: Likewise.
gas/
	* config/tc-s12z.c: Use C style comments.
	* config/tc-z80.c: Likewise.
	* config/tc-xtensa.c (emit_ld_r_n): Remove commented out code.
include/
	* coff/internal.h: Use C style comments.
	* coff/pe.h: Likewise.
	* elf/ppc64.h: Likewise.
opcodes/
	* arm-dis.c: Use C style comments.
	* cr16-opc.c: Likewise.
	* ft32-dis.c: Likewise.
	* moxie-opc.c: Likewise.
	* tic54x-dis.c: Likewise.
	* s12z-opc.c: Remove useless comment.
	* xgate-dis.c: Likewise.
2020-06-29 10:07:56 +09:30
H.J. Lu
b6cd5d100a x86: Process ImmExt without operands
To support Intel AMX instructions with 8-bit immediate opcode extension,
but without operands:

tilerelease, 0, 0x49, 0xc0, 1, CpuAMX_TILE|Cpu64, Vex|VexOpcode=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }

process ImmExt without operands.

	* config/tc-i386.c (md_assemble): Process ImmExt without
	operands.
2020-06-26 10:25:12 -07:00
H.J. Lu
63112cd67b x86: Rename VecSIB to SIB for Intel AMX
Rename VecSIB to SIB to support Intel Advanced Matrix Extensions which
introduces instructions with a mandatory SIB byte which isn't a vector
SIB (VSIB).

gas/

	* config/tc-i386.c (check_VecOperands): Replace vecsib with sib.
	Replace VecSIB128, VecSIB256 and VecSIB512 with VECSIB128,
	VECSIB256 and VECSIB512, respectively.
	(build_modrm_byte): Replace vecsib with sib.

opcodes/

	* i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
	(VecSIB128): Renamed to ...
	(VECSIB128): This.
	(VecSIB256): Renamed to ...
	(VECSIB256): This.
	(VecSIB512): Renamed to ...
	(VECSIB512): This.
	(VecSIB): Renamed to ...
	(SIB): This.
	(i386_opcode_modifier): Replace vecsib with sib.
	* i386-opc.tbl (VexSIB128): New.
	(VecSIB256): Likewise.
	(VecSIB512): Likewise.
	Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VexSIB128, VecSIB256
	and VecSIB512, respectively.
2020-06-26 08:24:44 -07:00
Jan Beulich
2a1bb84c67 x86: fix processing of -M disassembler option
Multiple -M options can be specified in any order. Therefore stright
assignment to fields affected needs to be avoided, such that earlier
options' effects won't be discarded. This was in particular a problem
for -Msuffix followed by certain of the other sub-options.

While updating documentation, take the liberty and also drop the
redundant mentioning of being able to comma-separate multiple options.
2020-06-26 16:42:55 +02:00
Pat Bernardi
85f7484a3a m68k: tag floating-point ABI used
This patch adds GNU attribute support to m68k and utilises it to tag the
floating-point calling convention used (hard-float or soft-float). It enables
the linker to ensure linked objects use a consistent floating-point ABI and
allows tools like GDB to infer the ABI used from the ELF file. It is based on
similar work done for PowerPC.

bfd/
	* elf32-m68k.c (m68k_elf_merge_obj_attributes): New function.
	(elf32_m68k_merge_private_bfd_data): Merge GNU attributes.
binutils/
	* readelf.c (display_m68k_gnu_attribute): New function.
	(process_arch_specific): Call display_m68k_gnu_attribute for EM_68K.
gas/
	* config/tc-m68k.c (m68k_elf_gnu_attribute): New function.
	(md_pseudo_table): Handle "gnu_attribute".
	* doc/as.texi: Document GNU attribute for M68K.
include/
	* elf/m68k.h: Add enum for GNU object attribute with floating point
	tag name and values.
ld/
	* testsuite/ld-m68k/attr-gnu-4-0.s: New file.
	* testsuite/ld-m68k/attr-gnu-4-1.s: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-2.s: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-00.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-01.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-02.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-10.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-11.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-12.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-20.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-21.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-22.d: Likewise.
	* testsuite/ld-m68k/m68k.exp: Run the new tests.
2020-06-26 14:42:19 +09:30
Nick Clifton
b59d128a11 Stop the assembler from generating R_ARM_THM_JMP11 relocations as these are not supported by the kernel.
PR 26141
	* config/tc-arm.c (arm_force_relocation): Force resolution of
	BFD_RELOC_THUMB_PCREL_BRANCH12 relocations.
	* testsuite/gas/arm/plt-1.d: Adjust expected disassembly.
2020-06-25 11:11:51 +01:00
Jan Beulich
c423d21a43 x86: move ImmExt processing
With abuses of ImmExt gone, all templates using it have operands. Move
its main invocation into process_operands(), matching its secondary one
for the SSE2AVX case.
2020-06-25 09:30:09 +02:00
Jan Beulich
8bbb3ad806 x86: operand sizing prefixes can disambiguate insns
Use of an explicit data size or REX.W prefix is sufficient indication of
the intended operation when operand size can't be derived from suffix or
register operands. Avoid the ambiguity warning and make in particular
immediate handling (sizing) cope with explicitly specified prefixes.

Extending/reusing the noreg16 test made me notice a few cases of
unintentional 32-bit addressing, which gets corrected at the same time.
2020-06-25 09:29:29 +02:00
Jan Beulich
589958d6ff x86: fix SYSRET disassembly, improve {,V}CVTSI2S{S,D} and PTWRITE
SYSRET can't use the same macro as IRET, since there's no 16-bit operand
size form of it. Re-use LQ for it instead.

Doing so made obvious that outside of 64-bit mode {,V}CVTSI2S{S,D} and
PTWRITE should have an 'l' suffix printed only in suffix-always mode.
2020-06-25 09:27:21 +02:00
Jan Beulich
0b9404fd37 x86-64: REX prefix is invalid with VEX etc
Just like for the data size prefix (see commit 7a8655d2bb ["x86: don't
abort() upon DATA16 prefix on (E)VEX encoded insn"]), any form of REX
prefix is invalid with VEX/XOP/EVEX.
2020-06-25 09:26:28 +02:00
Jan Beulich
a5aeccd9d3 x86-64: honor REX prefixes for SSE2AVX
Legacy encoded insns do so, and their automatic conversion to AVX ones
ought to produce functionally identical code. Therefore explicit REX
prefixes cannot simply be ignored. This is in particular relevant
because at least PCMPESTR{I,M}'s 64-bit forms couldn't be expressed in
older gas by other than using a REX64 prefix.
2020-06-25 09:25:52 +02:00
Jan Beulich
40d231b4fb x86: also refuse data size prefix on SIMD insns
The data size prefix alters the meaning of legacy encoded SIMD insns,
and hence shouldn't be accepted there. Use of it also leads to
inconsistencies in SSE2AVX mode. Don't match insns with data size prefix
against SSE2AVX templates.
2020-06-25 09:25:12 +02:00
Jan Beulich
11abe42647 x86: drop stray assignment from build_evex_prefix()
Unlike in build_vex_prefix() this is not needed here.
2020-06-25 09:24:23 +02:00
Nelson Chu
1a79004f61 RISC-V: Generate ELF priv attributes if priv instruction are explicited used.
We should generate the ELF priv attributes only if,

1. The priv attributes are already set in the assembly file.
2. The CSR are explicited used.
3. The privileged instruction are explicited used.

* There are four privileged instruction defined in the v1.11 priv spec:
`mret`, `sret`, `wfi` and `sfence.vma`.

* `sfence.vm` is dropped in the v1.10 priv spec.

* `uret` is actually a N-ext instruction.  So it is better to regard it as
an user instruction rather than the priv instruction.

* `hret` is used to return from traps in H-mode.  H-mode is removed since
the v1.10 priv spec, but probably be added in the new hypervisor spec.
Therefore, `hret` should be controlled by the hypervisor spec rather than
priv spec in the future.

* `dret` is a debug instruction.  We should record the debug spec versions
once it is explicited used in the future.

	gas/
	* config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to
	explicit_priv_attr.  It used to indicate CSR or priv instructions are
	explictly used.
	(riscv_is_priv_insn): Return True if it is a privileged instruction.
	(riscv_ip): Call riscv_is_priv_insn to check whether the instruction
	is privileged or not.  If it is, then set explicit_priv_attr to TRUE.
	(riscv_write_out_attrs): Clarification of when to generate the elf
	priv spec attributes.

	* testsuite/gas/riscv/attribute-11.s: Add comments.
	* testsuite/gas/riscv/attribute-14.s: New testcase.  Use symbol
	`priv_insn_<n>` to decide which priv instruction is expected to used.
	(<n> is a to g.)
	* testsuite/gas/riscv/attribute-14a.d: Likewise.
	* testsuite/gas/riscv/attribute-14b.d: Likewise.
	* testsuite/gas/riscv/attribute-14c.d: Likewise.
	* testsuite/gas/riscv/attribute-14d.d: Likewise.
	* testsuite/gas/riscv/attribute-14e.d: Likewise.
2020-06-23 09:38:12 +08:00
Nelson Chu
39ff0b8123 RISC-V: Report warning when linking the objects with different priv specs.
We do know some conflicts among different privileged specs.  For linker,
the safest approach is that don't allow the object linked with others which
may cause conflicts.  But this may cause inconvenience since not all objects
with conflicting priv specs are linked will cause problems.  But it is hard
to know the detailed conflict cases for linker, so we probably need a option
to tell linker that we do know there are no conflicts, or we are willing to
take risks to link the objects with conflicted priv specs.  But the option
is still under discussion.

Therefore, we can report warnings rather than errors when linking the objects
with conflicted priv specs.  This not only makes the linker more flexible,
but also warns people that the conflicts may happen.  We also need to update
the output priv spec version once the input priv spec is newer.

	bfd/
	* elfxx-riscv.c (struct priv_spec_t priv_specs[]): Move them from
	opcodes/riscv-opc.c to bfd/elfxx-riscv.c, since we need it in linker.
	(riscv_get_priv_spec_class): Likewise.
	(riscv_get_priv_spec_name): Likewise.
	(riscv_get_priv_spec_class_from_numbers): New function, convert
	the version numbers into string, then call riscv_get_priv_spec_class
	to get the priv spec class.
	* elfxx-riscv.h (riscv_get_priv_spec_class): Move forward declaration
	from include/opcode/riscv.h to bfd/elfxx-riscv.h.
	(riscv_get_priv_spec_name): Likewise.
	(riscv_get_priv_spec_class_from_numbers): New forward declaration.
	(opcode/riscv.h): Include it in the header rather than elfxx-riscv.c.
	* elfnn-riscv.c (riscv_merge_attributes):  Get the priv spec classes
	of input and output objects form their priv spec attributes by
	riscv_get_priv_spec_class_from_numbers.  Report warning rather than
	errors when linking objects with differnet priv spec versions.  We do
	know v1.9.1 may have conflicts to other versions, so report the
	warning, too.  After that, update the output priv spec version to the
	newest one so far.

	gas/
	* config/tc-riscv.c (buf_size, buf): Remove the unused variables.
	(riscv_set_default_priv_spec): Get the priv spec version from the
	priv spec attributes by riscv_get_priv_spec_class_from_numbers.

	include/
	* opcode/riscv.h (riscv_get_priv_spec_class): Move the function
	forward declarations to bfd/elfxx-riscv.h.
	(riscv_get_priv_spec_name): Likewise.

	opcodes/
	* riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
	* riscv-dis.c: Include elfxx-riscv.h.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Updated.
2020-06-22 10:01:14 +08:00
Alan Modra
e2201c2a57 SH gas configure and ld tests
All current SH gas targets use BFD.  sh-coff was incorrectly reported
as unsupported.

gas/
	* configure.tgt: Set bfd_gas for all SH targets.
ld/
	* testsuite/ld-sh/sh.exp: Don't run relax tests for non-ELF.
	Fail when ld_assemble fails.  Use elseif to reduce indentation.
2020-06-20 10:56:39 +09:30