Commit Graph

3514 Commits

Author SHA1 Message Date
H.J. Lu
4b5aaf5f69 x86: Accept Intel64 only instruction by default
Commit d835a58baa disabled sysenter/sysenter in 64-bit mode by
default.  By default, assembler should accept common, Intel64 only
and AMD64 ISAs since there are no conflicts.

gas/

	PR gas/25516
	* config/tc-i386.c (intel64): Renamed to ...
	(isa64): This.
	(match_template): Accept Intel64 only instruction by default.
	(i386_displacement): Updated.
	(md_parse_option): Updated.
	* c-i386.texi: Update -mamd64/-mintel64 documentation.
	* testsuite/gas/i386/i386.exp: Run x86-64-sysenter.  Pass
	-mamd64 to x86-64-sysenter-amd.
	* testsuite/gas/i386/x86-64-sysenter.d: New file.

opcodes/

	PR gas/25516
	* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
	with ISA64.
	* i386-opc.h (AMD64): Removed.
	(Intel64): Likewose.
	(AMD64): New.
	(INTEL64): Likewise.
	(INTEL64ONLY): Likewise.
	(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
	* i386-opc.tbl (Amd64): New.
	(Intel64): Likewise.
	(Intel64Only): Likewise.
	Replace AMD64 with Amd64.  Update sysenter/sysenter with
	Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
	* i386-tbl.h: Regenerated.
2020-02-10 08:37:36 -08:00
Sergey Belyashov
9fc0b501af Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add DWARF debug info support to the Z80 assembler.
PR 25469
bfd	* archures.c: Add GBZ80 and Z80N machine values.
	* reloc.c: Add BFD_RELOC_Z80_16_BE.
	* coff-z80.c: Add support for new reloc.
	* coffcode.h: Add support for new machine values.
	* cpu-z80.c: Add support for new machine names.
	* elf32-z80.c: Add support for new reloc.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

binutils* readelf.c (get_machine_flags): Add support for Z80N machine
	number.

gas	* config/tc-z80.c: Add -gbz80 command line option to generate code
	for the GameBoy Z80.  Add support for generating DWARF.
	* config/tc-z80.h: Add support for DWARF debug information
	generation.
	* doc/c-z80.texi: Document new command line option.
	* testsuite/gas/z80/gbz80_all.d: New file.
	* testsuite/gas/z80/gbz80_all.s: New file.
	* testsuite/gas/z80/z80.exp: Run the new tests.
	* testsuite/gas/z80/z80n_all.d: New file.
	* testsuite/gas/z80/z80n_all.s: New file.
	* testsuite/gas/z80/z80n_reloc.d: New file.

include	* coff/internal.h (R_IMM16BE): Define.
	* elf/z80.h (EF_Z80_MACH_Z80N): Define.
	(R_Z80_16_BE): New reloc.

ld	* emulparams/elf32z80.sh: Use z80 emulation.
	* emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations.
	* emultempl/z80elf.em: Delete.
	* testsuite/ld-elf/pr22450.d: Expect to fail for the Z80.
	* testsuite/ld-elf/sec64k.exp: Fix Z80 assembly.
	* testsuite/ld-unique/pr21529.s: Avoid register name conflict.
	* testsuite/ld-unique/unique.s: Likewise.
	* testsuite/ld-unique/unique_empty.s: Likewise.
	* testsuite/ld-unique/unique_shared.s: Likewise.
	* testsuite/ld-unique/unique.d: Updated expected output.
	* testsuite/ld-z80/arch_z80n.d: New file.
	* testsuite/ld-z80/comb_arch_z80_z80n.d: New file.
	* testsuite/ld-z80/labels.s: Add more labels.
	* testsuite/ld-z80/relocs.s: Add more reloc tests.
	* testsuite/ld-z80/relocs_f_z80n.d: New file

opcodes	* z80-dis.c: Add support for GBZ80 opcodes.
2020-02-07 14:53:46 +00:00
Alan Modra
c5d7be0c97 ubsan: d30v: negation of -2147483648
include/
	* opcode/d30v.h (struct pd_reg): Make value field unsigned.
opcodes/
	* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2020-02-04 14:10:40 +10:30
Alan Modra
44e4546fa2 ubsan: m32c: left shift of negative value
cpu/
	* m32c.cpu (f-dsp-64-s16): Mask before shifting signed value.
opcodes/
	* m32c-ibld.c: Regenerate.
2020-02-03 15:59:08 +10:30
Alan Modra
b2b1453ad4 ubsan: frv: left shift of negative value
More non-bugs flagged by ubsan, unless you happen to be compiling for
a 1's complement host.

cpu/
	* frv.cpu (f-u12): Multiply rather than left shift signed values.
	(f-label16, f-label24): Likewise.
opcodes/
	* frv-ibld.c: Regenerate.
2020-02-01 23:23:18 +10:30
Jan Beulich
4102be5cf9 x86: replace EXxmm_mdq by EXVexWdqScalar
There's no need to have two operand specifiers / enumerators for the
same purpose. This then renders xmm_mdq_mode unused.
2020-01-31 14:29:18 +01:00
Jan Beulich
825bd36cea x86: drop unused EXVexWdq / vex_w_dq_mode 2020-01-31 14:28:43 +01:00
Richard Sandiford
c3036ed063 aarch64: Fix MOVPRFX markup for bf16 conversions
bfcvt converts a .S input to a .H output, so any predicated movprfx
needs to operate on .S rather than .H.  In common with SVE2 narrowing
top operations, bfcvtnt doesn't accept movprfx.

2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.

gas/
	* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
	.s for the movprfx.
	* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
	* testsuite/gas/aarch64/sve-movprfx_28.d,
	* testsuite/gas/aarch64/sve-movprfx_28.l,
	* testsuite/gas/aarch64/sve-movprfx_28.s: New test.
2020-01-31 13:22:46 +00:00
Alan Modra
0c115f8483 ubsan: m32c: left shift of negative value
More nonsense fixing "bugs" with left shifts of signed values.  Yes,
the C standard does say this is undefined (and right shifts of signed
values are implementation defined BTW) but in practice there is no
problem with current machines.  1's complement is a thing of the past.

cpu/
	* m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting.
	(f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise.
	(f-dst32-rn-prefixed-QI): Likewise.
	(f-dsp-32-s32): Mask before shifting left.
	(f-dsp-48-u32, f-dsp-48-s32): Likewise.
	(f-bitbase32-16-s11-unprefixed): Multiply signed field rather than
	shifting left.
	(f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise.
	(h-gr-SI): Mask before shifting.
opcodes/
	* m32c-ibld.c: Regenerate.
2020-01-30 23:39:55 +10:30
Jose E. Marchesi
bd434cc4d9 cpu,opcodes,gas: fix neg and neg32 instructions in BPF
This patch fixes the neg/neg32 BPF instructions, which have K (=0)
instead of X (=1) in their header source bit, despite operating on
registes.

cpu/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (define-alu-insn-un): The unary BPF instructions
	(neg and neg32) use OP_SRC_K even if they operate only in
	registers.

opcodes/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c: Regenerate.

gas/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.d: Update expected opcode for `neg'.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise for `neg32'.
	* testsuite/gas/bpf/alu32-be.d: Likewise.
2020-01-30 13:59:04 +01:00
Jan Beulich
aeab2b26db x86-64: honor vendor specifics for near RET
While vendors agree about default operand size (64 bits) and hence
unavilability of a 32-bit form, AMD honors a 16-bit operand size
override (0x66) while Intel doesn't.
2020-01-30 11:36:33 +01:00
Jan Beulich
62b3f54810 x86: drop further pointless/bogus DefaultSize
- 64-bit CALL permitting just a single operand size doesn't need it.
- FLDENV et al should never have had it.

It remains suspicious that a number of 64-bit only insns continue to
have the attribute, despite this being intended for .code16gcc handling
only.
2020-01-30 11:33:53 +01:00
Alan Modra
1bd8ae1004 ubsan: tic4x: left shift cannot be represented in type 'int'
The patch also fixes a case where libopcodes built for a 64-bit
bfd_vma may print different results to libopcodes built for a 32-bit
bfd_vma.

	* tic4x-dis.c (tic4x_dp): Make unsigned.
2020-01-30 17:06:54 +10:30
H.J. Lu
bc31405ebb x86-64: Properly encode and decode movsxd
movsxd is a 64-bit only instruction.  It supports both 16-bit and 32-bit
destination registers.  Its AT&T mnemonic is movslq which only supports
64-bit destination register.  There is also a discrepancy between AMD64
and Intel64 on movsxd with 16-bit destination register.  AMD64 supports
32-bit source operand and Intel64 supports 16-bit source operand.

This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit
destination registers.  It also handles movsxd with 16-bit destination
register for AMD64 and Intel 64.

gas/

	PR binutils/25445
	* config/tc-i386.c (check_long_reg): Also convert to QWORD for
	movsxd.
	* doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA
	differences.  Document movslq and movsxd.
	* testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests.
	* testsuite/gas/i386/x86-64-movsxd-intel.d: New file.
	* testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-movsxd.d: Likewise.
	* testsuite/gas/i386/x86-64-movsxd.s: Likewise.

opcodes/

	PR binutils/25445
	* i386-dis.c (MOVSXD_Fixup): New function.
	(movsxd_mode): New enum.
	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	(intel_operand_size): Handle movsxd_mode.
	(OP_E_register): Likewise.
	(OP_G): Likewise.
	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	register on movsxd.  Add movsxd with 16-bit destination register
	for AMD64 and Intel64 ISAs.
	* i386-tbl.h: Regenerated.
2020-01-27 04:38:29 -08:00
Tamar Christina
7568c93bf9 AArch64: Fix cfinv disassembly issues
This fixes the preferred disassembly for cfinv.  The Armv8.4-a instruction
overlaps with the possible encoding space for msr.  This because msr allows you
to use unallocated encoding space using the general sA_B_cC_cD_E form.

However when an encoding does become allocated then we need to ensure that it's
used as the preferred disassembly.  The problem with cfinv is that its mask has
all bits sets because it has no arguments.

This causes issues for the Alias resolver in gas as it uses the mask to build
alias graph.  In this case it can't do it since it thinks almost everything
would alias with cfinv.  So instead we can only fix this by moving cfinv before
msr.

gas/ChangeLog:

	PR 25403
	* testsuite/gas/aarch64/armv8_4-a.d: Add cfinv.
	* testsuite/gas/aarch64/armv8_4-a.s: Likewise.

opcodes/ChangeLog:

	PR 25403
	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	* aarch64-asm-2.c: Regenerate
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
2020-01-27 10:55:41 +00:00
Jan Beulich
c006a730e9 x86: improve handling of insns with ambiguous operand sizes
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).

While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.

No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).

As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).

Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.

Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.

Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).
2020-01-21 08:28:25 +01:00
Jan Beulich
c906a69a1f x86: VCVTNEPS2BF16{X,Y} should permit broadcasting
Just like other VCVT*{X,Y} templates do, and to allow the programmer
flexibility (might be relevant in particular when heavily macro-izing
code), the two templates should also have Broadcast set, just like their
X/Y-suffix-less counterparts. This in turn requires them to also have
* Dword set on their memory operands, to cover the logic added to
  i386gen by 4a1b91eabb ("x86: Expand Broadcast to 3 bits"),
* RegXMM/RegYMM set on their source operands, to satisfy broadcast
  sizing logic in gas itself.
Otherwise ATTSyntax templates wouldn't need such operand size attributes.

While extending the test cases, also add Intel syntax broadcast forms
without explicit size specifiers.
2020-01-21 08:25:31 +01:00
Nick Clifton
26916852e1 Updated translations for various binutils sub-directories 2020-01-20 15:10:23 +00:00
Alan Modra
4d6cbb6442 ubsan: hppa: negation of -2147483648
* hppa-dis.c (fput_const): Remove useless cast.
2020-01-20 15:45:50 +10:30
Alan Modra
2bddb71a74 ubsan: arm: out of bounds array access
.inst 0x81bdfe9f

disassembles as
   0:	81bdfe9f 	ldaexdhi	pc, reg-names-std, [sp]

I'm quite sure "reg-names-std" isn't an ARM register.

	* arm-dis.c (print_insn_arm): Wrap 'T' value.
2020-01-20 15:45:50 +10:30
Nick Clifton
1b1bb2c67b Update version to 2.34.50. Regenerate configure and .pot files. 2020-01-18 14:12:07 +00:00
Nick Clifton
ae77468624 Add markers for 2.34 branch to the NEWS files and ChangeLogs. 2020-01-18 13:50:25 +00:00
Christian Biesinger
07f1f3aa53 Fix spelling errors
seperate -> separate

bfd/ChangeLog:

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* coff-arm.c: Fix spelling error (seperate).
	* elfxx-riscv.c (riscv_parse_sv_or_non_std_ext): Fix spelling
	error (seperate).
	* sysdep.h (strnlen): Fix spelling error (seperate).

opcodes/ChangeLog:

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* opintl.h: Fix spelling error (seperate).

sim/arm/ChangeLog:

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* iwmmxt.c: Fix spelling error (seperate).

Change-Id: I55e5f47bcf3cf3533d2acb7ad338f1be0d5f30f9
2020-01-17 12:34:03 -06:00
H.J. Lu
42e04b3601 x86: Add {vex} pseudo prefix
There are 2-byte VEX prefix and 3-byte VEX prefix.  2-byte VEX prefix
can't encode all operands.  By default, assembler tries 2-byte VEX prefix
first.  {vex3} can be used to force 3-byte VEX prefix.  This patch adds
{vex} pseudo prefix and keeps {vex2} for backward compatibility.

gas/

	* config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
	with vex_encoding_vex.
	(parse_insn): Likewise.
	* doc/c-i386.texi: Replace {vex2} with {vex}.  Update {vex}
	and {vex3} documentation.
	* testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
	{vex}.
	* testsuite/gas/i386/x86-64-pseudos.s: Likewise.

opcodes/

	* i386-opc.tbl: Add {vex} pseudo prefix.
	* i386-tbl.h: Regenerated.
2020-01-17 07:07:55 -08:00
Andre Vieira
2da2eaf4ce [binutils][arm] PR25376 Change MVE into a CORE_HIGH feature
This patch moves MVE feature bits into the CORE_HIGH section.  This makes sure
.fpu and -mfpu does not reset the bits set by MVE. This is important because
.fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose
to define MVE as an architecture extension rather than put it together with
other the legacy fpu features.

This will enable the following behavior:
.arch armv8.1-m.main
.arch mve
.fpu fpv5-sp-d16               #does not disable mve.
vadd.i32 q0, q1, q2

This patch also makes sure MVE is not taken into account during auto-detect.
This was already the case, but because we moved the MVE bits to the
architecture feature space we must make sure ARM_ANY does not include MVE.

gas/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
	(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
	* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
	* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
	* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
	* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.

include/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to...
	(ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space.
	(ARM_ANY): Redefine to not include any MVE bits.
	(ARM_FEATURE_ALL): Removed.

opcodes/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	(neon_opcodes): Likewise.
	(select_arm_features): Make sure we enable MVE bits when selecting
	armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
	any architecture.
2020-01-16 14:33:01 +00:00
Jan Beulich
d0849eed78 x86: drop stale Vec_Imm4 related comment
I overlooked this in commit 9d3bf266fd ("x86: drop Vec_Imm4"), presumably
because of the mis-spelling.
2020-01-16 10:07:05 +01:00
Jan Beulich
9cf70a448b x86: add a few more missing VexWIG
Alternatively it could also be VexW0 (to match other SSE2AVX), but the
VexW attribute shouldn't be left unset.
2020-01-16 10:06:21 +01:00
Jan Beulich
4814632e69 x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit mode
The AVX512DQ patterns lacking a Cpu64 attribute made the memory operand
forms accepted even outside of 64-bit mode, and this even without any
{evex} pseudo-prefix (otherwise one could argue that this is an attempt
to follow one possible, albeit somewhat odd, interpretation of the SDM
wording to this effect).

For consistency between the various involved templates drop the
* (now) unnecessary IgnoreSize attributes
* unnecessary (due to VexW1) Size64 attributes from VEX encoded forms
* redundant (with Reg64) Qword operand attributes
uniformly.
2020-01-16 10:05:35 +01:00
Alan Modra
aad09917e0 tic4x disassembly static variables
tic4x uses a number of static variables for tables that are generated
depending on the current machine (tic4x vs. tic3x).  However, it is
possible to change the machine from one invocation of print_insn_tic4x
to the next.  This patch throws away the old state if that happens,
and uses a relatively small known size array of register names rather
than a malloc'd table.

	* tic4x-dis.c (tic4x_version): Make unsigned long.
	(optab, optab_special, registernames): New file scope vars.
	(tic4x_print_register): Set up registernames rather than
	malloc'd registertable.
	(tic4x_disassemble): Delete optable and optable_special.  Use
	optab and optab_special instead.  Throw away old optab,
	optab_special and registernames when info->mach changes.
2020-01-16 00:01:13 +10:30
Sergey Belyashov
7a6bf3becb Fix various assembler testsuite failures for the Z80 target.
PR 25377
gas	* config/tc-z80.c: Add support for half precision, single
	precision and double precision floating point values.
	* config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes.
	* doc/as.texi: Add new z80 command line options.
	* doc/c-z80.texi: Document new z80 command line options.
	* testsuite/gas/z80/ez80_pref_dis.s: New test.
	* testsuite/gas/z80/ez80_pref_dis.d: New test driver.
	* testsuite/gas/z80/z80.exp: Run the new test.
	* testsuite/gas/z80/fp_math48.d: Use correct command line option.
	* testsuite/gas/z80/fp_zeda32.d: Likewise.
	* testsuite/gas/z80/strings.d: Update expected output.

opcodes	* z80-dis.c (suffix): Use .db instruction to generate double
	prefix.
2020-01-14 13:13:57 +00:00
Alan Modra
ca1eaac0ed ubsan: z8k: left shift cannot be represented in type 'int'
* z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
	values to unsigned before shifting.
2020-01-14 10:57:52 +10:30
Thomas Troeger
1d67fe3b6e Add an option to objdump's disassembler to generate ascii art diagrams showing the destinations of flow control instructions.
binutils* objdump.c (visualize_jumps, color_output, extended_color_output)
	(detected_jumps): New variables.
	(usage): Add the new jump visualization options.
	(option_values): Add new option value.
	(long_options): Add the new option.
	(jump_info_new, jump_info_free): New functions.
	(jump_info_min_address, jump_info_max_address): Likewise.
	(jump_info_end_address, jump_info_is_start_address): Likewise.
	(jump_info_is_end_address, jump_info_size): Likewise.
	(jump_info_unlink, jump_info_insert): Likewise.
	(jump_info_add_front, jump_info_move_linked): Likewise.
	(jump_info_intersect, jump_info_merge): Likewise.
	(jump_info_sort, jump_info_visualize_address): Likewise.
	(disassemble_jumps): New function - used to locate jumps.
	(disassemble_bytes): Add ascii art generation.
	(disassemble_section): Add scan to locate jumps.
	(main): Parse the new visualization option.
	* doc/binutils.texi: Document the new feature.
	* NEWS: Mention the new feature.

opcodes	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	flow instructions.
	(print_insn_thumb16, print_insn_thumb32): Likewise.
	(print_insn): Initialize the insn info.
	* i386-dis.c (print_insn): Initialize the insn info fields, and
	detect jumps.
2020-01-13 12:36:55 +00:00
Claudiu Zissulescu
5e4f7e0518 [ARC][committed] Code cleanup and improvements.
Code clean up and improvements when changing the cpu from command
line. Also, remove unused/old emulations.

gas/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change
	the CPU.
	* config/tc-arc.h: Add header if/defs.
	* testsuite/gas/arc/pseudos.d: Improve matching pattern.

ls/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* Makefile.am: Remove earcelf_prof.c and earclinux_prof.c
	emulations.
	* Makefile.in: Regenerate.
	* configure.tgt: Likewise.
	* emulparams/arcelf_prof.sh: Remove file.
	* emulparams/arclinux_prof.sh: Likewise.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (C_NE): Make it required.
2020-01-13 11:16:47 +02:00
Claudiu Zissulescu
b9fe6b8aa6 [ARC] [COMMITTED] Change ACCL/ACCH reg name to generic.
ACCL/ACCH register names are only available for ARCv2 architecture,
leading to a confusion when disassembling for any other ARC
variants. This patch is changing the default names for ACCL/ACCH to
generic r58/r59.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

        * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	reserved register name.
2020-01-13 10:25:50 +02:00
Alan Modra
90dee485e5 asan: ns32k: wild memory write
index_offset isn't set up for "sfsr", resulting in a random offset
being used when trying to disassemble the following.

 .byte 0x3e, 0xf7, 0x07, 0x00

	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2020-01-13 18:43:34 +10:30
Alan Modra
febda64f15 ubsan: wasm32: signed integer overflow
The signed integer overflow occurred when adding one to target_count
  for (i = 0; i < target_count + 1; i++)
but that's the least of the worries here.  target_count was long and i
int, leading to the possibility of a loop that never ended.

So to avoid this type of vulnerability, this patch uses what I believe
to be the proper types for arguments of various wasm32 opcodes, rather
than using "long" which may change in size.

gas/
	* testsuite/gas/wasm32/allinsn.d: Update expected output.
opcodes/
	* wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
	result of wasm_read_leb128 in a uint64_t and check that bits
	are not lost when copying to other locals.  Use uint32_t for
	most locals.  Use PRId64 when printing int64_t.
2020-01-13 16:44:27 +10:30
Alan Modra
df08b5881b score formatting
* score-dis.c: Formatting.
	* score7-dis.c: Formatting.
2020-01-13 12:12:41 +10:30
Alan Modra
b2c759ce68 ubsan: score: left shift of negative value
* score-dis.c (print_insn_score48): Use unsigned variables for
	unsigned values.  Don't left shift negative values.
	(print_insn_score32): Likewise.
	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2020-01-13 12:12:30 +10:30
Alan Modra
5496abe1c5 tic4x: sign extension using shifts
Don't do that.  Especially don't use shift counts that assume the type
being shifted is 32 bits when the type is long/unsigned long.  Also
reverts part of a change I made on 2019-12-11 to tic4x_print_register
that on closer inspection turns out to be unnecessary.

include/
	* opcode/tic4x.h (EXTR): Delete.
	(EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign
	extension using shifts.  Do trim INSERTU value to specified bitfield.
opcodes/
	* tic4x-dis.c (tic4x_print_register): Remove dead code.
gas/
	* config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap
	insertion.
2020-01-13 12:12:05 +10:30
Alan Modra
202e762b32 ubsan: fr30: left shift of negative value
cpu/
	* fr30.cpu (f-disp9, f-disp10, f-s10, f-rel9, f-rel12): Don't
	left shift signed values.
opcodes/
	* fr30-ibld.c: Regenerate.
2020-01-13 12:12:05 +10:30
Alan Modra
7ef412cf72 ubsan: xgate: left shift of negative value
* xgate-dis.c (print_insn): Don't left shift signed value.
	(ripBits): Formatting, use 1u.
2020-01-13 12:12:05 +10:30
Alan Modra
7f578b959c ubsan: tilepro: signed integer overflow
* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
2020-01-10 17:32:33 +10:30
Alan Modra
441af85bd9 ubsan: m10300: shift exponent -4
* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	and XRREG value earlier to avoid a shift with negative exponent.
	* m10200-dis.c (disassemble): Similarly.
2020-01-10 17:32:33 +10:30
Nick Clifton
bce58db4fb Fix the cast used to prevent compile time warning about an always false test.
PR 25224
	* z80-dis.c (ld_ii_ii): Use correct cast.
2020-01-09 14:32:49 +00:00
Sergey Belyashov
40c75bc8b0 Fix compile time warnings about comparisons always being false.
PR 25224
gas	* config/tc-z80.c (emit_ld_m_rr): Use integer types when checking
	opcode byte values.
	(emit_ld_r_r): Likewise.
	(emit_ld_rr_m): Likewise.
	(emit_ld_rr_nn): Likewise.

opcodes	* z80-dis.c (ld_ii_ii): Use character constant when checking
	opcode byte value.
2020-01-09 11:49:18 +00:00
Jan Beulich
d835a58baa x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMD
The disassembler change is such that in default mode we'd disassemble
the insns (for there not ebing any conflicts), but when AMD64 mode was
explicitly requested, we'd show them as "(bad)".
2020-01-09 11:38:01 +01:00
Alan Modra
030a2e78ac ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]'
The fix is the additional ARRAY_SIZE test, the rest just tidies
variable types rather than adding a cast to avoid warnings.

opcodes/
	* z8k-dis.c: Include libiberty.h
	(instr_data_s): Make max_fetched unsigned.
	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	Don't exceed byte_info bounds.
	(output_instr): Make num_bytes unsigned.
	(unpack_instr): Likewise for nibl_count and loop.
	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	idx unsigned.
	* z8k-opc.h: Regenerate.
gas/
	* config/tc-z8k.c (md_begin): Make idx unsigned.
	(get_specific): Likewise for this_index.
2020-01-08 21:51:32 +10:30
Shahab Vahedi
bb82aefe17 [ARC] Add finer details for LLOCK and SCOND
This patch changes the "class" of LLOCK/SCOND from "MEMORY" to
"LLOCK/SCOND" respectively. Moreover, it corrects the "data_size_mode".

These changes are necessary for GDB's atmoic sequence handler.

Signed-off-by: Shahab Vahedi <shahab@synopsys.com>
2020-01-07 15:25:34 +02:00
Alan Modra
cc6aa1a6e0 ubsan: m32c: left shift of negative value
There are probably a lot more of these still here.

cpu/
	* m32c.cpu (f-dsp-8-u16, f-dsp-8-s16): Rearrange to mask any sign
	bits before shifting rather than masking after shifting.
	(f-dsp-16-u16, f-dsp-16-s16, f-dsp-32-u16, f-dsp-32-s16): Likewise.
	(f-dsp-40-u16, f-dsp-40-s16, f-dsp-48-u16, f-dsp-48-s16): Likewise.
	(f-dsp-64-u16, f-dsp-8-s24): Likewise.
	(f-bitbase32-16-s19-unprefixed): Avoid signed left shift.
opcodes/
	* m32c-ibld.c: Regenerate.
2020-01-06 21:53:51 +10:30
Alan Modra
660e62b1d9 PR25344, z80 disassembler recursion
PR 25344
	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	Peek at next byte to prevent recursion on repeated prefix bytes.
	Ensure uninitialised "mybuf" is not accessed.
	(print_insn_z80): Don't zero n_fetch and n_used here,..
	(print_insn_z80_buf): ..do it here instead.
2020-01-06 21:53:16 +10:30
Alan Modra
c9ae58fe32 ubsan: m32r: left shift of negative value
cpu/
	* m32r.cpu (f-disp8): Avoid left shift of negative values.
	(f-disp16, f-disp24): Likewise.
opcodes/
	* m32r-ibld.c: Regenerate.
2020-01-04 19:20:33 +10:30
Alan Modra
5f57d4ecf5 ubsan: cr16: left shift cannot be represented in type 'int'
* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2020-01-04 19:20:33 +10:30
Alan Modra
2c5c119630 ubsan: crx: left shift cannot be represented in type 'int'
* crx-dis.c (match_opcode): Avoid shift left of signed value.
2020-01-04 19:20:33 +10:30
Alan Modra
2e98c6c5c5 ubsan: d30v: left shift cannot be represented in type 'int'
* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2020-01-04 19:20:33 +10:30
Jan Beulich
5437a02abc Arm64: correct address index operands for LD1RO{H,W,D}
Just like their LD1RQ{H,W,D} counterparts, as per the specification the
index registers get scaled by element size.
2020-01-03 10:16:44 +01:00
Jan Beulich
567dfba2be Arm64: correct {su,us}dot SIMD encodings
According to the specification these permit the Q bit to control the
vector length operated on, and hence this bit should not already be set
in the opcode table entries (it rather needs setting dynamically). Note
how the test case output did also not match its input. Besides
correcting the test case also extend it to cover both forms.
2020-01-03 10:14:16 +01:00
Jan Beulich
8c45011acd Arm64: correct uzp{1,2} mnemonics
According to the specification, and in line with the pre-existing
predicate forms, the mnemonics do not include an 'i'.
2020-01-03 10:13:31 +01:00
Jan Beulich
f4950f76fa Arm64: correct 64-bit element fmmla encoding
There's just one bit of difference to the 32-bit element form, as
per the documentation.
2020-01-03 10:12:49 +01:00
Sergey Belyashov
6655dba246 Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an ELF based target for these as well.
PR 25224
bfd	* Makefile.am: Add z80-elf target support.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* config.bfd: Add z80-elf target support and new arches: ez80 and z180.
	* elf32-z80.c: New file.
	* archures.c: Add new z80 architectures: eZ80 and Z180.
	* coffcode.h: Likewise.
	* cpu-z80.c: Likewise.
	* bfd-in2.h: Likewise plus additional Z80 relocations.
	* coff-z80.c: Add new relocations for Z80 target and local label check.

gas	* config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support
	for assembler code generated by SDCC. Add new relocation types. Add
	z80-elf target support.
	* config/tc-z80.h: Add z80-elf target support. Enable dollar local
	labels. Local labels starts from ".L".
	* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
	* testsuite/gas/all/fwdexp.s: Likewise.
	* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
	* testsuite/gas/z80/z80.exp: Add new tests
	* testsuite/gas/z80/dollar.d: New file.
	* testsuite/gas/z80/dollar.s: New file.
	* testsuite/gas/z80/ez80_adl_all.d: New file.
	* testsuite/gas/z80/ez80_adl_all.s: New file.
	* testsuite/gas/z80/ez80_adl_suf.d: New file.
	* testsuite/gas/z80/ez80_isuf.s: New file.
	* testsuite/gas/z80/ez80_z80_all.d: New file.
	* testsuite/gas/z80/ez80_z80_all.s: New file.
	* testsuite/gas/z80/ez80_z80_suf.d: New file.
	* testsuite/gas/z80/r800_extra.d: New file.
	* testsuite/gas/z80/r800_extra.s: New file.
	* testsuite/gas/z80/r800_ii8.d: New file.
	* testsuite/gas/z80/r800_z80_doc.d: New file.
	* testsuite/gas/z80/z180.d: New file.
	* testsuite/gas/z80/z180.s: New file.
	* testsuite/gas/z80/z180_z80_doc.d: New file.
	* testsuite/gas/z80/z80_doc.d: New file.
	* testsuite/gas/z80/z80_doc.s: New file.
	* testsuite/gas/z80/z80_ii8.d: New file.
	* testsuite/gas/z80/z80_ii8.s: New file.
	* testsuite/gas/z80/z80_in_f_c.d: New file.
	* testsuite/gas/z80/z80_in_f_c.s: New file.
	* testsuite/gas/z80/z80_op_ii_ld.d: New file.
	* testsuite/gas/z80/z80_op_ii_ld.s: New file.
	* testsuite/gas/z80/z80_out_c_0.d: New file.
	* testsuite/gas/z80/z80_out_c_0.s: New file.
	* testsuite/gas/z80/z80_reloc.d: New file.
	* testsuite/gas/z80/z80_reloc.s: New file.
	* testsuite/gas/z80/z80_sli.d: New file.
	* testsuite/gas/z80/z80_sli.s: New file.

ld	* Makefile.am: Add new target z80-elf
	* configure.tgt: Likewise.
	* emultempl/z80.em: Add support for eZ80 and Z180 architectures.
	* emulparams/elf32z80.sh: New file.
	* emultempl/z80elf.em: Likewise.
	* testsuite/ld-z80/arch_ez80_adl.d: Likewise.
	* testsuite/ld-z80/arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/arch_r800.d: Likewise.
	* testsuite/ld-z80/arch_z180.d: Likewise.
	* testsuite/ld-z80/arch_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z180.d: Likewise.
	* testsuite/ld-z80/labels.s: Likewise.
	* testsuite/ld-z80/relocs.s: Likewise.
	* testsuite/ld-z80/relocs_b_ez80.d: Likewise.
	* testsuite/ld-z80/relocs_b_z80.d: Likewise.
	* testsuite/ld-z80/relocs_f_z80.d: Likewise.
	* testsuite/ld-z80/z80.exp: Likewise.

opcodes	* z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02 14:14:59 +00:00
Alan Modra
b14ce8bfe1 Re: Update year range in copyright notice of binutils files
Add the ChangeLog entry.
2020-01-01 18:55:18 +10:30
Alan Modra
0b11474080 ChangeLog rotation 2020-01-01 18:12:08 +10:30
Alan Modra
2c5b6e1a1c Re: Usage of unitialized heap in tic4x_print_cond
PR 25319
	* tic4x-dis.c (tic4x_print_cond): Correct order of xcalloc args.
2019-12-30 09:35:29 +10:30
Alan Modra
4383e1fc3b ubsan: sparc: left shift cannot be represented in type 'int'
* sparc-dis.c (SEX): Don't use left and right shift to sign extend.
	(compare_opcodes): Avoid signed shift left overflow.
	(print_insn_sparc): Likewise.
2019-12-29 22:13:27 +10:30
Alan Modra
8c5e259235 Usage of unitialized heap in tic4x_print_cond
PR 25319
	* tic4x-dis.c (tic4x_print_cond): Init all of condtable.
2019-12-29 22:13:12 +10:30
Jan Beulich
376cd05610 x86-64: fix Intel64 handling of branch with data16 prefix
The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious
direct destination to translate to an indirect _far_ branch is plain
wrong. The operand size prefix should have no effect at all on the
interpretation of the operand. The main underlying issue here is that
the Intel64 templates of the direct branches don't include Disp16, yet
various assumptions exist that it would always be there when there's
also Disp32/Disp32S, toggled by the operand size prefix (which is
being ignored by direct branches in Intel64 mode).

Along these lines it was also wrong to base the displacement width
decision solely on the operand size prefix: REX.W cancels this effect
and hence needs taking into consideration, too.

A disassembler change is needed here as well: XBEGIN was wrongly treated
the same as direct CALL/JMP, which isn't the case - the operand size
prefix does affect displacement size there, it's merely ignored when it
comes to updating [ER]IP.
2019-12-27 09:38:34 +01:00
Jan Beulich
48bcea9f48 x86: consolidate Disp<NN> handling a little
In memory operand addressing, which forms of displacement are permitted
besides Disp8 is pretty clearly limited
- outside of 64-bit mode, Disp16 or Disp32 only, depending on address
  size (MPX being special in not allowing Disp16),
- in 64-bit mode, Disp32s or Disp64 without address size override, and
  solely Disp32 with one.
Adjust assembler and i386-gen to match this, observing that templates
already get adjusted before trying to match them against input depending
on the presence of an address size prefix.

This adjustment logic gets extended to all cases, as certain DispNN
values should also be dropped when there's no such prefix. In fact
behavior of the assembler, perhaps besides the exact diagnostics wording,
should not differ between there being templates applicable to 64-bit and
non-64-bit at the same time, or there being fully separate sets of
templates, with their DispNN settings already reduced accordingly.

This adjustment logic further gets guarded such that there wouldn't be
and Disp<N> conversion based on address size prefix when this prefix
doesn't control the width of the displacement (on branches other than
absolute ones).

These adjustments then also allow folding two MOV templates, which had
been split between 64-bit and non-64-bits variants so far.

Once in this area also
- drop the bogus DispNN from JumpByte templates, leaving just the
  correct Disp8 there (compensated by i386_finalize_displacement()
  now setting Disp8 on their operands),
- add the missing Disp32S to XBEGIN.

Note that the changes make it necessary to temporarily mark a test as
XFAIL; this will get taken care of by a subsequent patch. The failing
parts are entirely bogus and will get replaced.
2019-12-27 09:22:03 +01:00
Alan Modra
100b122fc1 ubsan: crx: index 5 out of bounds for type 'operand_desc const[5]'
* crx-dis.c (get_number_of_operands): Don't access operands[]
	out of bounds.
2019-12-26 17:49:03 +10:30
Alan Modra
6c2ca6c25d ubsan: v850: left shift cannot be represented in type 'int'
Another 1 << 31 complaint.

	* v850-dis.c (disassemble): Avoid signed overflow.  Don't use
	long vars when unsigned int will do.
2019-12-26 17:49:03 +10:30
Alan Modra
ebd1c6d1d3 ubsan: arm: shift exponent 32 is too large for 32-bit type 'unsigned int'
* arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
2019-12-24 12:01:42 +10:30
Jan Beulich
0e62b37a3f ppc: misc minor build corrections
Avoid shadowing a libiberty symbol (which oldish gcc warns about by
default), and allow building cleanly on 32-bit distros.
2019-12-23 11:53:10 +01:00
Alan Modra
7936714c0c ubsan: score: left shift of 2 by 31 places cannot be represented in type 'int'
* score-dis.c (print_insn_score32): Avoid signed overflow.
	(print_insn_score48): Likewise.  Don't cast to int when printing
	hex values.
2019-12-23 18:05:19 +10:30
Alan Modra
3e1056a1a6 ubsan: iq2000: left shift of negative value
cpu/
	* iq2000.cpu (f-offset): Avoid left shift of negative values.
opcodes/
	* iq2000-ibld.c: Regenerate.
2019-12-23 18:04:12 +10:30
Alan Modra
1a1e2852a5 ubsan: d30v: left shift cannot be represented in type 'long long'
* d30v-dis.c (extract_value): Make num param a uint64_t, constify
	oper.  Use unsigned vars.
	(print_insn): Make num var uint64_t.  Constify oper and remove now
	unnecessary casts on extract_value calls.
	(print_insn_d30v): Use unsigned vars.  Adjust printf formats.
2019-12-23 18:02:44 +10:30
Alan Modra
27c1c4271a ubsan: wasm: shift is too large for 64-bit type 'bfd_vma'
bfd/
	* wasm-module.c (wasm_read_leb128): Don't allow oversize shifts.
	Catch value overflow.  Sign extend only on terminating byte.
opcodes/
	* wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
	Catch value overflow.  Sign extend only on terminating byte.
2019-12-23 17:58:09 +10:30
Alan Modra
cda8d785b3 PR25281, sh disassembler abort
PR 25281
	* sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
	and MOVY_NOPX insns.  For invalid cases include 0xf000 in the word
	printed.  Print .word in more cases.
2019-12-20 17:57:58 +10:30
Alan Modra
bcd9f578a9 ubsan: or1k: left shift of negative value
cpu/
	* or1korbis.cpu (f-disp26, f-disp21): Don't left shift negative values.
opcodes/
	* or1k-ibld.c: Regenerate.
2019-12-20 17:57:58 +10:30
Alan Modra
15d2859fdd ubsan: hppa: left shift of negative value
bfd/
	* libhppa.h (hppa_field_adjust, bfd_hppa_insn2fmt): Delete forward
	declaration.  Move ATTRIBUTE_UNUSED to definition.
	(sign_extend, low_sign_extend, sign_unext, low_sign_unext),
	(re_assemble_3, re_assemble_12, re_assemble_14, re_assemble_16),
	(re_assemble_17, re_assemble_21, re_assemble_22): Likewise.  Make
	args and return value unsigned.  Use unsigned variables.
	(hppa_rebuild_insn): Similarly.
opcodes/
	* hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
	unsigned variables.
2019-12-20 13:36:06 +10:30
Alan Modra
000fe1a756 ubsan: m68hc1x: left shift of negative value
* m68hc11-dis.c (read_memory): Delete forward decls.
	(print_indexed_operand, print_insn): Likewise.
	(print_indexed_operand): Formatting.  Don't rely on short being
	exactly 16 bits, make sign extension explicit.
	(print_insn): Likewise.  Avoid signed overflow.
2019-12-20 13:36:06 +10:30
Alan Modra
f00901886d vax decoding of indexed addressing mode
This patch prevents print_insn_mode recursing into another index mode
byte, which if repeated enough times will overflow private.the_buffer
and scribble over other memory.

	* vax-dis.c (print_insn_mode): Stop index mode recursion.
2019-12-19 15:38:39 +10:30
Dr N.W. Filardo
1d29ab86cb PR25277, microblaze opcode enumeration vs ISO/IEC TS 18661-3:2015
fadd, fmul, and fdiv are now, by ISO/IEC TS 18661-3:2015, defined to
refer to functions from the runtime subsystem.

	PR 25277
	* microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
	fdiv with "mbi_".
	* microblaze-opc.h (opcodes): Adjust to suit.
2019-12-19 10:54:47 +10:30
Alan Modra
2480b6fa94 More signed overflow fixes
The arc fix in create_map avoiding signed overflow by casting an
unsigned char to unsigned int before shifting, shows one of the
dangers of blinding doing that.  The problem in this case was that the
variable storing the value, newAuxRegister->address, was a long.
Using the unsigned cast meant that the 32-bit value was zero extended
when long is 64 bits.  Previously we had a sign extension.  Net result
was that comparisons in arcExtMap_auxRegName didn't match.  Of course,
I could have cast the 32-bit unsigned value back to signed before
storing in a long, but it's neater to just use an unsigned int for the
address.

opcodes/
	* alpha-opc.c (OP): Avoid signed overflow.
	* arm-dis.c (print_insn): Likewise.
	* mcore-dis.c (print_insn_mcore): Likewise.
	* pj-dis.c (get_int): Likewise.
	* ppc-opc.c (EBD15, EBD15BI): Likewise.
	* score7-dis.c (s7_print_insn): Likewise.
	* tic30-dis.c (print_insn_tic30): Likewise.
	* v850-opc.c (insert_SELID): Likewise.
	* vax-dis.c (print_insn_vax): Likewise.
	* arc-ext.c (create_map): Likewise.
	(struct ExtAuxRegister): Make "address" field unsigned int.
	(arcExtMap_auxRegName): Pass unsigned address.
	(dump_ARC_extmap): Adjust.
	* arc-ext.h (arcExtMap_auxRegName): Update prototype.
2019-12-18 18:38:13 +10:30
Alan Modra
eb7b504651 ubsan: visium: left shift cannot be represented in type 'int'
* visium-dis.c (print_insn_visium): Avoid signed overflow.
2019-12-17 23:15:12 +10:30
Alan Modra
29298bf66f ubsan: aarch64: left shift cannot be represented in type 'int64_t'
* aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
	(value_fit_unsigned_field_p): Likewise.
	(aarch64_wide_constant_p): Likewise.
	(operand_general_constraint_met_p): Likewise.
	* aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
2019-12-17 22:58:19 +10:30
Alan Modra
e46d79a76e ubsan: nds32: left shift cannot be represented in type 'int'
Yet more.

	* nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
	(print_insn_nds32): Use uint64_t for "given" and "given1".
2019-12-17 22:58:11 +10:30
Alan Modra
5b660084e2 Remove tic80 support
This is one way of fixing ubsan bug reports, just delete the code.

The assembler support was removed back in 2005 along with other
non-BFD assemblers, but somehow the remainder of the port stayed in.

bfd/
	* coff-tic80.c: Delete file.
	* cpu-tic80.c: Delete file.
	* archures.c: Remove tic80 support.
	* coffcode.h: Likewise.
	* coffswap.h: Likewise.
	* targets.c: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* Makefile.am: Likewise.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
binutils/
	* testsuite/binutils-all/objcopy.exp: Remove tic80 support.
	* testsuite/binutils-all/objdump.exp: Likewise.
gas/
	* doc/as.texi: Remove mention of tic80.
include/
	* coff/tic80.h: Delete file.
	* opcode/tic80.h: Delete file.
ld/
	* emulparams/tic80coff.sh: Delete file.
	* scripttempl/tic80coff.sc: Delete file.
	* configure.tgt: Remove tic80 support.
	* Makefile.am: Likewise.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
opcodes/
	* tic80-dis.c: Delete file.
	* tic80-opc.c: Delete file.
	* disassemble.c: Remove tic80 support.
	* disassemble.h: Likewise.
	* Makefile.am: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
2019-12-17 16:36:54 +10:30
Alan Modra
62e6599087 ubsan: bpf: left shift cannot be represented in type 'DI' (aka 'long')
cpu/
	* bpf.cpu (f-imm64): Avoid signed overflow.
opcodes/
	* bpf-ibld.c: Regenerate.
2019-12-17 14:32:23 +10:30
Alan Modra
f81e7e2db6 ubsan: aarch64: left shift of negative value
* aarch64-dis.c (sign_extend): Return uint64_t.  Rewrite without
	conditional.
	(aarch64_ext_imm): Avoid signed overflow.
2019-12-16 17:35:13 +10:30
Alan Modra
488d02fe77 ubsan: microblaze: left shift cannot be represented in type 'int'
* microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
2019-12-16 17:35:13 +10:30
Alan Modra
8a92faab92 ubsan: nios2: left shift cannot be represented in type 'int'
* nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
2019-12-16 17:35:13 +10:30
Alan Modra
e6ced26afd ubsan: xstormy16: left shift of negative value
cpu/
	* xstormy16.cpu (f-rel12a): Avoid signed overflow.
opcodes/
	* xstormy16-ibld.c: Regenerate.
2019-12-16 17:35:13 +10:30
Alan Modra
84e098cdea asan: score: global-buffer-overflow
I'm flying blind here, not having an s+core s3 insn set reference,
but this seems reasonably obvious from what is done by the assembler.
s3_do16_rpop does some mixing of imm and reg values to place in the
rpop reg field, but I'm not going to try to fix the disassembly
there.

	* score-dis.c (print_insn_score16): Move rpush/rpop imm field
	value adjustment so that it doesn't affect reg field too.
2019-12-16 17:34:29 +10:30
Alan Modra
36bd8ea7f0 ubsan: crx: left shift cannot be represented in type 'int'
The ubsan complaint is fixed by the SBM change, with similar possible
complaints fixed by the EXTRACT change.  The rest is just cleanup.

include/
	* opcode/crx.h (inst <match>): Make unsigned int.
opcodes/
	* crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
	(get_number_of_operands, getargtype, getbits, getregname),
	(getcopregname, getprocregname, gettrapstring, getcinvstring),
	(getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
	(powerof2, match_opcode, make_instruction, print_arguments),
	(print_arg): Delete forward declarations, moving static to..
	(getregname, getcopregname, getregliststring): ..these definitions.
	(build_mask): Return unsigned int mask.
	(match_opcode): Use unsigned int vars.
2019-12-16 17:33:53 +10:30
Alan Modra
cedfc77485 ubsan: bfin: left shift of negative value
* bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
2019-12-16 17:33:53 +10:30
Alan Modra
4bdb25fe69 ubsan: nds32: left shift cannot be represented in type 'int'
Note that using 1u in N32_BIT makes all of N32_BIT, __MASK, __MF, __GF
and __SEXT evaluate as unsigned int (the latter three when when their
v arg is int or smaller).  This would be a problem if assigning the
result to a bfd_vma, long, or other type wider than an int since the
__SEXT result would be zero extended to the wider type.  Fortunately
nds32 target code doesn't use wider types unnecessarily.

include/
	* opcode/nds32.h (N32_BIT): Define using 1u.
	(__SEXT): Use __MASK and N32_BIT.
	(N32_IMMS): Remove duplicate mask.
opcodes/
	* nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
	(struct objdump_disasm_info): Delete.
	(nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
	N32_IMMS to unsigned before shifting left.
2019-12-16 17:33:53 +10:30
Alan Modra
cf950fd4dd ubsan: moxie: left shift of negative value
Commit 8c9b417187 didn't remove a glaring left shift of a number
that had just been sign extended.

	* moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
	(print_insn_moxie): Remove unnecessary cast.
2019-12-16 17:28:52 +10:30
Alan Modra
967354c3b9 csky: tidy csky_chars_to_number
* csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
	mask.
2019-12-12 16:46:45 +10:30
Alan Modra
1d61b03226 Remove more shifts for sign/zero extension
cpu/
	* epiphany.cpu (f-sdisp11): Don't sign extend with shifts.
	* lm32.cpu (f-branch, f-vall): Likewise.
	* m32.cpu (f-lab-8-16): Likewise.
opcodes/
	* arc-dis.c (BITS): Don't truncate high bits with shifts.
	* nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
	* tic54x-dis.c (print_instruction): Likewise.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.
	* tilepro-opc.c (parse_insn_tilepro): Likewise.
	* visium-dis.c (disassem_class0): Likewise.
	* pdp11-dis.c (sign_extend): Likewise.
	(SIGN_BITS): Delete.
	* epiphany-ibld.c: Regenerate.
	* lm32-ibld.c: Regenerate.
	* m32c-ibld.c: Regenerate.
2019-12-11 21:14:19 +10:30
Alan Modra
5afa80e9a8 Re: ubsan: ns32k: left shift cannot be represented in type
* ns32k-dis.c (sign_extend): Correct last patch.
2019-12-11 13:33:26 +10:30
Alan Modra
5c05618a0a ubsan: vax: left shift cannot be represented in type 'int'
* vax-dis.c (NEXTLONG): Avoid signed overflow.
2019-12-11 11:42:09 +10:30
Alan Modra
2a81ccbbbf ubsan: v850: left shift cannot be represented in type 'long'
* v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
	sign extend using shifts.
2019-12-11 11:41:52 +10:30
Alan Modra
b84f6152ee ubsan: tic6x: shift left of int
* tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
2019-12-11 11:41:27 +10:30
Alan Modra
66152f1668 ubsan: tic4x: segv and signed shifts
* tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
	on NULL registertable entry.
	(tic4x_hash_opcode): Use unsigned arithmetic.
2019-12-11 11:41:09 +10:30
Alan Modra
205c426a9b ubsan: s12z: left shift cannot be represented in type 'int'
* s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
2019-12-11 11:40:51 +10:30
Alan Modra
fb4cb4e26d ubsan: ns32k: left shift cannot be represented in type 'int'
* ns32k-dis.c (bit_extract): Use unsigned arithmetic.
	(bit_extract_simple, sign_extend): Likewise.
2019-12-11 11:40:33 +10:30
Alan Modra
96f1f60460 ubsan: nios2: left shift cannot be represented in type 'int'
* nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
2019-12-11 11:40:17 +10:30
Alan Modra
8c9b417187 ubsan: moxie: left shift of negative value
* moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
2019-12-11 11:40:00 +10:30
Alan Modra
334175b693 ubsan: m68k: left shift cannot be represented in type 'int'
* m68k-dis.c (COERCE32): Cast value first.
	(NEXTLONG, NEXTULONG): Avoid signed overflow.
2019-12-11 11:39:42 +10:30
Alan Modra
f8a87c78e6 ubsan: h8300: left shift cannot be represented in type 'int'
This is
  *cst = (data[0] << 24) + (data[1] << 16) + (data[2] << 8) + data[3];
data is unsigned char which promotes to int.

	* h8300-dis.c (extract_immediate): Avoid signed overflow.
	(bfd_h8_disassemble): Likewise.
2019-12-11 11:39:25 +10:30
Alan Modra
159653d8c0 ussan: d30v: index out of bounds
* d30v-dis.c (print_insn): Make opind unsigned.  Don't access
	past end of operands array.
2019-12-11 11:39:07 +10:30
Alan Modra
d93bba9e0d ubsan: csky: left shift cannot be represented in type 'int'
In the following buf is an unsigned char array, so elements are
promoted to int before arithmetic operations.

  if (dis_info.info->endian == BFD_ENDIAN_BIG)
    while (n--)
      val |= buf[n] << (n*8);
  else
    for (i = 0; i < n; i++)
      val |= buf[i] << (i*8);

	* csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
	overflow when collecting bytes of a number.
2019-12-11 11:38:45 +10:30
Alan Modra
c202f69e51 ubsan: cris: signed integer overflow
This was the following in print_with_operands
case 4:
  number
    = buffer[2] + buffer[3] * 256 + buffer[4] * 65536
    + buffer[5] * 0x1000000;
and buffer[5] * 0x1000000 can indeed overflow.  So to fix this we need
to use unsigned arithmetic where overflow semantics are specified.
But number is a long, and the expression is int which will be sign
extended to long.  If we make the expression unsigned it will be zero
extended.  So make number an int32_t and rearrange a little for some
of the places that need fixing.

	* cris-dis.c (print_with_operands): Avoid signed integer
	overflow when collecting bytes of a 32-bit integer.
2019-12-11 11:38:24 +10:30
Alan Modra
0ef562a4b5 ubsan: cr16: left shift cannot be represented in type 'int'
This was:
  unsigned long mask = SBM (instruction->match_bits);
with
  #define SBM(offs)  ((((1 << (32 - offs)) -1) << (offs)))

Well, there are a couple of problems.  Firstly, the expression uses
int values (1 rather than 1u or 1ul) resulting in the ubsan error, and
secondly, a zero offs will result in a 32-bit shift which is undefined
if ints are only 32 bits.

	* cr16-dis.c (EXTRACT, SBM): Rewrite.
	(cr16_match_opcode): Delete duplicate bcond test.
2019-12-11 11:38:04 +10:30
Alan Modra
2fd2b153a3 ubsan: bfin: shift exponent is too large
This was the following in fmtconst_val, x is unsigned int.
    x = SIGNEXTEND (x, constant_formats[cf].nbits);
Problem is, the SIGNEXTEND macro assumed its arg was a long and sign
extended by shifting left then shifting right, and didn't cast the
arg.  So don't do the silly shift thing.  It's not guaranteed to work
anyway according to the C standard.  ">>" might do a logical shift
even if its args are signed.

	* bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
	(SIGNBIT): New.
	(MASKBITS, SIGNEXTEND): Rewrite.
	(fmtconst): Don't use ? expression now that SIGNEXTEND uses
	unsigned arithmetic, instead assign result of SIGNEXTEND back
	to x.
	(fmtconst_val): Use 1u in shift expression.
2019-12-11 11:37:44 +10:30
Alan Modra
a11db3e9f3 ubsan: arc: shift exponent 32 is too large for 32-bit type 'int'
When operand->bits is 32, the following results in UB.
value = (insn >> operand->shift) & ((1 << operand->bits) - 1);

	* arc-dis.c (find_format_from_table): Use ull constant when
	shifting by up to 32.
2019-12-11 11:37:25 +10:30
Alan Modra
9d48687b41 aarch64 disassembler infinite loop
Assembling this to an object and trying to disassemble results in
objdump -d looping forever.

 .inst 0x45205120

	PR 25270
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
	false when field is zero for sve_size_tsz_bhs.
2019-12-11 11:36:59 +10:30
Alan Modra
b8e61daa1a ubsan: epiphany: left shift of negative value
Two places in epiphany_cgen_extract_operand, "value" is a long.
        value = ((((value) << (1))) + (pc));

cpu/
	* epiphany.cpu (f-simm8, f-simm24): Use multiply rather than
	shift left to avoid UB on left shift of negative values.
opcodes/
	* epiphany-ibld.c: Regenerate.
2019-12-11 11:34:33 +10:30
Alan Modra
20135676fc PR24960, Memory leak from disassembler
PR 24960
include/
	* dis-asm.h (disassemble_free_target): Declare.
opcodes/
	* disassemble.c (disassemble_free_target): New function.
binutils/
	* objdump.c (disassemble_data): Call disassemble_free_target.
2019-12-10 09:07:29 +10:30
Alan Modra
103ebbc35c Use disassemble_info.private_data in place of insn_sets
No cgen target uses private_data.  This patch removes a
disassemble_info field that is only used by cgen, and instead uses
private_data.  It also removes a macro that is no longer used.

include/
	* dis-asm.h (struct disassemble_info): Delete insn_sets.
	(INIT_DISASSEMBLE_INFO_NO_ARCH): Don't define.
opcodes/
	* cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
	* disassemble.c (disassemble_init_for_target): Likewise.
	* bpf-dis.c: Regenerate.
	* epiphany-dis.c: Regenerate.
	* fr30-dis.c: Regenerate.
	* frv-dis.c: Regenerate.
	* ip2k-dis.c: Regenerate.
	* iq2000-dis.c: Regenerate.
	* lm32-dis.c: Regenerate.
	* m32c-dis.c: Regenerate.
	* m32r-dis.c: Regenerate.
	* mep-dis.c: Regenerate.
	* mt-dis.c: Regenerate.
	* or1k-dis.c: Regenerate.
	* xc16x-dis.c: Regenerate.
	* xstormy16-dis.c: Regenerate.
2019-12-10 09:04:15 +10:30
Alan Modra
6f0e075230 Remove backup ppc struct dis_private.
ppc-dis.c used a global struct whenever malloc failed to provide the
eight bytes of memory necessary for struct dis_private.  Which is
quite ridiculous.  If that malloc failed there is zero chance some
other malloc won't fail too.

	* ppc-dis.c (private): Delete variable.
	(get_powerpc_dialect): Don't segfault on NULL info->private_data.
	(powerpc_init_dialect): Don't use global private.
2019-12-10 09:02:05 +10:30
Alan Modra
e7c22a69ac s12z-opc.c formatting fixes
Wrap overlong lines, whitespace fixes, and for function definitions
start a line with the name of the function.

	* s12z-opc.c: Formatting.
2019-12-10 09:00:04 +10:30
Alan Modra
0a6aef6b66 S12Z disassembler memory leak
* s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
	registers.
2019-12-08 22:03:53 +10:30
Jan Beulich
2dc4b12fcd Arm64: simplify Crypto arch extension handling
This, at the assembler level, is just a "brace" feature covering both
AES and SHA2. Hence there's no need for it to have a separate feature
flag, freeing up a bit for future re-use. Along these lines there are
also a number of dead definitions/variables in the opcode table file.
2019-12-05 08:44:22 +01:00
Alan Modra
378fd43640 PR25249, Memory leak in microblaze-dis.c
PR 25249
	* microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
	(struct string_buf): New.
	(strbuf): New function.
	(get_field): Use strbuf rather than strdup of local temp.
	(get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
	(get_field_rfsl, get_field_imm15): Likewise.
	(get_field_rd, get_field_r1, get_field_r2): Update macros.
	(get_field_special): Likewise.  Don't strcpy spr.  Formatting.
	(print_insn_microblaze): Formatting.  Init and pass string_buf to
	get_field functions.
2019-12-05 14:58:15 +10:30
Jan Beulich
0ba59a2940 x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifier
Since we accept these without suffix / operand size specifier, we should
also do so with one. (The fact that we unilaterally accept these, other
than far branches, rather than limiting them to Intel64 mode, will be
taken care of later on.)

Also take the opportunity and make sure "lfs <reg>, tbyte ptr <mem>"
et al get rejected outside of 64-bit mode. This became broken by
dc2be329b9 ("i386: Only check suffix in instruction mnemonic").
Furthermore cover lgdt et al in the Intel syntax handling as well, which
continued to work after said commit just by coincidence.
2019-12-04 10:45:17 +01:00
Jan Beulich
77ad80922b x86/Intel: extend MOVDIRI testing
Test also memory operands with operand size specifier, which was broken
prior to dc2be329b9 ("i386: Only check suffix in instruction
mnemonic"), due to the template not permitting any suffixes. Note that
this uncovered a disassembler issue, which is being fixed here as well.
2019-12-04 10:41:43 +01:00
Jan Beulich
3036c89919 x86: drop some stray/bogus DefaultSize
Insns permitting only GPR operands (and hence implicit sizing when
there's no suffix) don't ever have their DefaultSize attribute
inspected, so it shouldn't be there in the first place.

Additionally XBEGIN is like JMP, not CALL, and hence shouldn't be
converted to 32-bit operand size in .code16gcc mode. While the same is
true for SYSRET, it permitting more than one suffix makes it FLDENV-
like, and hence rather than dropping the attribute, for now add it to
the exclusion list to avoid it getting an operand size prefix emitted
in .code16gcc mode. (This will be dealt with later, perhaps together
with FLDENV and friends.)
2019-12-04 10:40:02 +01:00
Mihail Ionescu
8b301fbb61 Arm: Change CRC from fpu feature to archititectural extension
This patch changes the CRC extension to use the core feature bits instead
of the coproc/fpu feature bits.
CRC is not an fpu feature and it causes issues with the new fpu reset
patch (f439988037). CRC can be set using
the '.arch_extension' directive, which sets bits in the coproc bitfield. When
a '.fpu' directive is encountered, the CRC feature bit gets removed and
there is no way to set it back using '.fpu'.
With this patch, CRC will be marked in the feature core bits, which prevents
it from getting removed when setting/changing the fpu options.

gas/ChangeLog:

	* config/tc-arm.c (arm_ext_crc): New.
	(crc_ext_armv8): Remove.
	(insns): Rename crc_ext_armv8 to arm_ext_crc.
	(arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC.
	(armv8a_ext_table, armv8r_ext_table,
	arm_option_extension_value_table): Redefine the crc
	extension in terms of ARM_EXT2_CRC.
	* gas/testsuite/gas/arm/crc-ext.s: New.
	* gas/testsuite/gas/arm/crc-ext.d: New.

include/ChangeLog:

	* opcode/arm.h (ARM_EXT2_CRC): New extension feature
	to replace CRC_EXT_ARMV8.
	(CRC_EXT_ARMV8): Remove and mark bit as unused.
	(ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A,
	ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A,
	ARM_ARCH_V8_6A): Redefine using ARM_EXT2_CRC instead of
	CRC_EXT_ARMV8.

opcodes/ChangeLog:

	* opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
	Change the coproc CRC conditions to use the extension
	feature set, second word, base on ARM_EXT2_CRC.
2019-11-22 13:47:26 +00:00
Jan Beulich
6aa385b96f x86: drop redundant SYSCALL/SYSRET templates
The Cpu64 forms are no different in their attributes except for the CPU
flags; there's no need to key these off of anything other than
CpuSYSCALL even for the 64-bit forms. Dropping these improves the
diagnostic on SYSRETQ used in 32-bit code from "unsupported instruction
`sysret'" to "invalid instruction suffix for `sysret'".
2019-11-14 08:48:22 +01:00
Jan Beulich
0cfa3eb352 x86: fold individual Jump* attributes into a single Jump one
..., taking just 3 bits instead of 5. No two of them are used together.
2019-11-14 08:47:44 +01:00
Jan Beulich
6f2f06bea8 x86: make JumpAbsolute an insn attribute
... instead of an operand one: There's only ever one operand here
anyway.
2019-11-14 08:47:03 +01:00
Jan Beulich
601e856422 x86: make AnySize an insn attribute
... instead of an operand one. Which operand it applies to can be
determined from other operand properties, but as it turns out the only
place it is actually used at doesn't even need further qualification.
2019-11-14 08:46:19 +01:00
Jim Wilson
7722d40a9c RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.
We have to enable the f extension through -march or ELF attribute if we use the
FPR in .insn directive.  The behavior is same as the riscv_opcodes.

	2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
	opcodes/
	* riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
	INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
	use the floating point register (FPR).

	gas/
	* testsuite/gas/riscv/insn.d: Add the f extension to -march option.

Change-Id: I4f59d04c82673ef84c56ecd2659ad8ce164dd626
2019-11-12 16:13:00 -08:00
Mihail Ionescu
ce760a7620 [binutils][arm] Update the decoding of MVE VMOV, VMVN
This patch updates the decoding of the VMOV and VMVN instructions which depend on cmode.
Previously VMOV and VMVN with cmode 1101 were not allowed.
The cmode changes also required updating of the MVE conflict checking.
Now instructions with opcodes 0xef800d50 and 0xef800e70 correctly get decoded as VMOV
and VMVN, respectively.

2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>

	* opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
	cmode 1101.
	(is_mve_encoding_conflict): Update cmode conflict checks for
	MVE_VMVN_IMM.

2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>

	* gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd.
	* testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test.
	* testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.
2019-11-12 14:01:04 +00:00
Jan Beulich
51c8edf68b x86: fold EsSeg into IsString
EsSeg (a per-operand bit) is used with IsString (a per-insn attribute)
only. Extend the attribute to 2 bits, thus allowing to encode
- not a string insn,
- string insn with neither operand requiring use of %es:,
- string insn with 1st operand requiring use of %es:,
- string insn with 2nd operand requiring use of %es:,
which covers all possible cases, allowing to drop EsSeg.

The (transient) need to comment out the OTUnused #define did uncover an
oversight in the earlier OTMax -> OTNum conversion, which is being taken
care of here.
2019-11-12 09:09:31 +01:00
Jan Beulich
474da251bf x86: eliminate ImmExt abuse
Drop the remaining instances left in place by commit c3949f432f ("x86:
limit ImmExt abuse), now that we have a way to specify specific GPRs.

Take the opportunity and also introduce proper 16-bit forms of
applicable SVME insns as well as 1-operand forms of CLZERO.
2019-11-12 09:08:32 +01:00
Jan Beulich
75e5731b8f x86: introduce operand type "instance"
Special register "class" instances can't be combined with one another
(neither in templates nor in register entries), and hence it is not a
good use of resources (memory as well as execution time) to represent
them as individual bits of a bit field.

Furthermore the generalization becoming possible will allow
improvements to the handling of insns accepting only individual
registers as their operands.
2019-11-12 09:07:34 +01:00
Jan Beulich
91802f3cfe Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same register
This is just like for their umaxp/uminp and fmaxp/fminp counterparts.
2019-11-11 13:28:35 +01:00
Jan Beulich
4f5fc85d6c Arm64: fix build with old glibc
Some old glibc versions have string.h surface "index", which some
compilers then warn about if shadowed by a local variable. Re-use an
existing variable instead.
2019-11-11 13:27:47 +01:00
H.J. Lu
dc2be329b9 i386: Only check suffix in instruction mnemonic
We should check suffix in instruction mnemonic when matching instruction.
In Intel syntax, normally we check for memory operand size.  But the same
mnemonic with 2 different encodings can have the same memory operand
size and i.suffix is set to LONG_DOUBLE_MNEM_SUFFIX from memory operand
size in Intel syntax to distinguish them.  When there is no suffix in
mnemonic, we check LONG_DOUBLE_MNEM_SUFFIX in i.suffix for mnemonic
suffix.

gas/

	PR gas/25167
	* config/tc-i386.c (match_template): Don't check instruction
	suffix set from operand.
	* testsuite/gas/i386/code16.d: New file.
	* testsuite/gas/i386/code16.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run code16.
	* testsuite/gas/i386/x86-64-branch-4.l: Updated.

opcodes/

	PR gas/25167
	* i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
	* i386-tbl.h: Regenerated.
2019-11-08 09:31:17 -08:00
Jan Beulich
f74a630727 x86: convert RegMask and RegBND from bitfield to enumerator
This is to further shrink the operand type representation.
2019-11-08 09:06:24 +01:00
Jan Beulich
3528c362d9 x86: convert RegSIMD and RegMMX from bitfield to enumerator
This is to further shrink the operand type representation.
2019-11-08 09:05:36 +01:00
Jan Beulich
4a5c67ed84 x86: convert Control/Debug/Test from bitfield to enumerator
This is to further shrink the operand type representation.
2019-11-08 09:04:53 +01:00
Jan Beulich
00cee14fba x86: convert SReg from bitfield to enumerator
This is to further shrink the operand type representation.
2019-11-08 09:04:09 +01:00
Jan Beulich
bab6aec125 x86: introduce operand type "class"
Many operand types, in particular the various kinds of registers, can't
be combined with one another (neither in templates nor in register
entries), and hence it is not a good use of resources (memory as well as
execution time) to represent them as individual bits of a bit field.
2019-11-08 09:03:23 +01:00
Matthew Malcomson
1f4cd317b6 [gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]
Hi,

This patch is part of a series that adds support for Armv8.6-A
to binutils.

In this last patch, the new Data Gathering Hint mnemonic is introduced.

Committed on behalf of Mihail Ionescu.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* testsuite/gas/aarch64/dgh.s: New test.
	* testsuite/gas/aarch64/dgh.d: New test.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
	(aarch64_opcode_table): Add data gathering hint mnemonic.
	* opcodes/aarch64-dis-2.c: Account for new instruction.

Is it ok for trunk?

Regards,
Mihail
2019-11-07 17:23:53 +00:00
Matthew Malcomson
616ce08e1c [Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]
Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

This patch introduces the Matrix Multiply (Int8, F32, F64) extensions
to the arm backend.

The following Matrix Multiply instructions are added: vummla, vsmmla,
vusmmla, vusdot, vsudot[1].

[1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order

Committed on behalf of Mihail Ionescu.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* config/tc-arm.c (arm_ext_i8mm): New feature set.
	(do_vusdot): New.
	(do_vsudot): New.
	(do_vsmmla): New.
	(do_vummla): New.
	(insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics.
	(armv86a_ext_table): Add i8mm extension.
	(arm_extensions): Move bf16 extension to context sensitive table.
	(armv82a_ext_table, armv84a_ext_table, armv85a_ext_table):
	Move bf16 extension to context sensitive table.
	(armv86a_ext_table): Add i8mm extension.
	* doc/c-arm.texi: Document i8mm extension.
	* testsuite/gas/arm/i8mm.s: New test.
	* testsuite/gas/arm/i8mm.d: New test.
	* testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* opcode/arm.h (ARM_EXT2_I8MM): New feature macro.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.

Regression tested on arm-none-eabi.
Is this ok for trunk?

Regards,
Mihail
2019-11-07 17:20:08 +00:00
Matthew Malcomson
8382113fdb [binutils][aarch64] Matrix Multiply extension enablement [8/X]
Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

This patch introduces the Matrix Multiply (Int8, F32, F64) extensions
to the aarch64 backend.

The following instructions are added: {s/u}mmla, usmmla, {us/su}dot,
fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}.

Committed on behalf of Mihail Ionescu.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* config/tc-aarch64.c: Add new arch fetures to suppport the mm extension.
	(parse_operands): Add new operand.
	* testsuite/gas/aarch64/i8mm.s: New test.
	* testsuite/gas/aarch64/i8mm.d: New test.
	* testsuite/gas/aarch64/f32mm.s: New test.
	* testsuite/gas/aarch64/f32mm.d: New test.
	* testsuite/gas/aarch64/f64mm.s: New test.
	* testsuite/gas/aarch64/f64mm.d: New test.
	* testsuite/gas/aarch64/sve-movprfx-mm.s: New test.
	* testsuite/gas/aarch64/sve-movprfx-mm.d: New test.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_I8MM): New.
	(AARCH64_FEATURE_F32MM): New.
	(AARCH64_FEATURE_F64MM): New.
	(AARCH64_OPND_SVE_ADDR_RI_S4x32): New.
	(enum aarch64_insn_class): Add new instruction class "aarch64_misc" for
	instructions that do not require special handling.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
	aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
	aarch64_feature_f64mm): New feature sets.
	(INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
	F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
	instructions.
	(I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
	macros.
	(QL_MMLA64, OP_SVE_SBB): New qualifiers.
	(OP_SVE_QQQ): New qualifier.
	(INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
	F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
	the movprfx constraint.
	(aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
	(aarch64_opcode_table): Define new instructions smmla,
	ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod
	uzip{1/2}, trn{1/2}.
	* aarch64-opc.c (operand_general_constraint_met_p): Handle
	AARCH64_OPND_SVE_ADDR_RI_S4x32.
	(aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
	* aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
	Account for new instructions.
	* opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
	S4x32 operand.
	* aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.

Regression tested on arm-none-eabi.

Is it ok for trunk?

Regards,
Mihail
2019-11-07 17:11:52 +00:00
Matthew Malcomson
aab2c27d9f [binutils][arm] BFloat16 enablement [4/X]
Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

This patch introduces BFloat16 instructions to the arm backend.
The following BFloat16 instructions are added: vdot, vfma{l/t},
vmmla, vfmal{t/b}, vcvt, vcvt{t/b}.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-arm.c (arm_archs): Add armv8.6-a option.
	(cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a.
	* doc/c-arm.texi (-march): New armv8.6-a arch.
	* config/tc-arm.c (arm_ext_bf16): New feature set.
	(enum neon_el_type): Add NT_bfloat value.
	(B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder
	helpers.
	(BAD_BF16): New message.
	(parse_neon_type): Add bf16 type specifier.
	(enum neon_type_mask): Add N_BF16 type.
	(type_chk_of_el_type): Account for NT_bfloat.
	(el_type_of_type_chk): Account for N_BF16.
	(neon_three_args): Split out from neon_three_same.
	(neon_three_same): Part split out into neon_three_args.
	(CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour.
	(do_neon_cvt_1): Account for vcvt.bf16.f32.
	(do_bfloat_vmla): New.
	(do_mve_vfma): New function to deal with the mnemonic clash between the BF16
	vfmat and the MVE vfma in a VPT block with a 't'rue condition.
	(do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32.
	(do_vdot): New
	(do_vmmla): New
	(insns): Add vdot and vmmla mnemonics.
	(arm_extensions): Add "bf16" extension.
	* doc/c-arm.texi: Document "bf16" extension.
	* testsuite/gas/arm/attr-march-armv8_6-a.d: New test.
	* testsuite/gas/arm/bfloat16-bad.d: New test.
	* testsuite/gas/arm/bfloat16-bad.l: New test.
	* testsuite/gas/arm/bfloat16-bad.s: New test.
	* testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test.
	* testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test.
	* testsuite/gas/arm/bfloat16-cmdline-bad.d: New test.
	* testsuite/gas/arm/bfloat16-neon.s: New test.
	* testsuite/gas/arm/bfloat16-non-neon.s: New test.
	* testsuite/gas/arm/bfloat16-thumb-bad.d: New test.
	* testsuite/gas/arm/bfloat16-thumb-bad.l: New test.
	* testsuite/gas/arm/bfloat16-thumb.d: New test.
	* testsuite/gas/arm/bfloat16-vfp.d: New test.
	* testsuite/gas/arm/bfloat16.d: New test.
	* testsuite/gas/arm/bfloat16.s: New test.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A,
	ARM_ARCH_V8_6A): New.
	* opcode/arm.h (ARM_EXT2_BF16): New feature macro.
	(ARM_AEXT2_V8_6A): Include above macro in definition.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
	Armv8.6-A.
	(coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
	(neon_opcodes): Add bfloat SIMD instructions.
	(print_insn_coprocessor): Add new control character %b to print
	condition code without checking cp_num.
	(print_insn_neon): Account for BFloat16 instructions that have no
	special top-byte handling.

Regression tested on arm-none-eabi.

Is it ok for trunk?

Regards,
Mihail
2019-11-07 16:56:12 +00:00
Matthew Malcomson
33593eafc9 [Patch][binutils][arm] Create a new generic coprocessor array [3/10]
Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

Some generic instructions match a large range of encoding space (e.g.
stc, mcr, mrc).
Currently these instructions are in the coprocessor_opcodes array, which
means they are checked before many other instructions when disassembling
arm and thumb32 codes.

This patch moves the generic instructions into a separate array to be
checked later on.
This is done in order to avoid instruction conflict between the generic
instructions and newer ones -- this has already been seen with MVE, and
is also a problem with BFloat16.

One way to avoid the conflict could be to swap the search order between
coprocessor_opcodes and neon_opcodes.
We avoid this since it's a larger change that may introduce extra bugs
(that aren't caught by the testsuite).

We have decided against searching the generic array after searching the
arm specific and thumb32 specific arrays with a similar reasoning about
keeping the change small.

Regression tested with arm-none-linux-gnueabihf.

Committed on behalf of Mihail Ionescu.

opcodes/ChangeLog:

2019-10-29  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-10-29  Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (print_insn_coprocessor,
	print_insn_generic_coprocessor): Create wrapper functions around
	the implementation of the print_insn_coprocessor control codes.
	(print_insn_coprocessor_1): Original print_insn_coprocessor
	function that now takes which array to look at as an argument.
	(print_insn_arm): Use both print_insn_coprocessor and
	print_insn_generic_coprocessor.
	(print_insn_thumb32): As above.

Is it ok for trunk?

Regards,
Mihail
2019-11-07 16:55:29 +00:00
Matthew Malcomson
df6780137d [binutils][aarch64] Bfloat16 enablement [2/X]
Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

This patch introduces the following BFloat16 instructions to the
aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b],
bfcvtn2.

Committed on behalf of Mihail Ionescu.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (vectype_to_qualifier): Special case the
	S_2H operand qualifier.
	* doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions.
	* testsuite/gas/aarch64/bfloat16.d: New test.
	* testsuite/gas/aarch64/bfloat16.s: New test.
	* testsuite/gas/aarch64/illegal-bfloat16.d: New test.
	* testsuite/gas/aarch64/illegal-bfloat16.l: New test.
	* testsuite/gas/aarch64/illegal-bfloat16.s: New test.
	* testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test.
	* testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros.
	(AARCH64_ARCH_V8_6): Include BFloat16 feature macros.
	(enum aarch64_opnd_qualifier): Introduce new operand qualifier
	AARCH64_OPND_QLF_S_2H.
	(enum aarch64_insn_class): Introduce new class "bfloat16".
	(BFLOAT16_SVE_INSNC): New feature set for bfloat16
	instructions to support the movprfx constraint.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
	in reglane special case.
	* aarch64-dis-2.c (aarch64_opcode_lookup_1,
	aarch64_find_next_opcode): Account for new instructions.
	* aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
	in reglane special case.
	* aarch64-opc.c (struct operand_qualifier_data): Add data for
	new AARCH64_OPND_QLF_S_2H qualifier.
	* aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
	QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
	(aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve,
	aarch64_feature_bfloat16_bfmmla4): New feature sets.
	(BFLOAT_SVE, BFLOAT): New feature set macros.
	(BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros
	to define BFloat16 instructions.
	(aarch64_opcode_table): Define new instructions bfdot,
	bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
	bfcvtn2, bfcvt.

Regression tested on aarch64-elf.

Is it ok for trunk?

Regards,
Mihail
2019-11-07 16:42:36 +00:00
Matthew Malcomson
8ae2d3d9ea [gas][aarch64] Armv8.6-a option [1/X]
Hi,

This patch is part of a series that adds support for Armv8.6-A
to binutils.
This first patch adds the Armv8.6-A flag to binutils.
No instructions are behind it at the moment.

Commited on behalf of Mihail Ionescu.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (armv8.6-a): New arch.
	* doc/c-aarch64.texi (armv8.6-a): Document new arch.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_V8_6): New.
	(AARCH64_ARCH_V8_6): New.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-tbl.h (ARMV8_6): New macro.

Is it ok for trunk?

Regards,
Mihail
2019-11-07 16:21:17 +00:00
Jan Beulich
142861dfd5 x86: support further AMD Zen2 instructions
Both RDPRU and MCOMMIT have been publicly documented meanwhile:
https://www.amd.com/system/files/TechDocs/24594.pdf.
2019-11-07 09:29:14 +01:00
Jan Beulich
081e283faf x86: adjust register names printed for MONITOR/MWAIT
As the comments (here: almost, in the opcode table: fully) correctly
state - all register operands except MONITOR's address one are fixed
at 32 bit size. Don't print 64-bit registers there.

Also adjust x86-64-suffix.d's name such that it wouldn't be identical to
x86-64-rep-suffix.d's, but instead resemble that of its sibling
x86-64-suffix-intel.d.
2019-11-07 09:28:20 +01:00
Jan Beulich
c050c89a80 x86/Intel: drop IgnoreSize from operand-less MOVSD/CMPSD again
These were mistakenly added by d241b91073 ("x86/Intel: correct MOVSD and
CMPSD handling"). This addresses part of PR/gas 25167.
2019-11-07 09:27:16 +01:00
Jan Beulich
7abb8d8111 x86: fold OP_Mwaitx() into OP_Mwait()
There's no need to have separate functions, the difference can easily be
expressed using the function arguments.
2019-11-05 09:19:50 +01:00
Jan Beulich
267b8516f2 x86: split MONITORX/MWAITX entries
Both encodings do not ignore the 66/F3/F2 prefixes, so don't have the
disassembler ignore them either.
2019-11-05 09:19:10 +01:00
Jan Beulich
f8687e93a6 x86: consolidate disassembler enum naming a little
The original idea looks to have been for names to be composed in the
order that decoding gets done, which helps both reading and modifying
the code. Switch (back) to this model for some of the affected non-
vector insn enumerators.
2019-11-05 09:18:23 +01:00
Nick Clifton
5103274ffc Fix potential array overruns when disassembling corrupt v850 binaries.
* v850-dis.c (get_v850_sreg_name): New function.  Returns the name
	of a v850 system register.  Move the v850_sreg_names array into
	this function.
	(get_v850_reg_name): Likewise for ordinary register names.
	(get_v850_vreg_name): Likewise for vector register names.
	(get_v850_cc_name): Likewise for condition codes.
	* get_v850_float_cc_name): Likewise for floating point condition
	codes.
	(get_v850_cacheop_name): Likewise for cache-ops.
	(get_v850_prefop_name): Likewise for pref-ops.
	(disassemble): Use the new accessor functions.
2019-11-04 12:02:20 +00:00
Delia Burduv
1820262bc9 Modify the ARNM assembler to accept the omission of the immediate argument for the writeback form of the LDRAA and LDRAB mnemonics
This is a shorthand for the immediate argument being 0, as described here:
  https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldraa-ldrab-load-register-with-pointer-authentication

This is because the instructions still have a use with an immediate
argument of 0, unlike loads without the PAC functionality. Currently,
the mnemonics are

  LDRAA Xt, [Xn, #<simm10>]!
  LDRAB Xt, [Xn, #<simm10>]!

After this patch they become

  LDRAA Xt, [Xn {, #<simm10>}]!
  LDRAB Xt, [Xn {, #<simm10>}]!

gas	* config/tc-aarch64.c (parse_address_main): Accept the omission of
	the immediate argument for ldraa and ldrab as a shorthand for the
	immediate being 0.
	* testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test.
	* testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test.
	* testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the
	writeback form with no offset.
	* testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset
	error.

opcodes	* aarch64-opc.c (print_immediate_offset_address): Don't print the
	immediate for the writeback form of ldraa/ldrab if it is 0.
	* aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
	* aarch64-opc-2.c: Regenerated.
2019-10-30 13:23:35 +00:00
Jan Beulich
3cc17af589 x86: re-do "shorthand" handling
Now that the opcode table gets preprocessed, undo parts of commit
dc821c5f9a ("x86: replace Reg8, Reg16, Reg32, and Reg64"): Have the
preprocessor handle the expansion there, while making the expansions
explicit in i386-gen and the register table.
2019-10-30 09:07:40 +01:00
Jan Beulich
a2cebd03fa x86: slightly rearrange struct insn_template
This avoids holes between the individual fields, (potentially) shrinking
the overall template table size by 4 bytes per entry.
2019-10-30 09:06:42 +01:00
Jan Beulich
507916b855 x86: drop stray W
The flag is used to indicate opcodes which can be switched between byte
and word/dword/qword forms (in a "canonical" way). Obviously it's quite
odd then to see it on insns not allowing for byte operands in the first
place. As a result the opcode bytes need to be adjusted accordingly,
which includes comparisons done in optimize_encoding().

To make re-introduction of such issues less likely have i386-gen
diagnose it (in a generally non-fatal way for now).
2019-10-30 09:05:46 +01:00
Nick Clifton
efea62b446 Fix array overrun when disassembling corrupt TIC30 binaries.
* tic30-dis.c (print_branch): Correct size of operand array.
2019-10-29 15:35:30 +00:00
Nick Clifton
9adb259150 Fix a potential illegal array access in the D30V disassembler.
* d30v-dis.c (print_insn): Check that operand index is valid
	before attempting to access the operands array.
2019-10-29 10:25:09 +00:00
Nick Clifton
993a00a986 Prevent a left shift by a negative value when disassembling IA64 binaries.
* ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
	locating the bit to be tested.
2019-10-29 10:01:27 +00:00
Nick Clifton
66a66a17f4 Fix array overruns in the S12Z disassembler.
* s12z-dis.c (opr_emit_disassembly): Check for illegal register
	values.
	(shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
	(print_insn_s12z):  Check for illegal size values.
2019-10-29 09:17:39 +00:00
Nick Clifton
1ee3542c0a Fix potentially illegal shift and assign operation in CSKY disassembler.
* csky-dis.c (csky_chars_to_number): Check for a negative
	count. Use an unsigned integer to construct the return value.
2019-10-28 16:45:55 +00:00
Nick Clifton
bbf9a0b5ee Fix buffer overrun in TIC30 disassembler.
* tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
	operand buffer.  Set value to 15 not 13.
	(get_register_operand): Use OPERAND_BUFFER_LEN.
	(get_indirect_operand): Likewise.
	(print_two_operand): Likewise.
	(print_three_operand): Likewise.
	(print_oar_insn): Likewise.
2019-10-28 16:15:34 +00:00
Nick Clifton
d1e304bc27 Stop potential illegal memory access in the NS32K disassembler.
* ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
	(bit_extract_simple): Likewise.
	(bit_copy): Likewise.
	(pirnt_insn_ns32k): Ensure that uninitialised elements in the
	index_offset array are not accessed.
2019-10-28 15:44:23 +00:00
Nick Clifton
dee334510f Prevent an illegal memory access in the xgate disassembler.
* xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
	operand.
2019-10-28 15:06:32 +00:00
Nick Clifton
27cee81d06 Fix potential undefined behaviour in the RX disassembler.
* rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
	access to opcodes.op array element.
2019-10-25 16:10:04 +01:00
Nick Clifton
de6d8dc25c Fix typo in RX disassembler error messages.
* rx-dis.c (get_register_name): Fix spelling typo in error
	message.
	(get_condition_name, get_flag_name, get_double_register_name)
	(get_double_register_high_name, get_double_register_low_name)
	(get_double_control_register_name, get_double_condition_name)
	(get_opsize_name, get_size_name): Likewise.
2019-10-23 10:17:21 +01:00
Nick Clifton
6207ed2877 Prevent more potential illegal memory accesses in the RX disassembler.
* rx-dis.c (get_size_name): New function.  Provides safe
	access to name array.
	(get_opsize_name): Likewise.
	(print_insn_rx): Use the accessor functions.
2019-10-22 12:01:45 +01:00
Nick Clifton
12234dfd5f Fix potential illegal memory access when disassembling corrupt RX binaries.
opcodes * rx-dis.c (get_register_name): New function.  Provides safe
	access to name array.
	(get_condition_name, get_flag_name, get_double_register_name)
	(get_double_register_high_name, get_double_register_low_name)
	(get_double_control_register_name, get_double_condition_name):
	Likewise.
	(print_insn_rx): Use the accessor functions.
2019-10-16 12:56:58 +01:00
Nick Clifton
1d3787499d Fix the disassembly of the LDS and STS instructions of the AVR architecture.
PR 25041
opcodes	* avr-dis.c (avr_operand): Fix construction of address for lds/sts
	instructions.

gas	* testsuite/gas/avr/pr25041.s: New test.
	* testsuite/gas/avr/pr25041.d: New test driver.
2019-10-09 13:48:06 +01:00
Jan Beulich
d241b91073 x86/Intel: correct MOVSD and CMPSD handling
First and foremost the EsSeg attribute was misplaced for CMPSD. Then
both it and MOVSD were lacking Dword on both of their operands.
Finally string insns with multiple operands and requiring use of ES:
had the wrong operand number reported in the diagnostic.
2019-10-07 08:38:01 +02:00
Alan Modra
f5c5b7c124 m68k bfd.h tidy
bfd/
	* bfd-in.h: Move m68k function declaration..
	* cpu-m68k.h: ..to here, new file..
	* elf32-m68k.h: ..and here, new file.
	* elf32-m68k.c: Include cpu-m68k.h and elf32-m68k.h.
	* bfd-in2.h: Regenerate.
ld/
	* emultempl/m68kelf.em: Include elf32-m68k.h.
opcodes/
	* m68k-dis.c: Include cpu-m68k.h
2019-09-23 10:27:22 +09:30
Alan Modra
7beeaeb8c6 mips bfd.h tidy
bfd/
	* bfd-in.h: Move mips function declaration to..
	* elfxx-mips.h: ..here.
	* bfd-in2.h: Regenerate.
opcodes/
	* mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
	"elf/mips.h" earlier.
2019-09-23 10:27:20 +09:30
Jan Beulich
3f9aad111c x86-64: fix handling of PUSH/POP of segment register
Commit 21df382b91 ("x86: fold SReg{2,3}") went too far: Folding 64-bit
PUSH/POP templates into non-64-bit ones isn't correct, due to the
different operand widths, and hence suffixes permitted. Restore the
separate templates.

Add tests of PUSH/POP with q suffix and %fs/%gs operands to the
testsuite. While doing so also add PUSHF/POPF ones _without_ suffix.
2019-09-20 10:18:15 +02:00
Alan Modra
fd3619828e bfd_section_* macros
This large patch removes the unnecessary bfd parameter from various
bfd section macros and functions.  The bfd is hardly ever used and if
needed for the bfd_set_section_* or bfd_rename_section functions can
be found via section->owner except for the com, und, abs, and ind
std_section special sections.  Those sections shouldn't be modified
anyway.

The patch also removes various bfd_get_section_<field> macros,
replacing their use with bfd_section_<field>, and adds
bfd_set_section_lma.  I've also fixed a minor bug in gas where
compressed section renaming was done directly rather than calling
bfd_rename_section.  This would have broken bfd_get_section_by_name
and similar functions, but that hardly mattered at such a late stage
in gas processing.

bfd/
	* bfd-in.h (bfd_get_section_name, bfd_get_section_vma),
	(bfd_get_section_lma, bfd_get_section_alignment),
	(bfd_get_section_size, bfd_get_section_flags),
	(bfd_get_section_userdata): Delete.
	(bfd_section_name, bfd_section_size, bfd_section_vma),
	(bfd_section_lma, bfd_section_alignment): Lose bfd parameter.
	(bfd_section_flags, bfd_section_userdata): New.
	(bfd_is_com_section): Rename parameter.
	* section.c (bfd_set_section_userdata, bfd_set_section_vma),
	(bfd_set_section_alignment, bfd_set_section_flags, bfd_rename_section),
	(bfd_set_section_size): Delete bfd parameter, rename section parameter.
	(bfd_set_section_lma): New.
	* bfd-in2.h: Regenerate.
	* mach-o.c (bfd_mach_o_init_section_from_mach_o): Delete bfd param,
	update callers.
	* aoutx.h, * bfd.c, * coff-alpha.c, * coff-arm.c, * coff-mips.c,
	* coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c,
	* compress.c, * ecoff.c, * elf-eh-frame.c, * elf-hppa.h,
	* elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-properties.c,
	* elf-s390-common.c, * elf-vxworks.c, * elf.c, * elf32-arc.c,
	* elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c,
	* elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c,
	* elf32-d10v.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c,
	* elf32-ft32.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c,
	* elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c,
	* elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c, * elf32-mcore.c,
	* elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c,
	* elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c,
	* elf32-nios2.c, * elf32-or1k.c, * elf32-ppc.c, * elf32-pru.c,
	* elf32-rl78.c, * elf32-rx.c, * elf32-s390.c, * elf32-score.c,
	* elf32-score7.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c,
	* elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c,
	* elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c,
	* elf64-bpf.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mmix.c,
	* elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c,
	* elflink.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c,
	* elfxx-aarch64.c, * elfxx-mips.c, * elfxx-sparc.c,
	* elfxx-tilegx.c, * elfxx-x86.c, * i386msdos.c, * linker.c,
	* mach-o.c, * mmo.c, * opncls.c, * pdp11.c, * pei-x86_64.c,
	* peicode.h, * reloc.c, * section.c, * syms.c, * vms-alpha.c,
	* xcofflink.c: Update throughout for bfd section macro and function
	changes.
binutils/
	* addr2line.c, * bucomm.c, * coffgrok.c, * dlltool.c, * nm.c,
	* objcopy.c, * objdump.c, * od-elf32_avr.c, * od-macho.c,
	* od-xcoff.c, * prdbg.c, * rdcoff.c, * rddbg.c, * rescoff.c,
	* resres.c, * size.c, * srconv.c, * strings.c, * windmc.c: Update
	throughout for bfd section macro and function changes.
gas/
	* as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c,
	* read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c,
	* config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c,
	* config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c,
	* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
	* config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c,
	* config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c,
	* config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c,
	* config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c,
	* config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c,
	* config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c,
	* config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c,
	* config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c,
	* config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c,
	* config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c,
	* config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c,
	* config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c,
	* config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c,
	* config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c,
	* config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c,
	* config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c,
	* config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c,
	* config/tc-xtensa.c, * config/tc-z8k.c: Update throughout for
	bfd section macro and function changes.
	* write.c (compress_debug): Use bfd_rename_section.
gdb/
	* aarch64-linux-tdep.c, * arm-tdep.c, * auto-load.c,
	* coff-pe-read.c, * coffread.c, * corelow.c, * dbxread.c,
	* dicos-tdep.c, * dwarf2-frame.c, * dwarf2read.c, * elfread.c,
	* exec.c, * fbsd-tdep.c, * gcore.c, * gdb_bfd.c, * gdb_bfd.h,
	* hppa-tdep.c, * i386-cygwin-tdep.c, * i386-fbsd-tdep.c,
	* i386-linux-tdep.c, * jit.c, * linux-tdep.c, * machoread.c,
	* maint.c, * mdebugread.c, * minidebug.c, * mips-linux-tdep.c,
	* mips-sde-tdep.c, * mips-tdep.c, * mipsread.c, * nto-tdep.c,
	* objfiles.c, * objfiles.h, * osabi.c, * ppc-linux-tdep.c,
	* ppc64-tdep.c, * record-btrace.c, * record-full.c, * remote.c,
	* rs6000-aix-tdep.c, * rs6000-tdep.c, * s390-linux-tdep.c,
	* s390-tdep.c, * solib-aix.c, * solib-dsbt.c, * solib-frv.c,
	* solib-spu.c, * solib-svr4.c, * solib-target.c,
	* spu-linux-nat.c, * spu-tdep.c, * symfile-mem.c, * symfile.c,
	* symmisc.c, * symtab.c, * target.c, * windows-nat.c,
	* xcoffread.c, * cli/cli-dump.c, * compile/compile-object-load.c,
	* mi/mi-interp.c: Update throughout for bfd section macro and
	function changes.
	* gcore (gcore_create_callback): Use bfd_set_section_lma.
	* spu-tdep.c (spu_overlay_new_objfile): Likewise.
gprof/
	* corefile.c, * symtab.c: Update throughout for bfd section
	macro and function changes.
ld/
	* ldcref.c, * ldctor.c, * ldelf.c, * ldlang.c, * pe-dll.c,
	* emultempl/aarch64elf.em, * emultempl/aix.em,
	* emultempl/armcoff.em, * emultempl/armelf.em,
	* emultempl/cr16elf.em, * emultempl/cskyelf.em,
	* emultempl/m68hc1xelf.em, * emultempl/m68kelf.em,
	* emultempl/mipself.em, * emultempl/mmix-elfnmmo.em,
	* emultempl/mmo.em, * emultempl/msp430.em,
	* emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em,
	* emultempl/ppc64elf.em, * emultempl/xtensaelf.em: Update
	throughout for bfd section macro and function changes.
libctf/
	* ctf-open-bfd.c: Update throughout for bfd section macro changes.
opcodes/
	* arc-ext.c: Update throughout for bfd section macro changes.
sim/
	* common/sim-load.c, * common/sim-utils.c, * cris/sim-if.c,
	* erc32/func.c, * lm32/sim-if.c, * m32c/load.c, * m32c/trace.c,
	* m68hc11/interp.c, * ppc/hw_htab.c, * ppc/hw_init.c,
	* rl78/load.c, * rl78/trace.c, * rx/gdb-if.c, * rx/load.c,
	* rx/trace.c: Update throughout for bfd section macro changes.
2019-09-19 09:40:13 +09:30
Simon Marchi
e0b2a78c83 Re-generate many configure and Makefile.in files
I get some spurious changes when running autoconf/automake for various
projects in the tree.  This is likely because they were generated using
distro-patched tools last time.

I ran `autoreconf -f` in the various automake projects of the
binutils-gdb tree, and this is the result.  The tools I am using have
been compiled from source, from the upstream release.

bfd/ChangeLog:

	* Makefile.in: Re-generate.
	* configure: Re-generate.
	* doc/Makefile.in: Re-generate.

binutils/ChangeLog:

	* Makefile.in: Re-generate.
	* configure: Re-generate.
	* doc/Makefile.in: Re-generate.

gas/ChangeLog:

	* Makefile.in: Re-generate.
	* configure: Re-generate.
	* doc/Makefile.in: Re-generate.

gold/ChangeLog:

	* testsuite/Makefile.in: Re-generate.

gprof/ChangeLog:

	* Makefile.in: Re-generate.
	* configure: Re-generate.

ld/ChangeLog:

	* Makefile.in: Re-generate.
	* configure: Re-generate.

opcodes/ChangeLog:

	* Makefile.in: Re-generate.
	* configure: Re-generate.
2019-09-18 09:09:15 -04:00
Jim Wilson
7e9ad3a35c RISC-V: Gate opcode tables by enum rather than string.
Generalize opcode arch dependencies so that we can support the
overlapping B extension Zb* subsets.

	2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
	gas/
	* config/tc-riscv.c (riscv_multi_subset_supports): Handle
	insn_class enum rather than subset char string.
	(riscv_ip): Update call to riscv_multi_subset_supports.
	include/
	* opcode/riscv.h (riscv_insn_class): New enum.
	* opcode/riscv.h (struct riscv_opcode): Change
	subset field to insn_class field.
	opcodes/
	* riscv-opc.c (riscv_opcodes): Change subset field
	to insn_class field for all instructions.
	(riscv_insn_types): Likewise.
2019-09-17 17:59:08 -07:00
Phil Blundell
bb6959602b Update version to 2.33.50 and regenerate configure scripts. 2019-09-16 11:03:53 +01:00
Miod Vallat
8063ab7e37 Use the correct alias for the M68K tdiv instruction.
PR 24982
	* m68k-opc.c: Correct aliases for tdivsl and tdivul.
2019-09-10 17:17:01 +01:00
Phil Blundell
60391a255b Add markers for 2.33 branch to NEWS and ChangeLog files. 2019-09-09 10:27:40 +01:00
Nick Clifton
f44b758d31 Fix buffer underrun bug in the TI C30 disassembler.
PR 24961
	* tic30-dis.c (get_indirect_operand): Check for bufcnt being
	greater than zero before indexing via (bufcnt -1).
2019-09-03 15:37:12 +01:00
Nick Clifton
1e4b5e7d35 Fix a potential buffer overrun in the MMIX disassembler when processing a corrupt input file.
PR 24958
	* mmix-dis.c (MAX_REG_NAME_LEN): Define.
	(MAX_SPEC_REG_NAME_LEN): Define.
	(struct mmix_dis_info): Use defined constants for array lengths.
	(get_reg_name): New function.
	(get_sprec_reg_name): New function.
	(print_insn_mmix): Use new functions.
2019-09-03 09:53:25 +01:00
Srinath Parvathaneni
c4a23bf878 Add support for the MVE VMOV instruction to the ARM assembler. This instruction copies the value of one vector register to another vector register. The patch also modifies the decoding of VORR instruction which is effecting decoding of VMOV instruction.
gas     * config/tc-arm.c (parse_neon_mov): Add check to accept vector
	register to both the arguments in VMOV instruction.
	* testsuite/gas/arm/mve-vmov-1.d: Modify.
	* testsuite/gas/arm/mve-vmov-1.s: Likewise.
	* testsuite/gas/arm/mve-vorr.d: Likewise.

opcodes	* arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
	(is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
	(print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
2019-08-27 12:08:21 +01:00
Kyrylo Tkachov
a051e2f3e0 [AArch64][gas] Update MTE system register encodings
The MTE specification adjusted the encoding of the TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12 system registers.
This patch brings binutils up to date.

The references for the encodings are at:
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsre0_el1 (also contains TFSR_EL12 description)
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el1
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el2
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el3

Tested check-gas for aarch64-none-elf.

opcodes/

	* aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
	tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
	(aarch64_sys_reg_supported_p): Update checks for the above.

gas/

    * testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly for
    tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.
2019-08-22 10:20:01 +01:00
Srinath Parvathaneni
08132bdd87 Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.
This is a change to the first published specifications [1][a] but since there is no hardware
out there that uses the old instructions we do not want to support the old variant.
This changes are done based on the latest published specifications [1][b].

[1] https://developer.arm.com/architectures/cpu-architecture/m-profile/docs/ddi0553/latest/armv81-m-architecture-reference-manual
    [a] version bf
    [b] version bh

gas	* config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64.
	(po_imm1_or_imm2_or_fail): Marco to check the immediate is either of
        48 or 64.
	(parse_operands): Add case OP_I48_I64.
	(do_mve_scalar_shift1): Add function to encode the MVE shift
        instructions with 4 arguments.
	* testsuite/gas/arm/mve-shift-bad.l: Modify.
	* testsuite/gas/arm/mve-shift-bad.s: Likewise.
	* testsuite/gas/arm/mve-shift.d: Likewise.
	* testsuite/gas/arm/mve-shift.s: Likewise.

opcodes	* arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
	cases MVE_SQRSHRL and MVE_UQRSHLL.
	(print_insn_mve): Add case for specifier 'k' to check
	specific bit of the instruction.
2019-08-12 17:17:18 +01:00
Phillipe Antoine
d88bdcb4a5 Prevent objdump from aborting when asked to disassemble an unknown type of ARC binary file.
PR 24854
	* arc-dis.c (arc_insn_length): Return 0 rather than aborting when
	encountering an unknown machine type.
	(print_insn_arc): Handle arc_insn_length returning 0.  In error
	cases return -1 rather than calling abort.
2019-08-07 17:22:29 +01:00
Jan Beulich
bc750500af x86: drop stray FloatMF
The flag is supposed to be used in templates which allow for both a
"short" and a "long" format memory operand. Drop it from templates not
matching this pattern. In the control/status word cases it was (ab)used
in place of the intended IgnoreSize.
2019-08-07 10:46:52 +02:00
Barnaby Wilks
23d188c74e Removes support in the ARM assembler for the unsigned variants of the VQ(R)DMLAH and VQ(R)DMLASH MVE instructions.
Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH
instructions, however the Armv8.1-M Mainline specification states that these functions only
have signed variations (.s32, .s16 and .s8 suffixes).
This is documented here:
https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183

gas	* config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro.
	(do_neon_qrdmlah): Use N_S_32 macro.
	* testsuite/gas/arm/mve-vqdmlah-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmlah-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmlah-bad.s: New test.
	* testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests.
	* testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests.
	* testsuite/gas/arm/mve-vqdmlash-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmlash-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmlash-bad.s: New test.
	* testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests.
	* testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests.

opcodes	* arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
	instructions.
2019-08-05 12:43:38 +01:00
Jim Wilson
c0d6f62fce RISC-V: Fix minor issues with FP csr instructions.
Mel Chen <mel.chen@sifive.com>
	gas/
	* testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
	alias instructions.
	* testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with
	-Mno-aliases.
	* testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.
	* testsuite/gas/riscv/priv-reg.d: Update.
	opcodes/
	* riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
	fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
	* riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
	fscsr.
2019-07-30 14:42:16 -07:00
Claudiu Zissulescu
0f3f71676a [ARC] Update disassembler opcode selection
New instruction are added, and some of them are overlapping. Update
disassembler to correctly recognize them. Introduce nps400 option.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
	and MPY class instructions.
	(parse_option): Add nps400 option.
	(print_arc_disassembler_options): Add nps400 info.

gas/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/nps400-6.d: Update test.
2019-07-24 16:52:23 +03:00
Claudiu Zissulescu
7e126ba31a [ARC] Update ARC opcode table
Update ARC opcode table by cleaning up invalid instructions, and fixing wrong encodings.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-ext-tbl.h (bspeek): Remove it, added to main table.
	(bspop): Likewise.
	(modapp): Likewise.
	* arc-opc.c (RAD_CHK): Add.
	* arc-tbl.h: Regenerate.

include/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* include/opcode/arc.h (FASTMATH): Add.
	(SWITCH): Likewise.
2019-07-24 16:46:01 +03:00
Kyrylo Tkachov
a028026d2f [AArch64] Add support for GMID_EL1 register for +memtag
We're missing support for the GMID_EL1 system register from the Memory Tagging Extension in binutils.
This is specified at:
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/gmid_el1

This simple patch adds the support for this read-only register.
Tested make check on gas.
2019-07-23 15:54:54 +01:00
Nick Clifton
ac79ff9ed2 Add Changelog entry missing from previous delta.
2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>

	* arm-dis.c (is_mve_unpredictable): Stop marking some MVE
	instructions as UNPREDICTABLE.
2019-07-23 09:47:06 +01:00
Jose E. Marchesi
231097b03a cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassembler
This patch changes the eBPF CPU description to prefer the register
names %r0 and %r6 instead of %a and %ctx when disassembling.  This
matches better with the current practice, vs. cBPF.

It also updates the GAS tests in order to reflect this change.
Tested in a x86_64 host.

cpu/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
	%a and %ctx.

opcodes/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerated.

gas/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx.
	* testsuite/gas/bpf/lddw-be.d: Likewise.
	* testsuite/gas/bpf/lddw.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise.
2019-07-19 15:35:43 +02:00
Jan Beulich
1d942ae908 x86: drop stale Mem enumerator
This was supposed to also be removed by c48dadc9a8 ('x86: drop "mem"
operand type attribute').  It's odd enough that this hasn't caused
build issues, considering the careful use of OTunused (apparently to
avoid "missing initializer" warnings).

To avoid such happening again introduce compile time consistency
checks.
2019-07-17 09:15:49 +02:00