Commit Graph

14 Commits

Author SHA1 Message Date
Alan Modra
b3adc24a07 Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
Jim Wilson
2dc8dd17cd RISC-V: Support ELF attribute for gas and readelf.
2019-01-16  Kito Cheng  <kito@andestech.com>
		    Nelson Chu  <nelson@andestech.com>

	bfd/
	* elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New.
	(elf_backend_obj_attrs_vendor): Define.
	(elf_backend_obj_attrs_section_type): Likewise.
	(elf_backend_obj_attrs_section): Likewise.
	(elf_backend_obj_attrs_arg_type): Define as
	riscv_elf_obj_attrs_arg_type.
	* elfxx-riscv.c (riscv_estimate_digit): New.
	(riscv_estimate_arch_strlen1): Likewise.
	(riscv_estimate_arch_strlen): Likewise.
	(riscv_arch_str1): Likewise.
	(riscv_arch_str): Likewise.
	* elfxx-riscv.h (riscv_arch_str): Declare.
	binutils/
	* readelf.c (get_riscv_section_type_name): New function.
	(get_section_type_name): Add handler for RISC-V.
	(riscv_attr_tag_t): Declare.
	(riscv_attr_tag): New.
	(display_riscv_attribute): New function.
	(process_attributes): Add handler for RISC-V.
	* testsuite/binutils-all/strip-3.d: Remove .riscv.attribute
	section.
	gas/
	* config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined.
	(riscv_set_options): Add `arch_attr` field.
	(riscv_opts): Set default value for arch_attr.
	(riscv_write_out_arch_attr): New.
	(riscv_set_public_attributes): Likewise.
	(riscv_md_end): Likewise.
	(riscv_convert_symbolic_attribute): Likewise.
	(s_riscv_attribute): Likewise.
	(explicit_arch_attr): Likewise.
	(riscv_pseudo_table): Add .attribute to the table.
	(options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR
	enumeration constants.
	(md_longopts): Add `march-attr' and `mno-arch-attr' options.
	(md_parse_option): Handle the new options.
	(md_show_usage): Document the `march-attr' option.
	* config/tc-riscv.h (md_end): Define as riscv_md_end
	(riscv_md_end): Declare.
	(CONVERT_SYMBOLIC_ATTRIBUTE): Define as
	riscv_convert_symbolic_attribute.
	(riscv_convert_symbolic_attribute): Declare.
	(start_assemble): Declare.
	* testsuite/gas/elf/elf.exp: Adjust test case for section2.e.
	* testsuite/gas/elf/section2.e-riscv: New.
	* testsuite/gas/riscv/attribute-01.d: New test
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-04.s: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-05.s: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-06.s: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-07.s: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-08.s: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.s: Likewise.
	* testsuite/gas/riscv/empty.l: Likewise.
	* doc/c-riscv.texi (.attribute): Add documentation.
	* configure.ac (--enable-default-riscv-attribute): New options.
	* configure: Re-generate.
	* config.in: Re-generate.
	include/
	* elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define.
	(Tag_RISCV_arch): Likewise.
	(Tag_RISCV_priv_spec): Likewise.
	(Tag_RISCV_priv_spec_minor): Likewise.
	(Tag_RISCV_priv_spec_revision): Likewise.
	(Tag_RISCV_unaligned_access): Likewise.
	(Tag_RISCV_stack_align): Likewise.
2019-01-16 13:14:59 -08:00
Alan Modra
827041555a Update year range in copyright notice of binutils files 2019-01-01 22:06:53 +10:30
Andrew Burgess
884b49e3a9 opcodes/riscv: Hide '.L0 ' fake symbols
The RISC-V assembler generates fake labels with the name '.L0 ' as
part of the debug information (see
gas/config/tc-riscv.h:FAKE_LABEL_NAME).

The problem is that currently, when disassembling an object file, the
output looks like this (this is an example from the GDB testsuite, but
is pretty representative of anything with debug information):

  000000000000001e <main>:
    1e:   7179                    addi    sp,sp,-48
    20:   f406                    sd      ra,40(sp)
    22:   f022                    sd      s0,32(sp)
    24:   1800                    addi    s0,sp,48

  0000000000000026 <.L0 >:
    26:   87aa                    mv      a5,a0
    28:   feb43023                sd      a1,-32(s0)
    2c:   fcc43c23                sd      a2,-40(s0)
    30:   fef42623                sw      a5,-20(s0)

  0000000000000034 <.L0 >:
    34:   fec42783                lw      a5,-20(s0)
    38:   0007871b                sext.w  a4,a5
    3c:   678d                    lui     a5,0x3
    3e:   03978793                addi    a5,a5,57 # 3039 <.LASF30+0x2a9d>
    42:   02f71463                bne     a4,a5,6a <.L0 >

  0000000000000046 <.L0 >:
    46:   000007b7                lui     a5,0x0
    4a:   0007b783                ld      a5,0(a5) # 0 <need_malloc>
    4e:   6f9c                    ld      a5,24(a5)

  0000000000000050 <.L0 >:
    50:   86be                    mv      a3,a5
    52:   466d                    li      a2,27
    54:   4585                    li      a1,1
    56:   000007b7                lui     a5,0x0
    5a:   00078513                mv      a0,a5
    5e:   00000097                auipc   ra,0x0
    62:   000080e7                jalr    ra # 5e <.L0 +0xe>

  0000000000000066 <.L0 >:
    66:   4785                    li      a5,1
    68:   a869                    j       102 <.L0 >

  000000000000006a <.L0 >:
    6a:   000007b7                lui     a5,0x0
    6e:   00078513                mv      a0,a5
    72:   00000097                auipc   ra,0x0
    76:   000080e7                jalr    ra # 72 <.L0 +0x8>

The frequent repeated '.L0 ' labels are pointless, as they are
non-unique there's no way to match a use of '.L0 ' to its appearence
in the output, so we'd be better off just not printing it at all.
That's what this patch does by defining a 'symbol_is_valid' method for
RISC-V.  With this commit, the same disassembly now looks like this:

  000000000000001e <main>:
    1e:   7179                    addi    sp,sp,-48
    20:   f406                    sd      ra,40(sp)
    22:   f022                    sd      s0,32(sp)
    24:   1800                    addi    s0,sp,48
    26:   87aa                    mv      a5,a0
    28:   feb43023                sd      a1,-32(s0)
    2c:   fcc43c23                sd      a2,-40(s0)
    30:   fef42623                sw      a5,-20(s0)
    34:   fec42783                lw      a5,-20(s0)
    38:   0007871b                sext.w  a4,a5
    3c:   678d                    lui     a5,0x3
    3e:   03978793                addi    a5,a5,57 # 3039 <.LASF30+0x2a9d>
    42:   02f71463                bne     a4,a5,6a <.L4>
    46:   000007b7                lui     a5,0x0
    4a:   0007b783                ld      a5,0(a5) # 0 <need_malloc>
    4e:   6f9c                    ld      a5,24(a5)
    50:   86be                    mv      a3,a5
    52:   466d                    li      a2,27
    54:   4585                    li      a1,1
    56:   000007b7                lui     a5,0x0
    5a:   00078513                mv      a0,a5
    5e:   00000097                auipc   ra,0x0
    62:   000080e7                jalr    ra # 5e <main+0x40>
    66:   4785                    li      a5,1
    68:   a869                    j       102 <.L5>

  000000000000006a <.L4>:
    6a:   000007b7                lui     a5,0x0
    6e:   00078513                mv      a0,a5
    72:   00000097                auipc   ra,0x0
    76:   000080e7                jalr    ra # 72 <.L4+0x8>

In order to share the fake label between the assembler and the
libopcodes library, I've added some new defines RISCV_FAKE_LABEL_NAME
and RISCV_FAKE_LABEL_CHAR in include/opcode/riscv.h.  I could have
just moved FAKE_LABEL_NAME to the include file, however, I thnk this
would be confusing, someone working on the assembler would likely not
expect to find FAKE_LABEL_NAME defined outside of the assembler source
tree.  By introducing the RISCV_FAKE_LABEL_* defines I can leave the
assembler standard FAKE_LABEL_ defines in the assembler source, but
still share the RISCV_FAKE_LABEL_* with libopcodes.

gas/ChangeLog:

	* config/tc-riscv.h (FAKE_LABEL_NAME): Define as
	RISCV_FAKE_LABEL_NAME.
	(FAKE_LABEL_CHAR): Define as RISCV_FAKE_LABEL_CHAR.

include/ChangeLog:

	* dis-asm.h (riscv_symbol_is_valid): Declare.
	* opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define.
	(RISCV_FAKE_LABEL_CHAR): Define.

opcodes/ChangeLog:

        * disassembler.c (disassemble_init_for_target): Add RISC-V
        initialisation.
        * riscv-dis.c (riscv_symbol_is_valid): New function.
2018-12-06 09:40:56 +00:00
Jim Wilson
e80ae1906b RISC-V: Fix .align handling when .option norelax.
gas/
	PR gas/23219
	* config/tc-riscv.c (riscv_frag_align_code): Move frag_more call after
	!riscv_opts.relax check.
	(riscv_handle_align): Rewrite !riscv_opts.relax support.
	* config/tc-riscv (MAX_MEM_FOR_RS_ALIGN_CODE): Update.
	* testsuite/gas/riscv/no-relax-align.d: New
	* testsuite/gas/riscv/no-relax-align.s: New
	* testsuite/gas/riscv/no-relax-align-2.d: New
	* testsuite/gas/riscv/no-relax-align-2.s: New
2018-05-24 10:35:59 -07:00
Alan Modra
219d1afa89 Update year range in copyright notice of binutils files 2018-01-03 17:49:56 +10:30
Jim Wilson
2469b3c584 Riscv ld-elf/stab failure and fake label cleanup.
* as.c: Include write.h.
	(common_emul_init): Use FAKE_LABEL_NAME.
	* ecoff.c (add_file, ecoff_directive_end, ecoff_directive_loc):
	Likewise.
	(ecoff_build_symbols): Use FAKE_LABEL_CHAR.
	* expr.c (get_symbol_name): Use FAKE_LABEL_CHAR.  Accept only if
	input_from_string is TRUE.
	* read.c (input_from_string): New.
	(read_symbol_name): Use FAKE_LABEL_CHAR.  Accept only if
	input_from_string is TRUE.
	(temp_ilp): Set input_from_string to TRUE.
	(restore_ilp): Set input_from_string to FALSE.
	* read.h (input_from_string): Declare.
	* symbols.c: Include write.h
	(S_IS_LOCAL): Check for FAKE_LABEL_CHAR.
	(symbol_relc_make_sym): Fix comment refering to default fake label
	string.
	* write.h (FAKE_LABEL_CHAR): New.
	* config/tc-riscv.h (FAKE_LABEL_CHAR): Define.
	* testsuite/gas/all/err-fakelabel.s: New.
2017-11-22 11:20:48 -08:00
Alan Modra
91cb9803fc Allow target files access to default TC_FORCE_RELOCATION defines
* write.c (GENERIC_FORCE_RELOCATION_LOCAL): Define.
	(TC_FORCE_RELOCATION_LOCAL): Use it.
	(GENERIC_FORCE_RELOCATION_SUB_SAME): Define.
	(TC_FORCE_RELOCATION_SUB_SAME): Use it.
	* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL,
	TC_FORCE_RELOCATION_SUB_SAME): Use GENERIC defines.
	* config/tc-aarch64.h: Similarly.
	* config/tc-avr.h: Similarly.
	* config/tc-cris.h: Similarly.
	* config/tc-i386.h: Similarly.
	* config/tc-i960.h: Similarly.
	* config/tc-ia64.h: Similarly.
	* config/tc-microblaze.h: Similarly.
	* config/tc-mips.h: Similarly.
	* config/tc-msp430.h: Similarly.
	* config/tc-nds32.h: Similarly.
	* config/tc-pru.h: Similarly.
	* config/tc-riscv.h: Similarly.
	* config/tc-rl78.h: Similarly.
	* config/tc-s390.h: Similarly.
	* config/tc-sh.h: Similarly.
	* config/tc-sh64.h: Similarly.
	* config/tc-sparc.h: Similarly.
	* config/tc-xtensa.h: Similarly.
	* config/tc-mn10300.h: Similarly.
	(GENERIC_FORCE_RELOCATION_LOCAL): Define.
	* config/tc-msp430.c (msp430_force_relocation_local): Modify to
	be addition to rather than replacement of standard
	TC_FORCE_RELOCATION_LOCAL.
2017-05-16 10:35:02 +09:30
Kuan-Lin Chen
d47c3ff7d5 RISC-V: Define DWARF2_USE_FIXED_ADVANCE_PC.
gas/ChangeLog

2017-03-02  Kuan-Lin Chen  <rufus@andestech.com>

        * config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
2017-03-14 09:51:29 -07:00
Alan Modra
2571583aed Update year range in copyright notice of all files. 2017-01-02 14:08:56 +10:30
Andrew Waterman
d115ab8eee Don't define RISC-V .p2align
* config/tc-riscv.c (riscv_pseudo_table): Remove "align",
	"p2align", and "balign".
	(s_align): Remove.
	(riscv_handle_align): New function.
	(riscv_frag_align_code): Likewise.
	(riscv_make_nops): Likewise.
	* config/tc-riscv.h (MAX_MEM_FOR_RS_ALIGN_CODE): Change to 7.
	(HANDLE_ALIGN): Define.
	(md_do_align): Define.
	(riscv_handle_align): Declare.
	(riscv_frag_align_code): Likewise.
2016-12-20 12:26:34 +10:30
Andrew Waterman
2922d21da1 Re-work RISC-V gas flags: now we just support -mabi and -march
We've decided to standardize on two flags for RISC-V: "-march" sets the
target architecture (which determines which instructions can be
generated), and "-mabi" sets the target ABI.  We needed to rework this
because the old flag set didn't support soft-float or single-float ABIs,
and didn't support an x32-style ABI on RISC-V.

Additionally, we've changed the behavior of the -march flag: it's now a
lot stricter and only parses things we can actually understand.
Additionally, it's now lowercase-only: the rationale is that while the
RISC-V ISA manual specifies that ISA strings are case-insensitive, in
Linux-land things are usually case-sensitive.  Since this flag can be
used to determine library paths, we didn't want to bake some
case-insensitivity in there that would case trouble later.

This patch implements these two new flags and removes the old flags that
could conflict with these.  There wasn't a RISC-V release before, so we
want to just support a clean flag set.

include/
	* elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define.
	(EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define.
	(EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define.
	(EF_RISCV_FLOAT_ABI_QUAD): Define.
bfd/
	* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use
	EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT.
binutils/
	* readelf.c (get_machine_flags): Use
	EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of
	EF_RISCV_{SOFT,HARD}_FLOAT.
gas/
	* config/tc-riscv.h (xlen): Delete.
	* config/tc-riscv.c (xlen): Make static.
	(abi_xlen): New variable.
	(options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC}
	with OPTION_MABI.
	(md_longopts): Likewise.
	(md_parse_option): Likewise.
	(riscv_elf_final_processing): Likewise.
	* doc/as.texinfo (Target RISC-V options): Likewise.
	* doc/c-riscv.texi (OPTIONS): Likewise.
	* config/tc-riscv.c (float_mode): Removed.
	(float_abi): New type, specifies the floating-point ABI.
	(riscv_set_abi): New function.
	(riscv_add_subset): Only allow lower-case ISA names and require
	them to start with "rv".
	(riscv_after_parse_args): Likewise.
opcodes/
	* riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
	XLEN when none is provided.
2016-12-20 12:26:34 +10:30
Andrew Waterman
45f764234a Rework RISC-V relocations
Before this commit we didn't cleanly support CFI directives because the
internal offsets used to get relaxed which broke them.  This patch
significantly reworks how we handle linker relaxations:

 * DWARF is now properly supported

 * There is a ".option norelax" to disable relaxations, for when users
   write assembly that can't be relaxed (if it's to be later patched up,
   for example).

 * There is an additional _RELAX relocation that specifies when previous
   relocations can be relaxed.

We're in the process of documenting the RISC-V ELF ABI, which will
include documentation of our relocations

  https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

but we expect that this relocation set will remain ABI compatible in the
future (ie, it's safe to release).

Thanks to Kuan-Lin Chen for figuring out how to correctly relax the
debug info!

include/
	* elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
bfd/
	* reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation.
	(BFD_RELOC_RISCV_TPREL_S): Likewise.
	(BFD_RELOC_RISCV_RELAX): Likewise.
	(BFD_RELOC_RISCV_CFA): Likewise.
	(BFD_RELOC_RISCV_SUB6): Likewise.
	(BFD_RELOC_RISCV_SET8): Likewise.
	(BFD_RELOC_RISCV_SET8): Likewise.
	(BFD_RELOC_RISCV_SET16): Likewise.
	(BFD_RELOC_RISCV_SET32): Likewise.
	* elfnn-riscv.c (perform_relocation): Handle the new
	relocations.
	(_bfd_riscv_relax_tls_le): Likewise.
	(_bfd_riscv_relax_align): Likewise.
	(_bfd_riscv_relax_section): Likewise.
	(howto_table): Likewise.
	(riscv_reloc_map): Likewise.
	(relax_func_t): New type.
	(_bfd_riscv_relax_call): Add reserve_size argument, which
	controls the maximal offset pessimism.  Correct type of max_alignment.
	(_bfd_riscv_relax_lui): Likewise.
	(_bfd_riscv_relax_tls_le): Likewise.
	(_bfd_riscv_relax_align): Likewise.
	(_bfd_riscv_relax_section): Compute the required reserve size
	when relocating and use it to when calling relax_func.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.
gas/
	* config/tc-riscv.c (riscv_set_options): Add relax.
	(riscv_opts): Likewise.
	(s_riscv_option): Add relax and norelax.
	(riscv_apply_const_reloc): New function.
	(append_insn): Move constant relocation handling to
	riscv_apply_const_reloc.
	(md_pcrel_from): Likewise.
	(parse_relocation): Skip BFD_RELOC_UNUSED.
	(md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6,
	BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA.
	(md_apply_fix): Likewise.
	(riscv_pre_output_hook): New function.
	* config/tc-riscv.h (md_pre_output_hook): Define.
	(riscv_pre_output_hook): Declare.
	(DWARF_CIE_DATA_ALIGNMENT): Always -4.
2016-12-20 12:26:33 +10:30
Nick Clifton
e23eba971d Add support for RISC-V architecture.
bfd	* Makefile.am: Add entries for riscv32-elf and riscv64-elf.
	* config.bdf: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* archures.c: Add bfd_riscv_arch.
	* reloc.c: Add riscv relocs.
	* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
	* elfnn-riscv.c: New file.
	* elfxx-riscv.c: New file.
	* elfxx-riscv.h: New file.

binutils* readelf.c (guess_is_rela): Add EM_RISCV.
	(get_machine_name): Likewise.
	(dump_relocations): Add support for riscv relocations.
	(get_machine_flags): Add support for riscv flags.
	(is_32bit_abs_reloc): Add R_RISCV_32.
	(is_64bit_abs_reloc): Add R_RISCV_64.
	(is_none_reloc): Add R_RISCV_NONE.
	* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
	Expect the debug_ranges test to fail.

gas	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this architecture.
	* configure.in: Define a default architecture.
	* configure: Regenerate.
	* configure.tgt: Add entries for riscv.
	* doc/as.texinfo: Likewise.
	* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
	* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
	* config/tc-riscv.c: New file.
	* config/tc-riscv.h: New file.
	* doc/c-riscv.texi: New file.
	* testsuite/gas/riscv: New directory.
	* testsuite/gas/riscv/riscv.exp: New file.
	* testsuite/gas/riscv/t_insns.d: New file.
	* testsuite/gas/riscv/t_insns.s: New file.

ld	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this target.
	* configure.tgt: Add riscv entries.
	* emulparams/elf32lriscv-defs.sh: New file.
	* emulparams/elf32lriscv.sh: New file.
	* emulparams/elf64lriscv-defs.sh: New file.
	* emulparams/elf64lriscv.sh: New file.
	* emultempl/riscvelf.em: New file.

opcodes	* configure.ac: Add entry for bfd_riscv_arch.
	* configure: Regenerate.
	* disassemble.c (disassembler): Add support for riscv.
	(disassembler_usage): Likewise.
	* riscv-dis.c: New file.
	* riscv-opc.c: New file.

include	* dis-asm.h: Add prototypes for print_insn_riscv and
	print_riscv_disassembler_options.
	* elf/riscv.h: New file.
	* opcode/riscv-opc.h: New file.
	* opcode/riscv.h: New file.
2016-11-01 16:45:57 +00:00