mirrors/binutils-gdb
0
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2024-12-02 23:04:09 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity
85,742 Commits 382 Branches 134 Tags 582 MiB
d685192a58
Commit Graph

1937 Commits

Author SHA1 Message Date
Matthew Wahab
d685192a58 [AArch64] Add ARMv8.2 instructions BFC and REV64. 
ARMv8.2 adds two new instructions: BFC as an alias for BFM and REV64 as
an alias for REV. This patch set adds support for these to binutils,
enabled when the -march=armv8.2-a is given. It depends on the support
for an instruction being its preferred form which was added in an
earlier patch.

This patch adds the alias BFC <Rd>, #<imm>, #<width> as the preferred
form for BFM when the source is a zero register and the conditions for
using the BFI form are met (in other words, BFC is the preferred form
for BFI <Rd>, <Rs>, #<imm>, #<width> when the <Rs> is a zero register).

gas/testsuite/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/alias-2.d: New.
	* gas/aarch64/alias-2.s: New.

include/opcode/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_op): Add OP_BFC.

opcodes/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-asm.c (convert_bfc_to_bfm): New.
	(convert_to_real): Add case for OP_BFC.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-dis.c: (convert_bfm_to_bfc): New.
	(convert_to_alias): Add case for OP_BFC.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
	to allow width operand in three-operand instructions.
	* aarch64-tbl.h (QL_BF1): New.
	(aarch64_feature_v8_2): New.
	(ARMV8_2): New.
	(aarch64_opcode_table): Add "bfc".

Change-Id: I6efe318b2538ba11f0caece7c6d70957441c872b
 2015-11-27 15:28:42 +00:00
Matthew Wahab
870181955b [AArch64] Add feature flags and command line for ARMv8.2 FP16 support. 
ARMv8.2 adds optional support for 16-bit operations to the FP and
Adv.SIMD instructions. This patch adds a feature macro for this support
with a new command line option "+fp16" to enable/disable it.

Although the command line option is added as an architecture extension,
it only affects instructions available with when +fp or +simd is
enabled. If +fp16 is specified then it will also enable +fp.

There are currently no FP16 instructions implemented in binutils, this
patch is to enable subsequent work on supporting the extension.

gas/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "fp16".
	* doc/c-aarch64.texi (Architecture Extensions): Add "fp16".

include/opcode/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_F16): New.
	(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
	features.

Change-Id: Id2021e0513946e16d0935c2a5b9605574cdff95a
 2015-11-27 13:19:50 +00:00
Nick Clifton
2e8cf49e13 Add an AArch64 simulator to GDB. 
sim	* configure.tgt: Add aarch64 entry.
	* configure: Regenerate.
	* sim/aarch64/configure.ac: New configure template.
	* sim/aarch64/aclocal.m4: Generate.
	* sim/aarch64/config.in: Generate.
	* sim/aarch64/configure: Generate.
	* sim/aarch64/cpustate.c: New file - functions for accessing
	AArch64 registers.
	* sim/aarch64/cpustate.h: New header.
	* sim/aarch64/decode.h: New header.
	* sim/aarch64/interp.c: New file - interface between GDB and
	simulator.
	* sim/aarch64/Makefile.in: New makefile template.
	* sim/aarch64/memory.c: New file - functions for simulating
	aarch64 memory accesses.
	* sim/aarch64/memory.h: New header.
	* sim/aarch64/sim-main.h: New header.
	* sim/aarch64/simulator.c: New file - aarch64 simulator
	functions.
	* sim/aarch64/simulator.h: New header.

include/gdb * sim-aarch64.h: New file.

sim/test * configure: Regenerate.
	* sim/aarch64: New directory.
 2015-11-24 08:47:59 +00:00
Matthew Wahab
250aafa477 [AArch64] Add support for ARMv8.1 Virtulization Host Extensions. 
The ARMv8.1 architecture includes the Virtualization Host Extensions
which add a number of system registers. This patch adds support for
these system registers, making them available when -march=armv8.1-a is
selected.

include/opcode/
2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_V8_1): New.
	(AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.

opcodes/
2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
	sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
	tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
	amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
	cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
	cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
	cnthv_ctl_el2, cnthv_cval_el2.
	(aarch64_sys_reg_supported_p): Update for the new system
	registers.

gas/testsuite/
2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/virthostext-directive.d: New.
	* gas/aarch64/virthostext.d: New.
	* gas/aarch64/virthostext.s: New.

Change-Id: Iecb370591b1b6e9e00d81c8ccd9ae3b0f71794a2
 2015-11-20 16:09:34 +00:00
Matthew Wahab
56a1b672f4 [ARM] Add ARMv8.2 architecture feature and command line option. 
ARMv8.2 is an architectural extension of ARMv8. This patch adds an
architecture feature macro for ARMv8.2 to the binutils ARM target
with GAS command line option -march=armv8.2-a.

gas/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-arm.c (arm_archs): Add "armv8.2-a".
	* doc/c-arm.texi (-march): Add "armv8.2-a".

include/opcode/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* arm.h (ARM_EXT2_V8_2A): New.
	(ARM_ARCH_V8_2A): New.

Change-Id: I9e0f50e3c6cea24e6b87b8b862fd4e1cdcc1052e
 2015-11-19 09:24:14 +00:00
Matthew Wahab
acb787b032 [AArch64] Add ARMv8.2 command line option and feature flag. 
ARMv8.2 is an architectural extension of ARMv8. This patch adds an
architecture feature macro for ARMv8.2 to the binutils AArch64 target
with GAS command line option -march=armv8.2-a.

gas/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_archs): Add "armv8.2-a".
	* doc/c-aarch64.texi (-march): Likewise.

include/opcode/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_V8_2): New.
	(AARCH64_ARCH_V8_2): New.

Change-Id: I129232ab00234a07d18ce4b619607344acb3cbaf
 2015-11-19 09:12:49 +00:00
Tristan Gingold
c25b1ab690 Mach-O: add new defines and struct for darwin 14.5 
include/mach-o/
	* arm64.h: New file.
	* unwind.h: Add arm64 encodings.
	* loader.h (bfd_mach_o_cpu_subtype): Add arm64 literals.
	(BFD_MACH_O_LC_ENCRYPTION_INFO_64, BFD_MACH_O_LC_LINKER_OPTIONS)
	(BFD_MACH_O_LC_LINKER_OPTIMIZATION_HINT)
	(BFD_MACH_O_LC_VERSION_MIN_WATCHOS): Define.
	* external.h (mach_o_encryption_info_64_command_external):
	(mach_o_linker_option_command_external)
	(mach_o_dyld_cache_header_external)
	(mach_o_dyld_cache_mapping_info_external)
	(mach_o_dyld_cache_image_info_external): New types.
 2015-11-17 15:03:25 +01:00
Mike Frysinger
761e171ad8 sim: cr16: convert to common sim memory modules 
The cr16 port has a lot of translation/offset logic baked into it, but
it all looks like copy & paste from the d10v port rather than something
the cr16 port wants.
 2015-11-15 21:48:06 -05:00
Mike Frysinger
c4d4ed4083 sim: drop extern C linkage from most sim interface headers 
Since these headers merely have enum's, drop the extern C linkage
markings.  Helps to reduce the copy & paste spam.
 2015-11-15 00:38:26 -05:00
Peter Bergner
a680de9a98 Add assembler, disassembler and linker support for power9. 
include/opcode/
	* ppc.h (PPC_OPCODE_POWER9): New define.
	(PPC_OPCODE_VSX3): Likewise.

opcodes/
	* ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
	Add PPC_OPCODE_VSX3 to the vsx entry.
	(powerpc_init_dialect): Set default dialect to power9.
        * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
        insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
        extract_l1 insert_xtq6, extract_xtq6): New static functions.
        (insert_esync): Test for illegal L operand value.
	(DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
	XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
	XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
	XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
	PPCVSX3): New defines.
	(powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
	fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
	<mcrxr>: Use XBFRARB_MASK.
	<addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
	bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
	cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
	cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
	lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
	lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
	modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
	rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
	stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
	subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
	vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
	vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
	vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
	vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
	vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
	vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
	vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
	xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
	xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
	xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
	xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
	xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
	xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
	xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
	xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
	xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
	xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
	xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
	xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
	xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
	<doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
	<tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.

include/elf/
	* ppc.h (R_PPC_REL16DX_HA): New reloction.
	* ppc64.h (R_PPC64_REL16DX_HA): Likewise.

bfd/
	* elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA.
	(ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA.
	(ppc_elf_addr16_ha_reloc): Likewise.
	(ppc_elf_check_relocs): Likewise.
	(ppc_elf_relocate_section): Likewise.
	(is_insn_dq_form): Handle lxv and stxv instructions.
	* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA.
	(ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA.
	(ppc64_elf_ha_reloc): Likewise.
	(ppc64_elf_check_relocs): Likewise.
	(ppc64_elf_relocate_section): Likewise.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.
	* reloc.c (BFD_RELOC_PPC_REL16DX_HA): New.

elfcpp/
	* powerpc.h (R_POWERPC_REL16DX_HA): Define.

gas/
	* doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9.
	* doc/c-ppc.texi (PowerPC-Opts):  Likewise.
	* config/tc-ppc.c (md_show_usage): Likewise.
	(md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA.
	(md_apply_fix): Likewise.
	(ppc_handle_align): Handle power9's group ending nop.

gas/testsuite/
	* gas/ppc/altivec3.s: New test.
	* gas/ppc/altivec3.d: Likewise.
	* gas/ppc/vsx3.s: Likewise.
	* gas/ppc/vsx3.d: Likewise.
	* gas/ppc/power9.s: Likewise.
	* gas/ppc/power9.d: Likewise.
	* gas/ppc/ppc.exp: Run them.
	* gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests.
	* gas/ppc/power8.d: Likewise.
	* gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ...
	<lxvd2x, stxvd2x>: ...to this.
	* gas/ppc/vsx.d: Likewise.

gold/
	* gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function.
	(Powerpc_relocate_functions::addr16dx_ha): Likewise.
	(Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA.
	(Target_powerpc::Scan::global): Likewise.
	(Target_powerpc::Relocate::relocate): Likewise.

ld/testsuite/
	* ld-powerpc/addpcis.d: New test.
	* ld-powerpc/addpcis.s: New test.
	* ld-powerpc/powerpc.exp: Run it.
 2015-11-11 19:52:52 -06:00
Mike Frysinger
6637a4265e sim: cr16/d10v: localize translation funcs 
These functions are only used in the interp module, so there's no point
in exporting them and declaring them in the external sim interface.
 2015-11-10 02:17:15 -05:00
Alan Modra
e9f40d7d68 Modify obstack.[hc] to avoid having to include other gnulib files 
Using the standard gnulib obstack source requires importing quite a
lot of other files from gnulib, and requires build changes.

include/
	PR gdb/17133
	* obstack.h (__attribute_pure__): Expand _GL_ATTRIBUTE_PURE.
libiberty/
	PR gdb/17133
	* obstack.c (__alignof__): Expand alignof_type from alignof.h.
	(obstack_exit_failure): Don't use exitfail.h.
	(_): Include libintl.h when HAVE_LIBINTL_H and nls enabled.
	Provide default.  Don't include gettext.h.
	(_Noreturn): Define.
	* obstacks.texi: Adjust node references to external libc info files.
 2015-11-09 15:18:35 +10:30
Alan Modra
314dee8ea9 Copy gnulib obstack files 
This copies obstack.[ch] from gnulib, and updates the docs.  The next
patch should be applied if someone repeats the import at a later date.

include/
	PR gdb/17133
	* obstack.h: Import current gnulib file.
libiberty/
	PR gdb/17133
	* obstack.c: Import current gnulib file.
	* obstacks.texi: Updated doc, from glibc's manual/memory.texi.
 2015-11-09 15:12:45 +10:30
Nick Clifton
854eb72b00 Disassemble RX NOP instructions as such. 
opcode	* rx.h (enum RX_Opcode_ID): Add more NOP opcodes.

opcodes	* rx-decode.opc (rx_decode_opcode): Decode extra NOP
	instructions.
	* rx-decode.c: Regenerate.

tests	* gas/rx/max.d: Update expecetd disassembly.
	* gas/rx/nod.d: Likewise.
	* gas/rx/nop.sm: Add tests of more NOP instructions.
 2015-11-02 14:37:33 +00:00
Nick Clifton
e292aa7a95 Fix disassembly of RX zero-offset register indirect instructions. 
opcode	* rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.

opcodes	* rx-decode.opc (rx_disp): If the displacement is zero, set the
	type to RX_Operand_Zero_Indirect.
	* rx-decode.c: Regenerate.
	* rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.

gas	* config/rx-parse.y: Allow zero value for 5-bit displacements.

tests	* gas/rx/mov.sm: Add tests for zero offset indirect moves.
	* gas/rx/mov.d: Update expected output.
 2015-11-02 14:14:22 +00:00
Yao Qi
43cdf5aeb8 Pass noaliases_p to aarch64_decode_insn 
Nowadays aarch64_decode_insn is a public interface used by both
opcodes and gdb.  However, its behaviour relies on a global variable
no_aliases, which isn't a good practise.  On the other hand, In default,
no_aliases is zero, but in GDB, we do want no alias when decoding
instructions for prologue analysis (patches to be posted), so that we
can handle both instructions "add" and "mov" (an alias of "add") as
"add".  The code in GDB can be simplified.

This patch adds a new argument in aarch64_decode_insn, and pass no_aliases
to it.  In GDB side, always pass 1 to it.

include/opcode:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_decode_insn): Update declaration.

opcodes:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c	(aarch64_decode_insn): Add one argument
	noaliases_p.  Update comments.  Pass noaliases_p rather than
	no_aliases to aarch64_opcode_decode.
	(print_insn_aarch64_word): Pass no_aliases to
	aarch64_decode_insn.

gdb:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_software_single_step): Pass 1 to
	aarch64_decode_insn.
 2015-10-28 14:22:57 +00:00
Cupertino Miranda
6f4b1afcdc Fix errors in the gas testsuite for the ARC target. 
bfd	* reloc.c (BFD_RELOC_ARC_32_PCREL): New entry.
	(ARC_TLS_DTPOFF): Arrange it in order.
	* elf32-arc.c (arc_elf_howto_ini): Update formula.
	(get_middle_endian_relocation): New function.
	(PDATA): Define.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.

elf	* arc-reloc.def (ARC_32_PCREL): New definition.

gas	* config/tc-arc.c (tokenize_arguments): Avoid creating unused
	symbols when parsing relocation types.
	(md_apply_fix): Handle TLS relocations. Fix BFD_RELOC_ARC_32_PCREL
	relocation.
	(arc_check_reloc): Emit BFD_RELOC_ARC_32_PCREL relocation.
 2015-10-28 13:48:00 +00:00
Stephen Fisher
c6056a744a Add support to readelf for reading NetBSD ELF core notes. 
binutils * binutils.c (process_netbsd_elf_note): New function.
	(process_note): Call the new function for NetBSD core notes.

include	* common.h (NT_NETBSD_MARCH): Define.
 2015-10-27 11:32:38 +00:00
H.J. Lu
caa65211bb Add "-z call-nop=PADDING" option to ld 
The ld linker can transform indirect call to a locally defined function,
foo, via its GOT slot, to either "NOP call foo" or "call foo NOP" where
NOP is a 1-byte NOP padding.  This patch adds a "-z call-nop=PADDING"
option to x86 ld to control 1-byte NOP padding for x86 call instruction.
PADDING is one of prefix-addr, prefix-nop, suffix-nop, prefix-NUMBER or
suffix-NUMBER.

bfd/

	* elf32-i386.c (elf_i386_convert_load): Use call_nop_byte and
	check call_nop_as_suffix for 1-byte NOP padding to pad call.
	* elf64-x86-64.c (elf_x86_64_convert_load): Likewise.

include/

	* bfdlink.h (bfd_link_info): Add call_nop_as_suffix and
	call_nop_byte.

ld/

	* ld/ld.texinfo: Document "-z call-nop=PADDING" option.
	* emulparams/call_nop.sh: New file.
	* emulparams/elf_i386_be.sh: Source
	${srcdir}/emulparams/call_nop.sh.
	* emulparams/elf_i386_chaos.sh: Likewise.
	* emulparams/elf_i386_ldso.sh: Likewise.
	* emulparams/elf_i386_vxworks.sh: Likewise.
	* emulparams/elf_iamcu.sh: Likewise.
	* emulparams/elf_k1om.sh: Likewise.
	* emulparams/elf_l1om.sh: Likewise.
	* emulparams/elf_x86_64.sh: Likewise.
	* emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set
	link_info.call_nop_byte if $CALL_NOP_BYTE isn't empty.

ld/testsuite/

	* ld-i386/call3.s: New file.
	* ld-i386/call3a.d: Likewise.
	* ld-i386/call3b.d: Likewise.
	* ld-i386/call3c.d: Likewise.
	* ld-i386/call3d.d: Likewise.
	* ld-i386/call3e.d: Likewise.
	* ld-i386/call3f.d: Likewise.
	* ld-i386/call3g.d: Likewise.
	* ld-i386/call3h.d: Likewise.
	* ld-i386/load1-nacl.d: Likewise.
	* ld-x86-64/call1.s: Likewise.
	* ld-x86-64/call1a.d: Likewise.
	* ld-x86-64/call1b.d: Likewise.
	* ld-x86-64/call1c.d: Likewise.
	* ld-x86-64/call1d.d: Likewise.
	* ld-x86-64/call1e.d: Likewise.
	* ld-x86-64/call1f.d: Likewise.
	* ld-x86-64/call1g.d: Likewise.
	* ld-x86-64/call1h.d: Likewise.
	* ld-x86-64/call1i.d: Likewise.
	* ld-x86-64/load1a-nacl.d: Likewise.
	* ld-x86-64/load1b-nacl.d: Likewise.
	* ld-x86-64/load1c-nacl.d: Likewise.
	* ld-x86-64/load1d-nacl.d: Likewise.
 2015-10-22 04:56:39 -07:00
H.J. Lu
56ceb5b540 Add R_X86_64_[REX_]GOTPCRELX support to gas and ld 
This patch adds support for the R_X86_64_GOTPCRELX and
R_X86_64_REX_GOTPCRELX relocations proposed in

https://groups.google.com/forum/#!topic/x86-64-abi/n9AWHogmVY0

to gas and ld.  It updates gas to generate R_X86_64_GOTPCRELX,
R_X86_64_REX_GOTPCRELX if there is a REX prefix, relocation for memory
operand, foo@GOTPCREL(%rip).  With the locally defined symbol, foo, we
convert

  mov foo@GOTPCREL(%rip), %reg

to

   lea foo(%rip), %reg

and convert

   call/jmp *foo@GOTPCREL(%rip)
to

   nop call foo/jmp foo nop

When PIC is false, convert

   test %reg, foo@GOTPCREL(%rip)
to

test $foo, %reg

and convert

   binop foo@GOTPCREL(%rip), %reg

to

   binop $foo, %reg

where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions.

bfd/

	* elf64-x86-64.c: Include opcode/i386.h.
	(x86_64_elf_howto_table): Add R_X86_64_GOTPCRELX and
	R_X86_64_REX_GOTPCRELX.
	(R_X86_64_standard): Replace R_X86_64_PLT32_BND with
	R_X86_64_REX_GOTPCRELX.
	(x86_64_reloc_map): Add BFD_RELOC_X86_64_GOTPCRELX and
	BFD_RELOC_X86_64_REX_GOTPCRELX.
	(need_convert_mov_to_lea): Renamed to ...
	(need_convert_load): This.
	(elf_x86_64_check_relocs): Handle R_X86_64_GOTPCRELX and
	R_X86_64_REX_GOTPCRELX.  Replace need_convert_mov_to_lea with
	need_convert_load.
	(elf_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPCRELX and
	R_X86_64_REX_GOTPCRELX.
	(elf_x86_64_size_dynamic_sections): Likewise.
	(elf_x86_64_relocate_section): Likewise.
	(elf_x86_64_convert_mov_to_lea): Renamed to ...
	(elf_x86_64_convert_load): This.  Replace need_convert_mov_to_lea
	with need_convert_load.  Support R_X86_64_GOTPCRELX and
	R_X86_64_REX_GOTPCRELX transformations.
	* reloc.c (BFD_RELOC_X86_64_GOTPCRELX): New.
	(BFD_RELOC_X86_64_REX_GOTPCRELX): Likewise.
	* bfd-in2.h: Regenerated.
	* libbfd.h: Likewise.

gas/

	* config/tc-i386.c (tc_i386_fix_adjustable): Handle
	BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX.
	(tc_gen_reloc): Likewise.
	(i386_validate_fix): Generate BFD_RELOC_X86_64_GOTPCRELX or
	BFD_RELOC_X86_64_REX_GOTPCRELX if fx_tcbit2 is set.
	* config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Also return
	true for BFD_RELOC_X86_64_GOTPCRELX and
	BFD_RELOC_X86_64_REX_GOTPCRELX.

gas/testsuite/

	* gas/i386/i386.exp: Run x86-64-gotpcrel.
	* gas/i386/x86-64-gotpcrel.d: New file.
	* gas/i386/x86-64-gotpcrel.s: Likewise.
	* gas/i386/ilp32/x86-64-gotpcrel.d: Likewise.
	* gas/i386/x86-64-localpic.d: Replace R_X86_64_GOTPCREL with
	R_X86_64_REX_GOTPCRELX.
	* gas/i386/ilp32/x86-64-localpic.d: Likewise.

include/elf/

	* x86-64.h (R_X86_64_GOTPCRELX): New.
	(R_X86_64_REX_GOTPCRELX): Likewise.

ld/testsuite/

	* ld-ifunc/ifunc-5r-local-x86-64.d: Replace R_X86_64_GOTPCREL
	with R_X86_64_REX_GOTPCRELX.
	* ld-x86-64/plt-main1.rd: Likewise.
	* ld-x86-64/plt-main3.rd: Likewise.
	* ld-x86-64/plt-main4.rd: Likewise.
	* ld-x86-64/gotpcrel1.dd: New file.
	* ld-x86-64/gotpcrel1.out: Likewise.
	* ld-x86-64/gotpcrel1a.S: Likewise.
	* ld-x86-64/gotpcrel1b.c: Likewise.
	* ld-x86-64/gotpcrel1c.c: Likewise.
	* ld-x86-64/gotpcrel1d.S: Likewise.
	* ld-x86-64/load1.s: Likewise.
	* ld-x86-64/load1a.d: Likewise.
	* ld-x86-64/load1b.d: Likewise.
	* ld-x86-64/load1c.d: Likewise.
	* ld-x86-64/load1d.d: Likewise.
	* ld-x86-64/x86-64.exp: Run load1a, load1b, load1c and load1d
	tests.  Run gotpcrel1 test.
 2015-10-22 04:49:38 -07:00
H.J. Lu
02a866936d Add R_386_GOT32X support to gas and ld 
This patch adds support for the R_386_GOT32X relocation proposed in

https://groups.google.com/forum/#!topic/ia32-abi/GbJJskkid4I

to gas and ld.  It updates gas to generate R_386_GOT32X relocation for
memory operand, foo@GOT[(%reg)].  We must encode "mov foo@GOT, %eax"
with the 0x8b opcode, instead of the 0xb8 opcode, so that it can be
transformed to "lea foo, %eax".  With the locally defined symbol, foo,
we convert

   mov foo@GOT[(%reg1)], %reg2
to
   lea foo[@GOTOFF(%reg1)], %reg2

and convert

   call/jmp *foo@GOT[(%reg)]
to

   nop call foo/jmp foo nop

When PIC is false, convert

   test %reg1, foo@GOT[(%reg2)]
to
   test $foo, %reg1

and convert

binop foo@GOT[(%reg1)], %reg2

to

binop $foo, %reg2

where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions.

bfd/

	* elf32-i386.c: Include opcode/i386.h.
	(elf_howto_table): Add R_386_GOT32X.
	(R_386_ext2): Replace R_386_IRELATIVE with R_386_GOT32X.
	(elf_i386_reloc_type_lookup): Handle BFD_RELOC_386_GOT32X.
	(need_convert_mov_to_lea): Renamed to ...
	(need_convert_load): This.
	(elf_i386_check_relocs): Handle R_386_GOT32X.  Replace
	need_convert_mov_to_lea with need_convert_load.
	(elf_i386_gc_sweep_hook): Handle R_386_GOT32X.
	(elf_i386_size_dynamic_sections): Likewise.
	(elf_i386_relocate_section): Likewise.
	(elf_i386_convert_mov_to_lea): Renamed to ...
	(elf_i386_convert_load): This.  Replace need_convert_mov_to_lea
	with need_convert_load.  Support R_386_GOT32X transformations.
	* reloc.c (BFD_RELOC_386_GOT32X): New.
	* bfd-in2.h: Regenerated.
	* libbfd.h: Likewise.

gas/

	* config/tc-i386.c (tc_i386_fix_adjustable): Handle
	BFD_RELOC_386_GOT32X.
	(tc_gen_reloc): Likewise.
	(match_template): Force 0x8b encoding for "mov foo@GOT, %eax".
	(output_disp): Check for "call/jmp *mem", "mov mem, %reg",
	"test %reg, mem" and "binop mem, %reg" where binop is one of
	adc, add, and, cmp, or, sbb, sub, xor instructions.  Set
	fx_tcbit if the REX prefix is generated.  Set fx_tcbit2 if
	BFD_RELOC_386_GOT32X should be generated.
	(i386_validate_fix): Generate BFD_RELOC_386_GOT32X if fx_tcbit2
	is set.

gas/testsuite/

	* gas/i386/got.d: New file.
	* gas/i386/got.s: Likewise.
	* gas/i386/i386.exp: Run got.
	* gas/i386/localpic.d: Replace R_386_GOT32 with R_386_GOT32X.
	* gas/i386/mixed-mode-reloc32.d: Likewise.
	* gas/i386/reloc32.d: Likewise.

include/elf/

	* i386.h (R_386_GOT32X): New relocation.

ld/testsuite/

	* ld-i386/branch1.d: New file.
	* ld-i386/branch1.s: Likewise.
	* ld-i386/call1.d: Likewise.
	* ld-i386/call1.s: Likewise.
	* ld-i386/call2.d: Likewise.
	* ld-i386/call2.s: Likewise.
	* ld-i386/got1.dd: Likewise.
	* ld-i386/got1.out: Likewise.
	* ld-i386/got1a.S: Likewise.
	* ld-i386/got1b.c: Likewise.
	* ld-i386/got1c.c: Likewise.
	* ld-i386/got1d.S: Likewise.
	* ld-i386/jmp1.d: Likewise.
	* ld-i386/jmp1.s: Likewise.
	* ld-i386/jmp2.d: Likewise.
	* ld-i386/jmp2.s: Likewise.
	* ld-i386/load1.d: Likewise.
	* ld-i386/load1.s: Likewise.
	* ld-i386/load2.d: Likewise.
	* ld-i386/load2.s: Likewise.
	* ld-i386/load3.d: Likewise.
	* ld-i386/load3.s: Likewise.
	* ld-i386/load4.s: Likewise.
	* ld-i386/load4a.d: Likewise.
	* ld-i386/load4b.d: Likewise.
	* ld-i386/load5.s: Likewise.
	* ld-i386/load5a.d: Likewise.
	* ld-i386/load5b.d: Likewise.
	* ld-i386/load6.d: Likewise.
	* ld-i386/load6.s: Likewise.
	* ld-i386/i386.exp: Run branch1, call1, call2, jmp1, jmp2,
	load1, load2, load3, load4a, load4b, load5a, load5b and load6
	tests.  Run got1 test.
 2015-10-22 04:47:07 -07:00
Yao Qi
875880c661 Avoid using 'template' C++ keyword 
'template' is used in include/opcode/aarch64.h as below,

 typedef struct
 {
   const char *template;
   uint32_t value;
   int has_xt;
 } aarch64_sys_ins_reg;

and it triggers compilation errors when GDB is built in C++ mode.

In file included from git/gdb/aarch64-tdep.c:62:0:
git/gdb/../include/opcode/aarch64.h:651:15: error: expected unqualified-id before 'template'
   const char *template;

This patch is to rename field template to name.

gas/

	* config/tc-aarch64.c (md_begin): Access field 'name' rather
	than 'template'.

include/opcode/

	* aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
	<name>: New field.

opcodes/

	* aarch64-dis.c (aarch64_ext_sysins_op): Access field
	'name' rather than 'template'.
	* aarch64-opc.c (aarch64_print_operand): Likewise.
 2015-10-07 15:22:47 +01:00
Yao Qi
d3e12b29ae Wrap include/opcode/aarch64.h in extern "C" for C++ 
This is sufficient to link an aarch64 GDB built in C++ mode.  Pedro
did something similar in Feb
https://sourceware.org/ml/binutils/2015-02/msg00176.html

include/opcode/

2015-10-07  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h [__cplusplus]: Wrap in extern "C".
 2015-10-07 15:07:14 +01:00
Nick Clifton
886a250647 New ARC implementation. 
bfd	* archures.c: Remove support for older ARC. Added support for new
	ARC cpus (ARC600, ARC601, ARC700, ARCV2).
	* bfd-in2.h: Likewise.
	* config.bfd: Likewise.
	* cpu-arc.c: Likewise.
	* elf32-arc.c: Totally changed file with a refactored
	inplementation of the ARC port.
	* libbfd.h: Added ARC specific relocation types.
	* reloc.c: Likewise.

gas     * config/tc-arc.c: Revamped file for ARC support.
        * config/tc-arc.h: Likewise.
        * doc/as.texinfo: Add new ARC options.
        * doc/c-arc.texi: Likewise.

ld	* configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
	* emulparams/arcebelf_prof.sh: New file
	* emulparams/arcebelf.sh: Likewise.
	* emulparams/arceblinux_prof.sh: Likewise.
	* emulparams/arceblinux.sh: Likewise.
	* emulparams/arcelf_prof.sh: Likewise.
	* emulparams/arcelf.sh: Likewise.
	* emulparams/arclinux_prof.sh: Likewise.
	* emulparams/arclinux.sh: Likewise.
	* emulparams/arcv2elfx.sh: Likewise.
	* emulparams/arcv2elf.sh: Likewise.
	* emultempl/arclinux.em: Likewise.
	* scripttempl/arclinux.sc: Likewise.
	* scripttempl/elfarc.sc: Likewise.
	* scripttempl/elfarcv2.sc: Likewise
	* Makefile.am: Add new ARC emulations.
	* Makefile.in: Regenerate.
	* NEWS: Mention the new feature.

opcodes * arc-dis.c: Revamped file for ARC support
	* arc-dis.h: Likewise.
	* arc-ext.c: Likewise.
	* arc-ext.h: Likewise.
	* arc-opc.c: Likewise.
	* arc-fxi.h: New file.
	* arc-regs.h: Likewise.
	* arc-tbl.h: Likewise.

binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
	and ARCv2.
	(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_16bit_abs_reloc): Likewise.
	(is_none_reloc): Likewise.
	* NEWS: Mention the new feature.

include	* dis-asm.h (arc_get_disassembler): Correct declaration.
	* arc-reloc.def: Macro file with definition of all relocation
	types.
	* arc.h: Changed macros for the newly supported ARC cpus.  Altered
	enum defining the supported relocations.
	* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
	macro for EM_ARC_COMPACT2.
        * arc-func.h: New file.
        * arc.h: Likewise.
 2015-10-07 14:20:19 +01:00
Yao Qi
e141d84e89 Make aarch64_zero_register_p declaration starts from column one 
include/opcode:

2015-10-02  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_zero_register_p): Move the declaration
	to column one.
 2015-10-02 15:43:46 +01:00
Yao Qi
36f4aab18c [aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insn 
We want to use disas_aarch64_insn inside GDB to decode instructions, so
this patch exposes it and rename it to aarch64_decode_insn to follow
the conventions of other interfaces.

include/opcode:

2015-10-02  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_decode_insn): Declare it.

opcodes:

2015-10-02  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c	(disas_aarch64_insn): Remove static.  Change
	argument insn type to aarch64_insn.  Rename to ...
	(aarch64_decode_insn): ... it.
	(print_insn_aarch64_word): Caller updated.
 2015-10-02 15:23:58 +01:00
Nick Clifton
6899683948 Resync files in the binutils repository that are maintained in the gcc repository. 
.	2015-08-23  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>

	PR libfortran/54572
	* Makefile.def: Make libgfortran depend on libbacktrace.
	* Makefile.in: Regenerate.

	2015-08-12  Tom de Vries  <tom@codesourcery.com>

	PR other/67092
	PR other/67098
	* configure.ac: Remove --with_host_libstdcxx support.
	* configure: Regenerate.

	2015-08-10  Thomas Schwinge  <thomas@codesourcery.com>
	    Jakub Jelinek  <jakub@redhat.com>

	* configure.ac (noconfigdirs): Don't add "target-libgomp" for target
	nvptx*-*-*.
	* configure: Regenerate.

include	2015-08-14  Pierre-Marie de Rodat  <derodat@adacore.com>

	* dwarf2.def (DW_AT_GNU_bias): New attribute.

	2015-08-14  Pierre-Marie de Rodat  <derodat@adacore.com>

	* dwarf2.def (DW_AT_GNU_numerator, DW_AT_GNU_denominator): New
	attributes.

libiberty  2015-08-15  Ian Lance Taylor  <iant@google.com>

	* cp-demangle.c (d_abi_tags): Preserve di->last_name across any
	ABI tags.
 2015-09-30 17:55:16 +01:00
Dominik Vogt
7ecc513a44 Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine zEC12+nohtm+vx" 
gas	* doc/c-s390.texi: Add documentation.
	Add missing code markup.
	* config/tc-s390.c (current_flags): New static variable.
	(s390_parse_cpu): Parse cpu flags a la "+nohtm" etc.
	(s390_setup_opcodes): Use cpu flags to determine the set of opcodes.
	Fix indentation.
	(md_parse_option): Call s390_parse_cpu with the new signature.
	(s390_machine): Likewise.
	Keep track of current_flags.
	Simplify code a bit.
	undefine MAX_HISTORY at end of function.
	(s390_machinemode): undefine MAX_HISTORY at end of function.
	Update an error message.

tests	* gas/s390/s390.exp: Add new tests.
	* gas/s390/machine-parsing-1.s: New test file.
	* gas/s390/machine-parsing-1.l: Likewise.
	* gas/s390/machine-parsing-2.s: Likewise.
	* gas/s390/machine-parsing-2.l: Likewise.
	* gas/s390/machine-parsing-3.s: Likewise.
	* gas/s390/machine-parsing-3.l: Likewise.
	* gas/s390/machine-parsing-4.s: Likewise.
	* gas/s390/machine-parsing-4.l: Likewise.
	* gas/s390/machine-parsing-5.s: Likewise.
	* gas/s390/machine-parsing-5.l: Likewise.
	* gas/s390/machine-parsing-6.s: Likewise.
	* gas/s390/machine-parsing-6.l: Likewise.

opcode	* s390.h (S390_INSTR_FLAG_HTM): New flag.
	(S390_INSTR_FLAG_VX): New flag.
	(S390_INSTR_FLAG_FACILITY_MASK): New flag mask.

opcodes	* s390-mkopc.c (main): Parse htm and vx flag.
	* s390-opc.txt: Mark instructions from the hardware transactional
	memory and vector facilities with the "htm"/"vx" flag.
 2015-09-29 13:22:07 +01:00
jamesbowman
71f4ed30fe FT32: define macros for instruction recognition. 
Other places (e.g. the gdb stack unwinder) can use these instead of
hard-coded patterns.

[include/Changelog]

2015-09-26  James Bowman  <james.bowman@ftdichip.com>

	* opcode/ft32.h: Add instruction macros FT32_*()
 2015-09-28 11:23:54 -07:00
Nick Clifton
b6518b3871 Fix compile time warnings generated when compiling with clang. 
bfd	* bout.c (b_out_slurp_reloc_table): Cast constant to unsigned in
	order to avoid problems with left shifting negative values.
	(abs32code): Likewise.
	* mach-o.c (FILE_ALIGN): Likewise.
	* coff-rs6000.c (xcoff_debug_sections): Delete unused static
	array.
	* elf32-visium.c (visium_reloc_map): Likewise.
	* elf32-arm.c (elf32_arm_final_link_relocate): Remove useless
	calls to abs function.
	* elf32-frv.c (_frvfdpic_relax_tls_entries): Likewise.
	* elf32-score.c (score_elf_final_link_relocate): Likewise.
	* elf32-score7.c (score_elf_final_link_relocate): Likewise.
	* elf32-i860.c (i860_howto_pc26_reloc): Use multiplication instead
	of shifting to create a negative mask.
	* elf32-msp430.c (elf_backend_special_sections): Define.
	* elfxx-mips.c (got_ofst_reloc_p): Delete unused function.
	(got_hi16_reloc_p): Delete unused function.
	* ppcboot.c (ppcboot_bfd_print_private_bfd_data): Fix test of
	partition name.

gas	* config/tc-ppc.c (insn_validate): Cast PPC_OPSHIFT_INV to an int.

opcode	* ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
	shifting.

ld	* emultempl/elf32.em (ehdr_start_empty): New static variable.
	(before_allocation): Use it to initialise ehdr_start_save.
	* emultempl/pe.em (write_build_id): Remove useless double
	parenthesis.
	* emultempl/pep.em (write_build_id): Likewise.

opcodes	* bfin-dis.c (fmtconst): Remove unnecessary call to the abs
	function.
	* tic30-dis.c (print_branch): Likewise.
	* cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
	value before left shifting.
	* fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
	* hppa-dis.c (print_insn_hppa): Likewise.
	* mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
	array.
	* msp430-dis.c (msp430_singleoperand): Likewise.
	(msp430_doubleoperand): Likewise.
	(print_insn_msp430): Likewise.
	* nds32-asm.c (parse_operand): Likewise.
	* sh-opc.h (MASK): Likewise.
	* v850-dis.c (get_operand_value): Likewise.
 2015-09-23 18:05:16 +01:00
Nick Clifton
f04265eceb Enhance the RX disassembler to detect and report bad instructions. 
opcode	* rx.h (enum RX_Size): Add RX_Bad_Size entry.

opcodes	* rx-decode.opc (bwl): Use RX_Bad_Size.
	(sbwl): Likewise.
	(ubwl): Likewise.  Rename to ubw.
	(uBWL): Rename to uBW.
	Replace all references to uBWL with uBW.
	* rx-decode.c: Regenerate.
	* rx-dis.c (size_names): Add entry for RX_Bad_Size.
	(opsize_names): Likewise.
	(print_insn_rx): Detect and report RX_Bad_Size.
 2015-09-22 17:21:13 +01:00
Rainer Orth
5c383f0262 Solaris PIE support 
include/elf:
	* common.h (DF_1_STUB, DF_1_PIE): Define.

	ld:
	* emulparams/solaris2.sh (GENERATE_PIE_SCRIPT): Set to yes.

	* emultempl/elf32.em: Include ldlex.h.
	(gld${EMULATION_NAME}_handle_option) [GENERATE_PIE_SCRIPT]
	<OPTION_PIE>: Set DF_1_PIE.

	binutils:
	* readelf.c (process_dynamic_section): Handle DF_1_STUB, DF_1_PIE.
 2015-09-22 11:12:51 +02:00
H.J. Lu
7f7a1bce25 Change ch_type in Elf64_External_Chdr to 4 bytes 
The ch_type field in Elf64_External_Chdr is 4 bytes, followed by a
4-byte padding.  This change doesn't introduce any functional change
since only the lower 32 bits of the ch_type field are used.

	* external.h (Elf64_External_Chdr): Change ch_type to 4 bytes
	and add ch_reserved.
 2015-09-21 10:19:25 -07:00
Rich Felker
9b8b325a1f Add --no-dynamic-linker option to ld, for static PIE use 
Inhibits output of .interp section in ELF executables.

include/
	* bfdlink.h (struct bfd_link_info): Add "nointerp" field.
bfd/
	* elflink.c (_bfd_elf_link_create_dynamic_sections): Don't create
	.interp when info->nointerp.
	(bfd_elf_size_dynamic_sections): Adjust assert.
	* elf32-arm.c (elf32_arm_size_dynamic_sections): Don't size .interp
	when info->nointerp.
	* elf32-bfin.c (elf32_bfinfdpic_size_dynamic_sections): Likewise.
	* elf32-cr16.c (_bfd_cr16_elf_size_dynamic_sections): Likewise.
	* elf32-cris.c (elf_cris_size_dynamic_sections): Likewise.
	* elf32-frv.c (elf32_frvfdpic_size_dynamic_sections): Likewise.
	* elf32-hppa.c (elf32_hppa_size_dynamic_sections): Likewise.
	* elf32-i370.c (i370_elf_size_dynamic_sections): Likewise.
	* elf32-i386.c (elf_i386_size_dynamic_sections): Likewise.
	* elf32-lm32.c (lm32_elf_size_dynamic_sections): Likewise.
	* elf32-m32r.c (m32r_elf_size_dynamic_sections): Likewise.
	* elf32-m68k.c (elf_m68k_size_dynamic_sections): Likewise.
	* elf32-metag.c (elf_metag_size_dynamic_sections): Likewise.
	* elf32-nds32.c (nds32_elf_size_dynamic_sections): Likewise.
	* elf32-nios2.c (nios2_elf32_size_dynamic_sections): Likewise.
	* elf32-or1k.c (or1k_elf_size_dynamic_sections): Likewise.
	* elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise.
	* elf32-s390.c (elf_s390_size_dynamic_sections): Likewise.
	* elf32-score.c (s3_bfd_score_elf_size_dynamic_sections): Likewise.
	* elf32-score7.c (s7_bfd_score_elf_size_dynamic_sections): Likewise.
	* elf32-sh.c (sh_elf_size_dynamic_sections): Likewise.
	* elf32-tic6x.c (elf32_tic6x_size_dynamic_sections): Likewise.
	* elf32-tilepro.c (tilepro_elf_size_dynamic_sections): Likewise.
	* elf32-vax.c (elf_vax_size_dynamic_sections): Likewise.
	* elf32-xtensa.c (elf_xtensa_size_dynamic_sections): Likewise.
	* elf64-alpha.c (elf64_alpha_size_dynamic_sections): Likewise.
	* elf64-hppa.c (elf64_hppa_size_dynamic_sections): Likewise.
	* elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise.
	* elf64-s390.c (elf_s390_size_dynamic_sections): Likewise.
	* elf64-sh64.c (sh64_elf64_size_dynamic_sections): Likewise.
	* elf64-x86-64.c (elf_x86_64_size_dynamic_sections): Likewise.
	* elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Likewise.
	* elfnn-ia64.c (elfNN_ia64_size_dynamic_sections): Likewise.
	* elfxx-mips.c (_bfd_mips_elf_size_dynamic_sections): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise.
	* elfxx-tilegx.c (tilegx_elf_size_dynamic_sections): Likewise.
ld/
	* ld.texinfo (--no-dynamic-linker): Document.
	* ldlex.h (enum option_values): Add OPTION_NO_DYNAMIC_LINKER.
	* lexsup.c (ld_options, parse_args): Handle --no-dynamic-linker.
 2015-09-20 15:52:27 +09:30
Nick Clifton
7bdf96efee Make register name tables in visium.h static in order to prevent multiple definitions. 
* visium.h (gen_reg_table): Make static.
	(fp_reg_table): Likewise.
	(cc_table): Likewise.
 2015-09-09 14:50:08 +01:00
Alan Modra
5f329d5b14 Reorder enum output_type for better code generation 
Works around a gcc bug #67328 for the most commonly used of bfd_link_pic
and bfd_link_executable.

	* bfdlink.h (enum output_type): Reorder enum.
 2015-08-23 23:21:48 +09:30
Jiong Wang
49df5539f9 [AArch64][3/6] GAS support TLSLD move/add relocation types 
2015-08-19  Jiong Wang  <jiong.wang@arm.com>

bfd/
  * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12,
  BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0,
  BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC,
  BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1,
  BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC,
  BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2): New entries.
  * elfnn-aarch64.c (elfNN_aarch64_howto_table): Likewise.
  * bfd-in2.h: Regenerate.
  * libbfd.h: Regenerate.

gas/
  * config/tc-aarch64.c (reloc_table): New relocation modifiers,
  "dtprel_hi12", "dtprel_g0", "dtprel_g0_nc", "dtprel_g1",
  "dtprel_g1_nc", "dtprel_g2".
  (md_apply_fix): Support new relocation types.
  (aarch64_force_relocation): Likewise.
  (process_movw_reloc_info): Likewise.

gas/testsuite/
  * gas/aarch64/reloc-dtprel_g0.s: New testcase.
  * gas/aarch64/reloc-dtprel_g0-ilp32.s: Likewise.
  * gas/aarch64/reloc-dtprel_g0_nc.s: Likewise.
  * gas/aarch64/reloc-dtprel_g0_nc-ilp32.s: Likewise.
  * gas/aarch64/reloc-dtprel_g1.s: Likewise.
  * gas/aarch64/reloc-dtprel_g1-ilp32.s: Likewise.
  * gas/aarch64/reloc-dtprel_g1_nc.s: Likewise.
  * gas/aarch64/reloc-dtprel_g2.s: Likewise.
  * gas/aarch64/reloc-dtprel_hi12.s: Likewise.
  * gas/aarch64/reloc-dtprel_hi12-ilp32.s: Likewise.
  * gas/aarch64/reloc-dtprel_g0.d: New expectation file.
  * gas/aarch64/reloc-dtprel_g0-ilp32.d: Likewise.
  * gas/aarch64/reloc-dtprel_g0_nc.d: Likewise.
  * gas/aarch64/reloc-dtprel_g0_nc-ilp32.d: Likewise.
  * gas/aarch64/reloc-dtprel_g1.d: Likewise.
  * gas/aarch64/reloc-dtprel_g1-ilp32.d: Likewise.
  * gas/aarch64/reloc-dtprel_g1_nc.d: Likewise.
  * gas/aarch64/reloc-dtprel_g2.d: Likewise.
  * gas/aarch64/reloc-dtprel_hi12.d: Likewise.
  * gas/aarch64/reloc-dtprel_hi12-ilp32.d: Likewise.
 2015-08-19 16:36:22 +01:00
Jiong Wang
13289c10e2 [AArch64][1/6] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 
2015-08-19  Jiong Wang  <jiong.wang@arm.com>

bfd/
  * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC): New entry.
  * bfd-in2.h: Regenerate.
  * libbfd.h: Regenerate.
  * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
  BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC.

gas/
  * config/tc-aarch64.c (reloc_table): New relocation modifiers.
  (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC.
  (aarch64_force_relocation): Likewise.

gas/testsuite/
  * gas/aarch64/reloc-dtprel_lo12_nc.s: New testcase.
  * gas/aarch64/reloc-dtprel_lo12_nc-ilp32.s: Likewise.
  * gas/aarch64/reloc-dtprel_lo12_nc.d: New expectation file.
  * gas/aarch64/reloc-dtprel_lo12_nc-ilp32.d: Likewise.
 2015-08-19 16:28:08 +01:00
Alan Modra
64d94ba01a Remove link_info.pic 
Adding type_pie to output_type allows us to remove link_info.pic and
with some reordering of the enum, produces better code.

include/
	* bfdlink.h (enum output_type): Delete type_executable, add type_pde
	and type_pie.  Reorder.
	(struct bfd_link_info): Delete pic field.
	(bfd_link_executable, bfd_link_pde, bfd_link_pie, bfd_link_pic): Adjust.
ld/
	* emultempl/aix.em: Don't set link_info.pic.
	* emultempl/pe.em: Likewise.
	* emultempl/pep.em: Likewise.
	* emultempl/sunos.em: Likewise.
	* lexsup.c (parse_args): Likewise.  Set type_pie for -pie.
	* plugin.c (set_tv_header <LDPT_LINKER_OUTPUT>): Simplify.
 2015-08-19 12:53:54 +09:30
Alan Modra
3cbc1e5e68 Add bfd_link_pde, and simplify some tests of link_info.type 
include/
	* bfdlink.h (bfd_link_pde): Define.
bfd/
	* elf-s390-common.c: Simplify expressions using
	bfd_linke_executable, bfd_link_pie and bfd_link_pic.
	* elf32-arm.c: Likewise.
	* elf32-bfin.c: Likewise.
	* elf32-frv.c: Likewise.
	* elf32-m68k.c: Likewise.
	* elf32-nios2.c: Likewise.
	* elf32-ppc.c: Likewise.
	* elf32-s390.c: Likewise.
	* elf32-sh.c: Likewise.
	* elf64-alpha.c: Likewise.
	* elf64-ppc.c: Likewise.
	* elf64-s390.c: Likewise.
	* elflink.c: Likewise.
 2015-08-19 12:51:06 +09:30
H.J. Lu
0e1862bb40 Add output_type to bfd_link_info 
The "shared" field in bfd_link_info is set for both DSO and and PIE.
There are separate fields for executable and relocatable outputs.  This
patch adds an "output_type" field:

enum output_type
{
  type_unknown = 0,
  type_executable,
  type_dll,
  type_relocatable
};

and a "pic" field to bfd_link_info to replace shared, executable and
relocatable fields so that we can use the "output_type" field to check
for output type and the "pic" field check if output is PIC.  Macros,
bfd_link_executable, bfd_link_dll, bfd_link_relocatable, bfd_link_pic
and bfd_link_pie, are provided to check for output features.

bfd/

	* bfd/aoutx.h: Replace shared, executable, relocatable and pie
	fields with bfd_link_executable, bfd_link_dll,
	bfd_link_relocatable, bfd_link_pic and bfd_link_pie.
	* bfd/bout.c: Likewise.
	* bfd/coff-alpha.c: Likewise.
	* bfd/coff-arm.c: Likewise.
	* bfd/coff-i386.c: Likewise.
	* bfd/coff-i960.c: Likewise.
	* bfd/coff-m68k.c: Likewise.
	* bfd/coff-mcore.c: Likewise.
	* bfd/coff-mips.c: Likewise.
	* bfd/coff-ppc.c: Likewise.
	* bfd/coff-rs6000.c: Likewise.
	* bfd/coff-sh.c: Likewise.
	* bfd/coff-tic80.c: Likewise.
	* bfd/coff-x86_64.c: Likewise.
	* bfd/coff64-rs6000.c: Likewise.
	* bfd/coffgen.c: Likewise.
	* bfd/cofflink.c: Likewise.
	* bfd/ecoff.c: Likewise.
	* bfd/ecofflink.c: Likewise.
	* bfd/elf-bfd.h: Likewise.
	* bfd/elf-eh-frame.c: Likewise.
	* bfd/elf-ifunc.c: Likewise.
	* bfd/elf-m10200.c: Likewise.
	* bfd/elf-m10300.c: Likewise.
	* bfd/elf-s390-common.c: Likewise.
	* bfd/elf-vxworks.c: Likewise.
	* bfd/elf.c: Likewise.
	* bfd/elf32-arm.c: Likewise.
	* bfd/elf32-avr.c: Likewise.
	* bfd/elf32-bfin.c: Likewise.
	* bfd/elf32-cr16.c: Likewise.
	* bfd/elf32-cr16c.c: Likewise.
	* bfd/elf32-cris.c: Likewise.
	* bfd/elf32-crx.c: Likewise.
	* bfd/elf32-d10v.c: Likewise.
	* bfd/elf32-dlx.c: Likewise.
	* bfd/elf32-epiphany.c: Likewise.
	* bfd/elf32-fr30.c: Likewise.
	* bfd/elf32-frv.c: Likewise.
	* bfd/elf32-ft32.c: Likewise.
	* bfd/elf32-h8300.c: Likewise.
	* bfd/elf32-hppa.c: Likewise.
	* bfd/elf32-i370.c: Likewise.
	* bfd/elf32-i386.c: Likewise.
	* bfd/elf32-i860.c: Likewise.
	* bfd/elf32-ip2k.c: Likewise.
	* bfd/elf32-iq2000.c: Likewise.
	* bfd/elf32-lm32.c: Likewise.
	* bfd/elf32-m32c.c: Likewise.
	* bfd/elf32-m32r.c: Likewise.
	* bfd/elf32-m68hc11.c: Likewise.
	* bfd/elf32-m68hc1x.c: Likewise.
	* bfd/elf32-m68k.c: Likewise.
	* bfd/elf32-mcore.c: Likewise.
	* bfd/elf32-mep.c: Likewise.
	* bfd/elf32-metag.c: Likewise.
	* bfd/elf32-microblaze.c: Likewise.
	* bfd/elf32-moxie.c: Likewise.
	* bfd/elf32-msp430.c: Likewise.
	* bfd/elf32-mt.c: Likewise.
	* bfd/elf32-nds32.c: Likewise.
	* bfd/elf32-nios2.c: Likewise.
	* bfd/elf32-or1k.c: Likewise.
	* bfd/elf32-ppc.c: Likewise.
	* bfd/elf32-rl78.c: Likewise.
	* bfd/elf32-rx.c: Likewise.
	* bfd/elf32-s390.c: Likewise.
	* bfd/elf32-score.c: Likewise.
	* bfd/elf32-score7.c: Likewise.
	* bfd/elf32-sh-symbian.c: Likewise.
	* bfd/elf32-sh.c: Likewise.
	* bfd/elf32-sh64.c: Likewise.
	* bfd/elf32-spu.c: Likewise.
	* bfd/elf32-tic6x.c: Likewise.
	* bfd/elf32-tilepro.c: Likewise.
	* bfd/elf32-v850.c: Likewise.
	* bfd/elf32-vax.c: Likewise.
	* bfd/elf32-visium.c: Likewise.
	* bfd/elf32-xc16x.c: Likewise.
	* bfd/elf32-xstormy16.c: Likewise.
	* bfd/elf32-xtensa.c: Likewise.
	* bfd/elf64-alpha.c: Likewise.
	* bfd/elf64-hppa.c: Likewise.
	* bfd/elf64-ia64-vms.c: Likewise.
	* bfd/elf64-mmix.c: Likewise.
	* bfd/elf64-ppc.c: Likewise.
	* bfd/elf64-s390.c: Likewise.
	* bfd/elf64-sh64.c: Likewise.
	* bfd/elf64-x86-64.c: Likewise.
	* bfd/elflink.c: Likewise.
	* bfd/elfnn-aarch64.c: Likewise.
	* bfd/elfnn-ia64.c: Likewise.
	* bfd/elfxx-mips.c: Likewise.
	* bfd/elfxx-sparc.c: Likewise.
	* bfd/elfxx-tilegx.c: Likewise.
	* bfd/i386linux.c: Likewise.
	* bfd/linker.c: Likewise.
	* bfd/m68klinux.c: Likewise.
	* bfd/pdp11.c: Likewise.
	* bfd/pe-mips.c: Likewise.
	* bfd/peXXigen.c: Likewise.
	* bfd/reloc.c: Likewise.
	* bfd/reloc16.c: Likewise.
	* bfd/sparclinux.c: Likewise.
	* bfd/sunos.c: Likewise.
	* bfd/vms-alpha.c: Likewise.
	* bfd/xcofflink.c: Likewise.

include/

	* include/bfdlink.h (output_type): New enum.
	(bfd_link_executable): New macro.
	(bfd_link_dll): Likewise.
	(bfd_link_relocatable): Likewise.
	(bfd_link_pic): Likewise.
	(bfd_link_pie): Likewise.
	(bfd_link_info): Remove shared, executable, pie and relocatable.
	Add output_type and pic.

ld/

	* ld/ldctor.c: Replace shared, executable, relocatable and pie
	fields with bfd_link_executable, bfd_link_dll,
	bfd_link_relocatable, bfd_link_pic and bfd_link_pie.
	* ld/ldemul.c: Likewise.
	* ld/ldfile.c: Likewise.
	* ld/ldlang.c: Likewise.
	* ld/ldmain.c: Likewise.
	* ld/ldwrite.c: Likewise.
	* ld/lexsup.c: Likewise.
	* ld/pe-dll.c: Likewise.
	* ld/plugin.c: Likewise.
	* ld/emultempl/aarch64elf.em: Likewise.
	* ld/emultempl/aix.em: Likewise.
	* ld/emultempl/alphaelf.em: Likewise.
	* ld/emultempl/armcoff.em: Likewise.
	* ld/emultempl/armelf.em: Likewise.
	* ld/emultempl/avrelf.em: Likewise.
	* ld/emultempl/beos.em: Likewise.
	* ld/emultempl/cr16elf.em: Likewise.
	* ld/emultempl/elf-generic.em: Likewise.
	* ld/emultempl/elf32.em: Likewise.
	* ld/emultempl/genelf.em: Likewise.
	* ld/emultempl/generic.em: Likewise.
	* ld/emultempl/gld960.em: Likewise.
	* ld/emultempl/gld960c.em: Likewise.
	* ld/emultempl/hppaelf.em: Likewise.
	* ld/emultempl/irix.em: Likewise.
	* ld/emultempl/linux.em: Likewise.
	* ld/emultempl/lnk960.em: Likewise.
	* ld/emultempl/m68hc1xelf.em: Likewise.
	* ld/emultempl/m68kcoff.em: Likewise.
	* ld/emultempl/m68kelf.em: Likewise.
	* ld/emultempl/metagelf.em: Likewise.
	* ld/emultempl/mipself.em: Likewise.
	* ld/emultempl/mmo.em: Likewise.
	* ld/emultempl/msp430.em: Likewise.
	* ld/emultempl/nds32elf.em: Likewise.
	* ld/emultempl/needrelax.em: Likewise.
	* ld/emultempl/nios2elf.em: Likewise.
	* ld/emultempl/pe.em: Likewise.
	* ld/emultempl/pep.em: Likewise.
	* ld/emultempl/ppc32elf.em: Likewise.
	* ld/emultempl/ppc64elf.em: Likewise.
	* ld/emultempl/sh64elf.em: Likewise.
	* ld/emultempl/solaris2.em: Likewise.
	* ld/emultempl/spuelf.em: Likewise.
	* ld/emultempl/sunos.em: Likewise.
	* ld/emultempl/tic6xdsbt.em: Likewise.
	* ld/emultempl/ticoff.em: Likewise.
	* ld/emultempl/v850elf.em: Likewise.
	* ld/emultempl/vms.em: Likewise.
	* ld/emultempl/vxworks.em: Likewise.
 2015-08-18 05:51:19 -07:00
H.J. Lu
dd419f3aac Sync ansidecl.h with GCC 
Sync with GCC
	2015-08-11  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>

	* ansidecl.h (GCC_FINAL): New macro.
 2015-08-12 05:02:21 -07:00
Jiong Wang
70151fb54a [AArch64][7/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12 
2015-08-11  Jiong Wang  <jiong.wang@arm.com>

include/elf/
  * aarch64.h (R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12): Define.

bfd/
  * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12): New entry.
  * bfd-in2.h: Regenerate.
  * libbfd.h: Regenerate.
  * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
  BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.

gas/
  * config/tc-aarch64.c (reloc_table): New relocation modifiers
  "dtprel_lo12".
  (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
  (aarch64_force_relocation): Likewise.

gas/testsuite/
  * gas/aarch64/reloc-dtprel_lo12-1.s: New testcase.
  * gas/aarch64/reloc-dtprel_lo12-ilp32-1.s: Likewise.
  * gas/aarch64/reloc-dtprel_lo12-1.d: New expectation file.
  * gas/aarch64/reloc-dtprel_lo12-ilp32-1.d: Likewise.
 2015-08-11 21:26:31 +01:00
Jiong Wang
56a2e4507a [AArch64][4/8] Add R_AARCH64_P32_TLSLD_ADD_LO12_NC in elf header 
2015-08-11  Jiong Wang  <jiong.wang@arm.com>

include/elf/
  * aarch64.h (R_AARCH64_P32_TLSLD_ADD_LO12_NC): Define.
 2015-08-11 21:25:32 +01:00
Jiong Wang
2c0a466a7f [AArch64][1/8] Add R_AARCH64_P32_TLSLD_ADR_PAGE21 in elf header 
2015-08-11  Jiong Wang  <jiong.wang@arm.com>

include/elf/
  * aarch64.h (R_AARCH64_P32_TLSLD_ADR_PAGE21): Define.
 2015-08-11 21:15:52 +01:00
H.J. Lu
72f4393d8c Remove leading/trailing white spaces in ChangeLog 2015-07-24 04:16:47 -07:00
Matthew Wahab
f33026a965 [ARM] Support correctly spelled ARMv6KZ architecture names 
2015-07-20  Matthew Wahab  <matthew.wahab@arm.com>

gas/
    * NEWS: Mention corrected spelling of armv6kz.
    * config/tc-arm.c (arm_cpus): Replace ARM_ARCH_V6ZK with
    ARM_ARCH_V6KZ.
    (arm_archs): Likewise. Also add "armv6kz" and "armv6kzt2".
    * doc/c-arm.texi: Replace "armv6zk" with "armv6kz".

gas/testsuite

    * gas/arm/attr-march-armv6kz.d: New.
    * gas/arm/attr-march-armv6kzt2.d: New.

include/opcode

    * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
    (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
    (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
    (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
 2015-07-21 09:43:35 +01:00
Jiong Wang
53e8fd0f07 [AArch64][1/3] Add R_AARCH64_P32_TLSLD_ADR_PREL21 in elf header 2015-07-16 15:38:32 +01:00
H.J. Lu
dc2edb520a Sync longlong.h with GCC 
Sync with GCC
	2014-10-28  Richard Henderson  <rth@redhat.com>

	* longlong.h [__alpha] (umul_ppmm): Disable for c++.
 2015-07-14 09:18:16 -07:00
H.J. Lu
d0270d8cb9 Sync hashtab.h, splay-tree.h with GCC 
Sync with GCC
	2014-12-09  Trevor Saunders  <tsaunders@mozilla.com>

	* hashtab.h, splay-tree.h: Remove GTY markers.
 2015-07-14 09:18:16 -07:00