If GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS is set on any input
relocatable files:
1. Don't generate copy relocations.
2. Turn off extern_protected_data since it implies
GNU_PROPERTY_NO_COPY_ON_PROTECTED.
3. Treate reference to protected symbols with indirect external access
as local.
4. Set GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS on output.
5. When generating executable, clear this bit when there are non-GOT or
non-PLT relocations in input relocatable files without the bit set.
6. Add -z [no]indirect-extern-access to control indirect external access.
bfd/
* elf-bfd (elf_obj_tdata): Add has_indirect_extern_access.
(elf_has_indirect_extern_access): New.
* elf-properties.c (_bfd_elf_parse_gnu_properties): Set
elf_has_indirect_extern_access and elf_has_no_copy_on_protected
when seeing GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS.
(elf_write_gnu_propertie): Add an argument to pass link_info.
Set needed_1_p for GNU_PROPERTY_1_NEEDED in memory.
(_bfd_elf_link_setup_gnu_properties): Handle
GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS for
-z indirect-extern-access. Set nocopyreloc to true and
extern_protected_data to false for indirect external access.
(_bfd_elf_convert_gnu_properties): Updated.
* elf32-i386.c (elf_i386_check_relocs): Set
non_got_ref_without_indirect_extern_access on legacy non-GOT or
non-PLT references.
* elf64-x86-64.c (elf_x86_64_check_relocs): Likewise.
* elflink.c (_bfd_elf_symbol_refs_local_p): Return true for
STV_PROTECTED symbols with indirect external access.
* elfxx-x86.c (_bfd_x86_elf_adjust_dynamic_symbol): Clear
indirect_extern_access for legacy non-GOT/non-PLT references.
* elfxx-x86.h (elf_x86_link_hash_entry): Add
non_got_ref_without_indirect_extern_access.
include/
* bfdlink.h (bfd_link_info): Add indirect_extern_access and
needed_1_p. Change nocopyreloc to int.
ld/
* NEWS: Mention -z [no]indirect-extern-access
* ld.texi: Document -z [no]indirect-extern-access
* ldmain.c (main): Initialize link_info.indirect_extern_access
to -1.
* emulparams/extern_protected_data.sh: Support
-z [no]indirect-extern-access.
* testsuite/ld-elf/indirect-extern-access-1.rd: New file
* testsuite/ld-elf/indirect-extern-access-1a.c: Likewise.
* testsuite/ld-elf/indirect-extern-access-1b.c: Likewise.
* testsuite/ld-elf/indirect-extern-access-2.rd: Likewise.
* testsuite/ld-elf/indirect-extern-access-2a.c: Likewise.
* testsuite/ld-elf/indirect-extern-access-2b.c: Likewise.
* testsuite/ld-elf/indirect-extern-access-3.rd: Likewise.
* testsuite/ld-elf/indirect-extern-access.S: Likewise.
* testsuite/ld-elf/property-1_needed-1b.d: Likewise.
* testsuite/ld-elf/property-1_needed-1c.d: Likewise.
* testsuite/ld-x86-64/indirect-extern-access.rd: Likewise.
* testsuite/ld-x86-64/protected-data-1.h: Likewise.
* testsuite/ld-x86-64/protected-data-1a.c: Likewise.
* testsuite/ld-x86-64/protected-data-1b.c: Likewise.
* testsuite/ld-x86-64/protected-data-2a.S: Likewise.
* testsuite/ld-x86-64/protected-data-2b.S: Likewise.
* testsuite/ld-x86-64/protected-func-2a.S: Likewise.
* testsuite/ld-x86-64/protected-func-2b.S: Likewise.
* testsuite/ld-x86-64/protected-func-2c.c: Likewise.
* testsuite/ld-elf/linux-x86.exp: Run test with
GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS.
* testsuite/ld-x86-64/x86-64.exp: Run tests for protected
function and data with indirect external access.
Add GNU_PROPERTY_1_NEEDED:
#define GNU_PROPERTY_1_NEEDED GNU_PROPERTY_UINT32_OR_LO
to indicate the needed properties by the object file.
Add GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS:
#define GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS (1U << 0)
to indicate that the object file requires canonical function pointers and
cannot be used with copy relocation.
binutils/
* readelf.c (decode_1_needed): New.
(print_gnu_property_note): Handle GNU_PROPERTY_1_NEEDED.
include/
* elf/common.h (GNU_PROPERTY_1_NEEDED): New.
(GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS): Likewise.
ld/
* testsuite/ld-elf/property-1_needed-1a.d: New file.
* testsuite/ld-elf/property-1_needed-1.s: Likewise.
When link_info.keep_memory is true, linker caches the relocation
information and symbol tables of input files in memory. When there
are many input files with many relocations, we may run out of memory.
Add --max-cache-size=SIZE to set the maximum cache size.
bfd/
PR ld/18028
* bfd.c (bfd): Add alloc_size.
* elf-bfd.h (_bfd_elf_link_info_read_relocs): New.
* elf32-i386.c (elf_i386_check_relocs): Use _bfd_link_keep_memory.
Update cache_size.
* elf64-x86-64.c (elf_x86_64_check_relocs): Likewise.
* elflink.c (_bfd_elf_link_read_relocs): Renamed to ...
(_bfd_elf_link_info_read_relocs): This. Update cache_size.
(_bfd_elf_link_read_relocs): New.
(_bfd_elf_link_check_relocs): Call _bfd_elf_link_info_read_relocs
instead of _bfd_elf_link_read_relocs.
(elf_link_add_object_symbols): Likewise.
(elf_link_input_bfd): Likewise.
(init_reloc_cookie_rels): Likewise.
(init_reloc_cookie): Update cache_size. Call
_bfd_elf_link_info_read_relocs instead of
_bfd_elf_link_read_relocs.
(link_info_ok): New.
(elf_gc_smash_unused_vtentry_relocs): Updated. Call
_bfd_elf_link_info_read_relocs instead of
_bfd_elf_link_read_relocs.
(bfd_elf_gc_sections): Use link_info_ok. Pass &link_info_ok
to elf_gc_smash_unused_vtentry_relocs.
* libbfd-in.h (_bfd_link_keep_memory): New.
* linker.c (_bfd_link_keep_memory): New.
* opncls.c (bfd_alloc): Update alloc_size.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
include/
PR ld/18028
* bfdlink.h (bfd_link_info): Add cache_size and max_cache_size.
ld/
PR ld/18028
* NEWS: Mention --max-cache-size=SIZE.
* ld.texi: Document --max-cache-size=SIZE.
* ldlex.h (option_values): Add OPTION_MAX_CACHE_SIZE.
* ldmain.c: (main): Set link_info.max_cache_size to -1.
* lexsup.c (ld_options): Add --max-cache-size=SIZE.
(parse_args): Support OPTION_MAX_CACHE_SIZE.
* testsuite/ld-bootstrap/bootstrap.exp: Add test for
--max-cache-size=-1.
Although the XScale and its iwMMX extensions are implemented in the
Arm co-processor space, they are not considered to be part of the FPU
specification. In particular, they cannot be enabled or disabled via
a .fpu directive. It's therefore incorrect to strip these properties
when a new .fpu directive is encountered.
Note that the legacy Maverick co-processor is considered to be a FPU
and it is possible to control this via the .fpu directive.
include:
PR gas/28031
* opcode/arm.h (FPU_ANY): Exclude XScale-related features.
This helps these funcs get printf format checking coverage.
The sim-io.c hack as a result is a bit unfortunate, but the compiler
throws warnings when printing with empty strings. In this one case,
we actually want that due to the side-effect of the callback halting
execution for us.
This will make it easier to emulate the syscall. If the kill target
is the sim itself, don't do anything. This forces the higher layers
to make a decision as to how to handle this event: like halting the
overall engine process.
Implement GNU_PROPERTY_UINT32_AND_XXX/GNU_PROPERTY_UINT32_OR_XXX:
https://sourceware.org/pipermail/gnu-gabi/2021q1/000467.html
1. GNU_PROPERTY_UINT32_AND_LO..GNU_PROPERTY_UINT32_AND_HI
#define GNU_PROPERTY_UINT32_AND_LO 0xb0000000
#define GNU_PROPERTY_UINT32_AND_HI 0xb0007fff
A bit in the output pr_data field is set only if it is set in all
relocatable input pr_data fields. If all bits in the the output
pr_data field are zero, this property should be removed from output.
If the bit is 1, all input relocatables have the feature. If the
bit is 0 or the property is missing, the info is unknown.
2. GNU_PROPERTY_UINT32_OR_LO..GNU_PROPERTY_UINT32_OR_HI
#define GNU_PROPERTY_UINT32_OR_LO 0xb0008000
#define GNU_PROPERTY_UINT32_OR_HI 0xb000ffff
A bit in the output pr_data field is set if it is set in any
relocatable input pr_data fields. If all bits in the the output
pr_data field are zero, this property should be removed from output.
If the bit is 1, some input relocatables have the feature. If the
bit is 0 or the property is missing, the info is unknown.
bfd/
* elf-properties.c (_bfd_elf_parse_gnu_properties): Handle
GNU_PROPERTY_UINT32_AND_LO, GNU_PROPERTY_UINT32_AND_HI,
GNU_PROPERTY_UINT32_OR_LO and GNU_PROPERTY_UINT32_OR_HI.
(elf_merge_gnu_properties): Likewise.
binutils/
* readelf.c (print_gnu_property_note): Handle
GNU_PROPERTY_UINT32_AND_LO, GNU_PROPERTY_UINT32_AND_HI,
GNU_PROPERTY_UINT32_OR_LO and GNU_PROPERTY_UINT32_OR_HI.
include/
* elf/common.h (GNU_PROPERTY_UINT32_AND_LO): New.
(GNU_PROPERTY_UINT32_AND_HI): Likewise.
(GNU_PROPERTY_UINT32_OR_LO): Likewise.
(GNU_PROPERTY_UINT32_OR_HI): Likewise.
ld/
* testsuite/ld-elf/property-and-1.d: New file.
* testsuite/ld-elf/property-and-1.s: Likewise.
* testsuite/ld-elf/property-and-2.d: Likewise.
* testsuite/ld-elf/property-and-2.s: Likewise.
* testsuite/ld-elf/property-and-3.d: Likewise.
* testsuite/ld-elf/property-and-3.s: Likewise.
* testsuite/ld-elf/property-and-4.d: Likewise.
* testsuite/ld-elf/property-and-empty.s: Likewise.
* testsuite/ld-elf/property-or-1.d: Likewise.
* testsuite/ld-elf/property-or-1.s: Likewise.
* testsuite/ld-elf/property-or-2.d: Likewise.
* testsuite/ld-elf/property-or-2.s: Likewise.
* testsuite/ld-elf/property-or-3.d: Likewise.
* testsuite/ld-elf/property-or-3.s: Likewise.
* testsuite/ld-elf/property-or-4.d: Likewise.
* testsuite/ld-elf/property-or-empty.s: Likewise.
The idea of this change is simple: Populate a data structure, namely
"disasm_option_and_arg_t" from "include/dis-asm.h", to encompass the
disassembly options and their possible arguments.
This will make it easier to manage or extend those options by adapting
entries in a data structure, "arc_options". There will be lesser need
to hard-code the options in the code itself. Moreover, ARC GDB will
use this population function, "disassembler_options_arc ()", to enable
the "set disassembler-option" for ARC targets. The gdb change will be
in a separate patch though.
The changes in this patch can be divided into:
1) Introduction of "disassembler_options_arc ()" that will return a
"disasm_option_and_arg_t" structure representing the disassembly
options and their likely arguments.
2) New data type "arc_options_arg_t" and new data "arc_options".
These are the internals for keeping track of options and arguments
entries that can easily be extended.
3) To print the options, the "print_arc_disassembler_options ()" has
been adjusted to use this dynamically built structure instead of having
them hard-coded inside.
To see this in effect, one can look into the output of:
$ ./binutils/objdump --help
...
The following ARC specific disassembler options are...
...
include/ChangeLog:
* dis-asm.h (disassembler_options_arc): New prototype.
opcodes/ChangeLog:
* arc-dis.c (arc_option_arg_t): New enumeration.
(arc_options): New variable.
(disassembler_options_arc): New function.
(print_arc_disassembler_options): Reimplement in terms of
"disassembler_options_arc".
Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and
handle the exclusion for any ISA levels properly in `opcode_is_member'.
Flatten the structure of the `if' statements there. No functional
change for the existing opcode tables.
include/
* opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA
exclusion.
(opcode_is_member): Handle ISA level exclusion.
In preparation for the next change factor out code for ISA matching
against instruction flags used in MIPS opcode tables, similarly to how
CPU matching is already done. No functional change, though for clarity
split the single `if' statement into multiple ones and use temporaries
rather than repeated expressions.
include/
* opcode/mips.h (isa_is_member): New inline function, factored
out from...
(opcode_is_member): ... here.
The CP0 control register set has never been defined, however encodings
for the CFC0 and CTC0 instructions remained available for implementers
up until the MIPS32 ISA declared them invalid and causing the Reserved
Instruction exception[1]. Therefore we handle them for both assembly
and disassembly, however in the latter case the names of CP0 registers
from the regular set are incorrectly printed if named registers are
requested. This is because we do not define separate operand classes
for coprocessor regular and control registers respectively, which means
the disassembler has no way to tell the two cases apart. Consequently
nonsensical disassembly is produced like:
cfc0 v0,c0_random
Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0
instructions[2] although it failed to document them in the relevant
opcode table until MIPSr6 only.
Correct the issue then by defining a new register class, OP_REG_CONTROL,
and corresponding operand codes, `g' and `y' for the two positions in
the machine instruction a control register operand can take. Adjust the
test cases affected accordingly.
While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries
with each other so that they come in the alphabetical order.
References:
[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of
rs Field", p. 242
[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of
Instructions", pp. 195, 216
include/
* opcode/mips.h: Document `g' and `y' operand codes.
(mips_reg_operand_type): Add OP_REG_CONTROL enumeration
constant.
gas/
* tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G'
operand code.
opcodes/
* mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
handling code over to...
<OP_REG_CONTROL>: ... this new case.
* mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
(mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
"cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
replacing the `G' operand code with `g'. Update "cftc1" and
"cftc2" entries replacing the `E' operand code with `y'.
* micromips-opc.c (decode_micromips_operand) <'g'>: New case.
(micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
entries replacing the `G' operand code with `g'.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0
operand disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
In the operand handling rewrite made for the MIPS disassembler with
commit ab90248154 ("Add structures to describe MIPS operands"),
<https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g'
operand code has become redundant for the regular MIPS instruction set
by duplicating the OP_REG_COPRO semantics of the `G' operand code.
Later commit 351cdf24d2 ("Implement O32 FPXX, FP64 and FP64A ABI
extensions") converted the CTTC1 instruction from the `g' to the `G'
operand code, but still left a few instructions behind.
Convert the three remaining instructions still using the `g' code then,
namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand
code, freeing it up for other use.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
and "mtthc2" to using the `G' rather than `g' operand code for
the coprocessor control register referred.
include/
* opcode/mips.h: Complement change made to opcodes and remove
references to the `g' regular MIPS ISA operand code.
commit a7664973b2
Author: Jan Beulich <jbeulich@suse.com>
Date: Mon Apr 26 10:41:35 2021 +0200
x86: correct overflow checking for 16-bit PC-relative relocs
caused linker failure when building 16-bit program in a 32-bit ELF
container. Update GNU_PROPERTY_X86_FEATURE_2_USED with
#define GNU_PROPERTY_X86_FEATURE_2_CODE16 (1U << 12)
to indicate that 16-bit mode instructions are used in the input object:
https://groups.google.com/g/x86-64-abi/c/UvvXWeHIGMA
to indicate that 16-bit mode instructions are used in the object to
allow linker to properly perform relocation overflow check for 16-bit
PC-relative relocations in 16-bit mode instructions.
1. Update x86 assembler to always generate the GNU property note with
GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object.
2. Update i386 and x86-64 linkers to use 16-bit PC16 relocations if
input object is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16.
bfd/
PR ld/27905
* elf32-i386.c: Include "libiberty.h".
(elf_howto_table): Add 16-bit R_386_PC16 entry.
(elf_i386_rtype_to_howto): Add a BFD argument. Use 16-bit
R_386_PC16 if input has 16-bit mode instructions.
(elf_i386_info_to_howto_rel): Update elf_i386_rtype_to_howto
call.
(elf_i386_tls_transition): Likewise.
(elf_i386_relocate_section): Likewise.
* elf64-x86-64.c (x86_64_elf_howto_table): Add 16-bit
R_X86_64_PC16 entry.
(elf_x86_64_rtype_to_howto): Use 16-bit R_X86_64_PC16 if input
has 16-bit mode instructions.
* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Set
elf_x86_has_code16 if relocatable input is marked with
GNU_PROPERTY_X86_FEATURE_2_CODE16.
* elfxx-x86.h (elf_x86_obj_tdata): Add has_code16.
(elf_x86_has_code16): New.
binutils/
PR ld/27905
* readelf.c (decode_x86_feature_2): Support
GNU_PROPERTY_X86_FEATURE_2_CODE16.
gas/
PR ld/27905
* config/tc-i386.c (set_code_flag): Update x86_feature_2_used
with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF
object.
(set_16bit_gcc_code_flag): Likewise.
(x86_cleanup): Always generate the GNU property note if
x86_feature_2_used isn't 0.
* testsuite/gas/i386/code16-2.d: New file.
* testsuite/gas/i386/code16-2.s: Likewise.
* testsuite/gas/i386/x86-64-code16-2.d: Likewise.
* testsuite/gas/i386/i386.exp: Run code16-2 and x86-64-code16-2.
include/
PR ld/27905
* elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): New.
ld/
PR ld/27905
* testsuite/ld-i386/code16.d: New file.
* testsuite/ld-i386/code16.t: Likewise.
* testsuite/ld-x86-64/code16.d: Likewise.
* testsuite/ld-x86-64/code16.t: Likewise.
* testsuite/ld-i386/i386.exp: Run code16.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
The official name for Loongson Architecture is LoongArch, it is better
to use LoongArch instead of Loongson Loongarch for EM_LOONGARCH to avoid
confusion and keep consistent with the various of software in the future.
The official documentation in Chinese:
http://www.loongson.cn/uploadfile/cpu/LoongArch.pdf
The translated version in English:
https://loongson.github.io/LoongArch-Documentation/
binutils/
* readelf.c (get_machine_name): Change Loongson Loongarch to
LoongArch.
include/
* elf/common.h (EM_LOONGARCH): Change Loongson Loongarch to
LoongArch.
Rather than rely on off_t being the right size between the host &
target, have the interface always be 64-bit. We can figure out if
we need to truncate when actually outputting it to the right target.
PR sim/27705
Rather than rely on time_t being the right size between the host &
target, have the interface always be 64-bit. We can figure out if
we need to truncate when actually outputting it to the right target.
The gdb/callback.h & gdb/remote-sim.h headers have nothing to do with
gdb and are really definitions for the libsim API under the sim/ tree.
While gdb uses those headers as a client, it's not specific to it. So
create a new sim/ namespace and move the headers there.
The libiberty hash table includes a helper function for strings, but
no equality function. Consequently, this equality function has been
reimplemented a number of times in both the gcc and binutils-gdb
source trees. This patch adds the function to the libiberty hash
table, as a step toward the goal of removing all the copies.
One change to gcc is included here. Normally I would have put this in
the next patch, but gensupport.c used the most natural name for its
reimplementation of this function, and this can't coexist with the
extern function in libiberty.
include
* hashtab.h (htab_eq_string): Declare.
libiberty
* hashtab.c (htab_eq_string): New function.
The gotha() relocation mnemonic will be outputted by OpenRISC GCC when
using the -mcmodel=large option. This relocation is used along with
got() to generate 32-bit GOT offsets. This increases the previous GOT
offset limit from the previous 16-bit (64K) limit.
This is needed on large binaries where the GOT grows larger than 64k.
bfd/ChangeLog:
PR 21464
* bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation.
* elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise.
(or1k_final_link_relocate, or1k_elf_relocate_section,
or1k_elf_check_relocs): Likewise.
* libbfd.h (bfd_reloc_code_real_names): Likewise.
* reloc.c: Likewise.
cpu/ChangeLog:
PR 21464
* or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic
for gotha() relocation.
include/ChangeLog:
PR 21464
* elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number.
opcodes/ChangeLog:
PR 21464
* or1k-asm.c: Regenerate.
gas/ChangeLog:
PR 21464
* testsuite/gas/or1k/reloc-1.s: Add test for new relocation.
* testsuite/gas/or1k/reloc-1.d: Add test result for new
relocation.
Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
fixup reloc, add tests
Before now, types that could not be encoded in CTF were represented as
references to type ID 0, which does not itself appear in the
dictionary. This choice is annoying in several ways, principally that it
forces generators and consumers of CTF to grow special cases for types
that are referenced in valid dicts but don't appear.
Allow an alternative representation (which will become the only
representation in format v4) whereby nonrepresentable types are encoded
as actual types with kind CTF_K_UNKNOWN (an already-existing kind
theoretically but not in practice used for padding, with value 0).
This is backward-compatible, because CTF_K_UNKNOWN was not used anywhere
before now: it was used in old-format function symtypetabs, but these
were never emitted by any compiler and the code to handle them in libctf
likely never worked and was removed last year, in favour of new-format
symtypetabs that contain only type IDs, not type kinds.
In order to link this type, we need an API addition to let us add types
of unknown kind to the dict: we let them optionally have names so that
GCC can emit many different unknown types and those types with identical
names will be deduplicated together. There are also small tweaks to the
deduplicator to actually dedup such types, to let opening of dicts with
unknown types with names work, to return the ECTF_NONREPRESENTABLE error
on resolution of such types (like ID 0), and to print their names as
something useful but not a valid C identifier, mostly for the sake of
the dumper.
Tests added in the next commit.
include/ChangeLog
2021-05-06 Nick Alcock <nick.alcock@oracle.com>
* ctf.h (CTF_K_UNKNOWN): Document that it can be used for
nonrepresentable types, not just padding.
* ctf-api.h (ctf_add_unknown): New.
libctf/ChangeLog
2021-05-06 Nick Alcock <nick.alcock@oracle.com>
* ctf-open.c (init_types): Unknown types may have names.
* ctf-types.c (ctf_type_resolve): CTF_K_UNKNOWN is as
non-representable as type ID 0.
(ctf_type_aname): Print unknown types.
* ctf-dedup.c (ctf_dedup_hash_type): Do not early-exit for
CTF_K_UNKNOWN types: they have real hash values now.
(ctf_dedup_rwalk_one_output_mapping): Treat CTF_K_UNKNOWN types
like other types with no referents: call the callback and do not
skip them.
(ctf_dedup_emit_type): Emit via...
* ctf-create.c (ctf_add_unknown): ... this new function.
* libctf.ver (LIBCTF_1.2): Add it.
bfd/ChangeLog:
* coff-rs6000.c (_bfd_xcoff_swap_aux_in): Add errors for
unsupported storage class or auxialiry entries.
Improve and adapt to new aux structures.
Add C_DWARF support.
(_bfd_xcoff_swap_aux_out): Likewise.
* coff64-rs6000.c (_bfd_xcoff64_swap_aux_in): Likewise.
(_bfd_xcoff64_swap_aux_out): Likewise.
binutils/ChangeLog:
* od-xcoff.c (dump_xcoff32_symbols): Adapt to new
aux structures.
include/ChangeLog:
* coff/internal.h (union internal_auxent):
Add x_sect structure.
* coff/rs6000.h (union external_auxent): Rework to
match official documentation.
* coff/rs6k64.h (union external_auxent): Likewise.
(_AUX_SECT): New define.
PR 27760
include * coff/pe.h (IMAGE_DLLCHARACTERISTICS_APPCONTAINER): Define.
(IMAGE_DLLCHARACTERISTICS_GUARD_CF): Define.
bfd * peXXigen.c (_bfd_XX_print_private_bfd_data_common): Add display
of IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP,
IMAGE_FILE_NET_RUN_FROM_SWAP and IMAGE_FILE_UP_SYSTEM_ONLY flags.
Decode the contents of the DllCharacteristics field.
So don't set those flags for an executable. In the patch I also test
DYNAMIC even though the PE bfd code doesn't appear to set it for dlls.
I figure it doesn't hurt to include that flag too.
PR 27567
bfd/
* coffcode.h (styp_to_sec_flags): Use an unsigned long styp_flags.
(coff_write_object_contents): Pass bfd to COFF_ENCODE_ALIGNMENT,
ignore alignment checks when return is false. Formatting.
include/
* coff/internal.h (struct internal_scnhdr): Make s_flags unsigned long.
* coff/pe.h (COFF_ENCODE_ALIGNMENT): Don't set align flags for an
executable and return false. Do so for a relocatable object and
evaluate to true.
* coff/ti.h (COFF_ENCODE_ALIGNMENT): Add bfd arg and evaluate to true.
(COFF_DECODE_ALIGNMENT): Formatting.
* coff/z80.h (COFF_ENCODE_ALIGNMENT): Similarly.
(COFF_DECODE_ALIGNMENT): Similarly.
This adds some annotation to Power10 pcrel instructions, displaying
the target address (ie. pc + D34 field) plus a symbol if there is one
at exactly that target address. pld from the .got or .plt will also
look up the entry and display it, symbolically if there is a dynamic
relocation on the entry.
include/
* dis-asm.h (struct disassemble_info): Add dynrelbuf and dynrelcount.
binutils/
* objdump.c (struct objdump_disasm_info): Delete dynrelbuf and
dynrelcount.
(find_symbol_for_address): Adjust for dynrelbuf and dynrelcount move.
(disassemble_section, disassemble_data): Likewise.
opcodes/
* ppc-dis.c (struct dis_private): Add "special".
(POWERPC_DIALECT): Delete. Replace uses with..
(private_data): ..this. New inline function.
(disassemble_init_powerpc): Init "special" names.
(skip_optional_operands): Add is_pcrel arg, set when detecting R
field of prefix instructions.
(bsearch_reloc, print_got_plt): New functions.
(print_insn_powerpc): For pcrel instructions, print target address
and symbol if known, and decode plt and got loads too.
gas/
* testsuite/gas/ppc/prefix-pcrel.d: Update expected output.
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
* gas/testsuite/gas/ppc/vsx_32byte.d: Likewise.
ld/
* testsuite/ld-powerpc/inlinepcrel-1.d: Update expected output.
* testsuite/ld-powerpc/inlinepcrel-2.d: Likewise.
* testsuite/ld-powerpc/notoc2.d: Likewise.
* testsuite/ld-powerpc/notoc3.d: Likewise.
* testsuite/ld-powerpc/pcrelopt.d: Likewise.
* testsuite/ld-powerpc/startstop.d: Likewise.
* testsuite/ld-powerpc/tlsget.d: Likewise.
* testsuite/ld-powerpc/tlsget2.d: Likewise.
* testsuite/ld-powerpc/tlsld.d: Likewise.
* testsuite/ld-powerpc/weak1.d: Likewise.
* testsuite/ld-powerpc/weak1so.d: Likewise.
This turns into a signed left shift by 31 bits, otherwise. This is an
offset and is always treated as unsigned in any case, so add an
appropriate cast.
include/ChangeLog
2021-03-25 Nick Alcock <nick.alcock@oracle.com>
PR libctf/27628
* ctf-api.h: Fix some indentation.
(CTF_SET_STID): Always do an unsigned shift, even if STID is
signed.
AArch64 MTE support in the Linux kernel exposes a new register
through ptrace. This patch adds the required code to support it.
include/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* elf/common.h (NT_ARM_TAGGED_ADDR_CTRL): Define.
gdb/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* aarch64-linux-nat.c (fetch_mteregs_from_thread): New function.
(store_mteregs_to_thread): New function.
(aarch64_linux_nat_target::fetch_registers): Update to call
fetch_mteregs_from_thread.
(aarch64_linux_nat_target::store_registers): Update to call
store_mteregs_to_thread.
* aarch64-tdep.c (aarch64_mte_register_names): New struct.
(aarch64_cannot_store_register): Handle MTE registers.
(aarch64_gdbarch_init): Initialize and setup MTE registers.
* aarch64-tdep.h (gdbarch_tdep) <mte_reg_base>: New field.
<has_mte>: New method.
* arch/aarch64-linux.h (AARCH64_LINUX_SIZEOF_MTE): Define.
gdbserver/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* linux-aarch64-low.cc (aarch64_fill_mteregset): New function.
(aarch64_store_mteregset): New function.
(aarch64_regsets): Add MTE register set entry.
(aarch64_sve_regsets): Add MTE register set entry.
* peXXigen.c (_bfd_XXi_swap_aux_out): Avoid potential buffer
overrun by using sizeof of the destination x_fname field as the
limit for a memcpy.
* coff/internal.h (struct internal_auxent): Fix a couple of typos
in comment describing the x_fname field.
