This patch sets GUILE to just plain 'guile'.
In the distant ("devo") past, the top-level build did support building
Guile in-tree. However, I don't think this really works any more.
For one thing, there are no build dependencies on it, so there's no
guarantee it would actually be built before the uses.
This patch also removes the use of "-s" as an option to cgen scheme
scripts. With my latest patch upstream, this is no longer needed.
After the upstream changes, either Guile 2 or Guile 3 will work, with
or without the compiler enabled.
2023-08-24 Tom Tromey <tom@tromey.com>
* cgen.sh: Don't pass "-s" to cgen.
* Makefile.in: Rebuild.
* Makefile.am (GUILE): Simplify.
This patch fixes a regression recently introduced in the BPF
disassembler, that was assuming an abfd was always available in
info->section->owner. Apparently this is not so in GDB, and therefore
https://sourceware.org/bugzilla/show_bug.cgi?id=30705.
Tested in bpf-unkonwn-none.
opcodes/ChangeLog:
2023-07-31 Jose E. Marchesi <jose.marchesi@oracle.com>
PR 30705
* bpf-dis.c (print_insn_bpf): Check that info->section->owner is
actually available before using it.
This patch adds support for EF_BPF_CPUVER bits in the ELF
machine-dependent header flags. These bits encode the BPF CPU
version for which the object file has been compiled for.
The BPF assembler is updated so it annotates the object files it
generates with these bits.
The BPF disassembler is updated so it honors EF_BPF_CPUVER to use the
appropriate ISA version if the user didn't specify an explicit ISA
version in the command line. Note that a value of zero in
EF_BPF_CPUVER is interpreted by the disassembler as "use the later
supported version" (the BPF CPU versions start with v1.)
The readelf utility is updated to pretty print EF_BPF_CPUVER when it
prints out the ELF header:
$ readelf -h a.out
ELF Header:
...
Flags: 0x4, CPU Version: 4
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/bpf.h (EF_BPF_CPUVER): Define.
* opcode/bpf.h (BPF_XBPF): Change from 0xf to 0xff so it fits in
EF_BPF_CPUVER.
binutils/ChangeLog:
2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* readelf.c (get_machine_flags): Recognize and pretty print BPF
machine flags.
opcodes/ChangeLog:
2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-dis.c: Initialize asm_bpf_version to -1.
(print_insn_bpf): Set BPF ISA version from the cpu version ELF
header flags if no explicit version set in the command line.
* disassemble.c (disassemble_init_for_target): Remove unused code.
gas/ChangeLog:
2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.h (elf_tc_final_processing): Define.
* config/tc-bpf.c (bpf_elf_final_processing): New function.
This patch fixes the BPF_INSN_NEGR and BPF_INSN_NEG32R BPF
instructions to not use their source registers.
Tested in bpf-unknown-none.
opcodes/ChangeLog:
2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src
register.
gas/ChangeLog:
2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.s: The register neg instruction gets only
one argument.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu32.s: Likewise.
* doc/c-bpf.texi (BPF Instructions): Update accordingly.
This patch adds support for the BPF V4 ISA byte swap instructions to
opcodes, assembler and disassembler.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (BPF_IMM32_BSWAP16): Define.
(BPF_IMM32_BSWAP32): Likewise.
(BPF_IMM32_BSWAP64): Likewise.
(enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}.
opcodes/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
instructions.
gas/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions.
* testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions.
* testsuite/gas/bpf/alu.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
This patch fixes the pseudoc syntax of the V4 instructions MOVS* and
LDXS* in order to reflect https://reviews.llvm.org/D144829.
opcodes/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
instructions.
gas/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-bpf.texi (BPF Instructions): Fix pseudoc syntax for MOVS*
and LDXS* instructions.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
This patch adds support for the V4 BPF instruction jal/gotol, which is
like ja/goto but it supports a signed 32-bit PC-relative (in number of
64-bit words minus one) target operand instead of the 16-bit signed
operand of the other instruction. This greatly increases the jump
range in BPF programs.
Tested in bpf-unkown-none.
bfd/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32.
* elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc.
* libbfd.h (bfd_reloc_code_real_names): Regenerate.
gas/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (struct bpf_insn): New field `id'.
(md_assemble): Save the ids of successfully parsed instructions
and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate.
(md_apply_fix): Adapt to the new BFD reloc.
* testsuite/gas/bpf/jump.s: Test JAL.
* testsuite/gas/bpf/jump.d: Likewise.
* testsuite/gas/bpf/jump-pseudoc.d: Likewise.
* testsuite/gas/bpf/jump-be.d: Likewise.
* testsuite/gas/bpf/jump-be-pseudoc.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document new instruction
jal/gotol.
Document new operand type disp32.
include/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL.
(enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI.
opcodes/ChangeLog:
2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entry for jal.
This commit adds the signed load to register (ldxs*) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Add entries for signed load
instructions.
(BPF_MODE_SMEM): Define.
opcodes/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
instructions.
gas/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.s: Add signed load instructions.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/mem.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document the signed load
instructions.
This commit adds the signed register move (movs) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (BPF_OFFSET16_MOVS8): Define.
(BPF_OFFSET16_MOVS16): Likewise.
(BPF_OFFSET16_MOVS32): Likewise.
(enum bpf_insn_id): Add entries for MOVS{8,16,32}R and
MOVS32{8,16,32}R.
opcodes/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
MOVS32{8,16,32}R instructions. and MOVS32I instructions.
gas/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.s: Test movs instructions.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu.d: Add expected results.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
This was breaking --enable-targets=all builds.
opcodes/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c
* Makefile.in: Regenerate.
A recent change in opcodes/i386-dis.c caused a build failure on my
x86-64 Fedora 36 system, which uses:
$ gcc --version
gcc (GCC) 12.2.1 20221121 (Red Hat 12.2.1-4)
[...]
The error is:
../../binutils-gdb/opcodes/i386-dis.c: In function ‘OP_J’:
../../binutils-gdb/opcodes/i386-dis.c:12705:22: error: ‘val’ may be used uninitialized [-Werror=maybe-uninitialized]
12705 | disp = val & 0x8000 ? val - 0x10000 : val;
| ~~~~^~~~~~~~
This patch fixes the warning.
opcodes/ChangeLog
2023-04-21 Tom Tromey <tromey@adacore.com>
* i386-dis.c (OP_J): Check result of get16.
The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
This patch changes the address for "isa_config" auxiliary register
from 0xC2 to the correct value 0xC1. Moreover, it only exists in
arc700+ and not all ARCs.
opcodes/ChangeLog:
* arc-regs.h: Change isa_config address to 0xc1.
isa_config exists for ARC700 and ARCV2 and not ARCALL.
Update the ARC disassembler to supply style information to the
disassembler output. The output formatting remains unchanged.
opcodes/ChangeLog:
* disassemble.c (disassemble_init_for_target): Set
created_styled_output for ARC based targets.
* arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
instead of fprintf_ftype throughout.
(find_format): Likewise.
(print_flags): Likewise.
(print_insn_arc): Likewise.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
* disassemble.c: (disassemble_init_for_target): Set
created_styled_output for AVR based targets.
* avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
instead of fprintf_ftype throughout.
(avr_operand): Pass in and fill disassembler_style when
parsing operands.
So far z16 was identified as arch14. After the machine has been
announced we can now add the real name.
gas/ChangeLog:
* config/tc-s390.c (s390_parse_cpu): Add z16 as alternate CPU
name.
* doc/as.texi: Add z16 and arch14 to CPU string list.
* doc/c-s390.texi: Add z16 to CPU string list.
opcodes/ChangeLog:
* s390-mkopc.c (main): Enable z16 as CPU string in the opcode
table.
There isn't an actual opcodes implementation for the AMDGCN arch (yet),
this is just the bare minimum to get
$ ./configure --target=amdgcn-hsa-amdhsa --disable-gas
$ make all-binutils
working later in this series.
opcodes/ChangeLog:
* configure.ac: Handle bfd_amdgcn_arch.
* configure: Re-generate.
Change-Id: Ib7d7c5533a803ed8b2a293e9275f667ed781ce79
Correct issues with INSN2_ALIAS annotation for branch instructions:
- regular MIPS BEQZ/L and BNEZ/L assembly instructions are idioms for
BEQ/L and BNE/L respectively with the `rs' operand equal to $0,
- microMIPS 32-bit BEQZ and BNEZ assembly instructions are idioms for
BEQ and BNE respectively with the `rt' operand equal to $0,
- regular MIPS BAL assembly instruction is an idiom for architecture
levels of up to the MIPSr5 ISA and a machine instruction on its own
from the MIPSr6 ISA up.
Add missing annotation to BEQZ/L and BNEZ/L accordingly then and add a
new entry for BAL for the MIPSr6 ISA, correcting a disassembly bug:
$ mips-linux-gnu-objdump -m mips:isa64r6 -M no-aliases -d bal.o
bal.o: file format elf32-tradlittlemips
Disassembly of section .text:
00000000 <foo>:
0: 04110000 0x4110000
...
$
Add test cases accordingly.
Parts for regular MIPS BEQZ/L and BNEZ/L instructions from Sagar Patel.
2022-03-06 Maciej W. Rozycki <macro@orcam.me.uk>
binutils/
* testsuite/binutils-all/mips/mips1-branch-alias.d: New test.
* testsuite/binutils-all/mips/mips1-branch-noalias.d: New test.
* testsuite/binutils-all/mips/mips2-branch-alias.d: New test.
* testsuite/binutils-all/mips/mips2-branch-noalias.d: New test.
* testsuite/binutils-all/mips/mips32r6-branch-alias.d: New test.
* testsuite/binutils-all/mips/mips32r6-branch-noalias.d: New
test.
* testsuite/binutils-all/mips/micromips-branch-alias.d: New
test.
* testsuite/binutils-all/mips/micromips-branch-noalias.d: New
test.
* testsuite/binutils-all/mips/mips-branch-alias.s: New test
source.
* testsuite/binutils-all/mips/micromips-branch-alias.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
2022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
Maciej W. Rozycki <macro@orcam.me.uk>
opcodes/
* mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
* micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
"bnez" instructions.
The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
In preparation for the next commit, which will add GDB support for
RISC-V disassembler options, this commit restructures how the
disassembler options are managed within libopcodes.
The implementation provided here is based on this mailing list patch
which was never committed:
https://sourceware.org/pipermail/binutils/2021-January/114944.html
which in turn took inspiration from the MIPS implementation of the
same feature.
The biggest changes from the original mailing list post are:
1. The GDB changes have been split into a separate patch, and
2. The `riscv_option_args_privspec` variable, which held the valid
priv-spec values is now gone, instead we use the `riscv_priv_specs`
array from bfd/cpu-riscv.c instead.
Co-authored-by: Simon Cook <simon.cook@embecosm.com>
include/ChangeLog:
* dis-asm.h (disassembler_options_riscv): Declare.
opcodes/ChangeLog:
* riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
(riscv_options): New static global.
(disassembler_options_riscv): New function.
(print_riscv_disassembler_options): Rewrite to use
disassembler_options_riscv.
If built as a shared library, libopcodes has a load-time dependency on
libbfd, which is recorded in the dynamic section, however without a
corresponding RPATH entry for the directory to find libbfd in. This
causes loading to fail whenever libbfd is only pulled by libopcodes
indirectly and libbfd has been installed in a directory that is not in
the dynamic loader's search path.
It does not happen with the programs included with binutils or GDB,
because they all also pull libbfd when using libopcodes, but it can
happen with external software, e.g.:
$ gdbserver --help
gdbserver: error while loading shared libraries: libbfd-[...].so: cannot open shared object file: No such file or directory
$
(not our `gdbserver').
Indirect dynamic dependencies are handled by libtool automatically by
adding RPATH entries as required, however our setup for libopcodes
prevents this from happening by linking in libbfd with an explicit file
reference sneaked through to the linker directly behind libtool's back
via the `-Wl' linker command-line option rather than via `-l' combined
with a suitable library search path specified via `-L', as it would be
usually the case, or just referring to the relevant .la file in a fully
libtool-enabled configuration such as ours.
According to an observation in the discussion back in 2007[1][2][3] that
has led to the current arrangement it is to prevent libtool from picking
up the wrong version of libbfd. It does not appear to be needed though,
not at least with our current libtool incarnation, as directly referring
`libbfd.la' does exactly what it should, as previously suggested[4], and
with no link-time reference to the installation directory other than to
set RPATH. Uninstalled version of libopcodes has libbfd's build-time
location prepended to RPATH too, as also expected.
Use a direct reference to `libbfd.la' then, making the load error quoted
above go away. Alternatively `-L' and `-l' could be used to the same
effect, but it seems an unnecessary complication and just another way to
circumvent rather than making use of libtool.
References:
[1] "compile failure due to undefined symbol",
<https://sourceware.org/ml/binutils/2007-08/msg00476.html>
[2] same, <https://sourceware.org/ml/binutils/2007-09/msg00000.html>
[3] same, <https://sourceware.org/ml/binutils/2007-10/msg00019.html>
[4] same, <https://sourceware.org/ml/binutils/2007-10/msg00034.html>
opcodes/
* Makefile.am: Remove obsolete comment.
* configure.ac: Refer `libbfd.la' to link shared BFD library
except for Cygwin.
* Makefile.in: Regenerate.
* configure: Regenerate.
SPR 896 and the mfppr mfppr32, mtppr and mtppr32 extended mnemonics were added
in ISA 2.03, so enable them on POWER5 and later.
opcodes/
* ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
on POWER5 and later.
gas/
* testsuite/gas/ppc/power5.s: New test.
* testsuite/gas/ppc/power5.d: Likewise.
* testsuite/gas/ppc/ppc.exp: Run it.
* testsuite/gas/ppc/power7.s: Remove tests for mfppr, mfppr32, mtppr
and mtppr32.
* testsuite/gas/ppc/power7.d: Likewise.
