Commit Graph

425 Commits

Author SHA1 Message Date
Ian Lance Taylor
b56c3d6cee * mips-dis.c (_print_insn_mips): Don't print a trailing tab if
there are no operand types.
1996-10-29 21:31:22 +00:00
Jeff Law
244558e354 * v850-opc.c (D9_RELAX): Renamed from D9, all references
changed.
        (v850_operands): Make sure D22 immediately follows D9_RELAX.
1996-10-29 19:25:35 +00:00
Jeff Law
0f02ae6e5a * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for
"bCC"instructions).
Because quantum's code uses jnz, jcc, etc etc etc.
1996-10-24 23:55:11 +00:00
Ian Lance Taylor
4f6d7c2c30 * mips-dis.c (_print_insn_mips): Use a tab between the instruction
and the arguments.
1996-10-24 21:21:37 +00:00
Ian Lance Taylor
de145351e8 * ppc-opc.c (PPCPWR2): Define.
(powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating
	it.
1996-10-23 03:34:07 +00:00
Jeff Law
63dc694d29 * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode
field for movhu instruction.
Bug found by gas testsuite.

        * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands,
        cast value to "long" not "signed long" to keep hpux10
        compiler quiet.
Found in an attempt to build the v850 on hpux10 with the HP
compiler.
1996-10-11 22:06:47 +00:00
Jeff Law
02d4ad193b * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field
for mov (abs16),DN.
Bug found by gas testsuite.  Matsushita.
1996-10-10 21:42:01 +00:00
Jeff Law
ba8ed10c7e * mn10300-opc.c (FMT*): Remove definitions.
Moved into opcode/mn10300.h
1996-10-10 20:31:06 +00:00
Jeff Law
1e5ddd3be4 * mn10300-opc.c (mn10300_opcodes): Fix destination register
for shift-by-register opcodes.
Bug found by testsuite.
1996-10-10 19:08:46 +00:00
Jeff Law
36b34aa4a9 * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM
into [AD][MN][01] for encoding the position of the register
        in the opcode.
Matsushita.
1996-10-10 16:28:14 +00:00
Jeff Law
344d6417bb * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
Matsushita.
1996-10-09 17:20:59 +00:00
Jeff Law
db22905430 * mn10300-opc.c (mn10300_operands): Remove "REGS" operand.
Fix various typos.  Add "PAREN" operand.
        (MEM, MEM2): Define.
        (mn10300_opcodes): Surround all memory addresses with "PAREN"
        operands.  Fix several typos.
Should parse all opcodes in the instruction specification, except the
"user extension instructions".
1996-10-08 21:09:57 +00:00
Jeff Law
06b796584d * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's
changes.
Matsushita.
1996-10-08 17:56:40 +00:00
Jeff Law
5ab7bce62d * mn10300-opc.c (FMT_XX): Renumber starting at one.
(mn10300_operands): Rough cut.  Enough to parse "mov" instructions
        at this time.
        (mn10300_opcodes): Break opcode format out into its own field.
        Update many operand fields to deal with signed vs unsigned
        issues.  Fix one or two typos in the "mov" instruction
        opcode, mask and/or operand fields.
Checkpointing today's work.  Matsushita.
1996-10-07 22:52:18 +00:00
Ian Lance Taylor
6ba7ecd4eb Mon Oct 7 11:39:49 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* m68k-opc.c (plusha): Prefer encoding for m68040up, in case
	m68851 wasn't reset.
1996-10-07 15:41:56 +00:00
Jeff Law
99777c0bfb * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for
all opcodes.  Very rough cut at operands for all opcodes.
Matsushita.
1996-10-04 22:02:43 +00:00
Jeff Law
cd8a9026b9 * mn10300-opc.c (mn10300_opcodes): Start fleshing out the
opcode table.
Checkpointint 10300 work.
1996-10-04 19:20:19 +00:00
Ian Lance Taylor
6c9370db2a * Makefile.in (ALL_MACHINES): Add mn10200-dis.o, mn10200-opc.o,
mn10300-dis.o, and mn10300-opc.o.
Also add d10v and v850 files, with appropriate sanitization.
1996-10-03 21:17:46 +00:00
Jeff Law
ae1b99e42d Grrr. The mn10200 and mn10300 are _not_ similar enough to easily support
with a single generic configuration.  So break them up into two different
configurations.  See the individual ChangeLogs for additional detail.
1996-10-03 16:42:22 +00:00
Jason Molenda
42b4add910 * Makefile.in (MOSTLYCLEAN): Move config.log to distclean. 1996-10-03 06:58:15 +00:00
Jeff Law
e7c50ceffd * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita
MN10x00 processors.
        * disassemble (ARCH_mn10x00): Define.
        (disassembler): Handle bfd_arch_mn10x00.
        * configure.in: Recognize bfd_mn10x00_arch.
        * configure: Rebuilt.
Continue stubbing out for Matsushita work.
1996-10-03 05:31:01 +00:00
Jeff Law
072b27ea5e Add missing copyright. 1996-10-03 04:48:16 +00:00
Ian Lance Taylor
a5cb84dd6f * i386-dis.c (op_rtn): Change to be a pointer. Adjust uses
accordingly.  Don't declare functions using op_rtn.
Remove ANSI C constructs.
1996-10-01 14:50:19 +00:00
Ian Lance Taylor
800bda836e * mips-opc.c: Add a case for "div" and "divu" with two registers
and a destination of $0.
PR 10654.
1996-09-17 16:07:41 +00:00
Fred Fish
d7deed257c * mips-dis.c (print_insn_arg): Add prototype.
(_print_insn_mips): Ditto.
1996-09-11 04:26:58 +00:00
Ian Lance Taylor
30b1724cc8 * mips-dis.c (print_insn_arg): Print condition code registers as
$fccN.
1996-09-09 18:27:10 +00:00
Jeff Law
eb5c28e173 * v850-dis.c (disassemble): Make static. Provide prototype. 1996-09-03 18:05:25 +00:00
Ian Lance Taylor
44789bee66 whoops--typo 1996-09-02 16:41:29 +00:00
Ian Lance Taylor
01d34e4be3 file was really removed a long time ago 1996-09-02 16:41:28 +00:00
Jeff Law
09478dc331 * v850-dis.c (disassemble): Handle insertion of ',', '[' and
']' characters into the output stream.
        * v850-opc.c (v850_opcodes: Remove size field from all opcodes.
        Add "memop" field to all opcodes (for the disassembler).
        Reorder opcodes so that "nop" comes before "mov" and "jr"
        comes before "jarl".
Should give us a functional disassembler.
1996-08-31 22:00:45 +00:00
Jeff Law
e05cae190b * v850-dis.c (print_insn_v850): Properly handle disassembling
a two byte insn at the end of a memory region when the memory
        region's size is only two byte aligned.
1996-08-31 21:21:27 +00:00
Jeff Law
a5f2a4e50e * v850-dis.c (v850_cc_names): Fix stupid thinkos. 1996-08-31 21:10:43 +00:00
Jeff Law
502535cff7 * v850-dis.c (v850_reg_names): Define.
(v850_sreg_names, v850_cc_names): Likewise.
        (disassemble): Very rough cut at printing operands (unformatted).
One step at a time.

        * v850-opc.c (BOP_MASK): Fix.
        (v850_opcodes): Fix mask for jarl and jr.
Bugs exposed by disassembler testing.
1996-08-31 20:56:05 +00:00
Jeff Law
529418ddc4 * v850-dis.c: New file. Skeleton for disassembler support.
* Makefile.in Remove v850 references, they're not needed here
        and they weren't being sanitized away.
        * configure.in: Add v850-dis.o when building v850 toolchains.
        * configure: Rebuilt.
        * disassemble.c (disassembler): Call v850 disassembler.
1996-08-31 19:22:11 +00:00
Jeff Law
ba39d3dde1 * v850-dis.c: New file. Skeleton for disassembler support.
* Makefile.in Remove v850 references, they're not needed here
        and they weren't being sanitized away.
        * configure.in: Add v850-dis.o when building v850 toolchains.
        * configure: Rebuilt.
        * disassemble.c (disassembler): Call v850 disassembler.
Skeleton support for V850 disassembler.
1996-08-31 19:20:28 +00:00
Jeff Law
b219416478 * v850-opc.c (insert_d8_7, extract_d8_7): New functions.
(insert_d8_6, extract_d8_6): New functions.
        (v850_operands): Rename D7S to D7; operand for D7 is unsigned.
        Rename D8 to D8_7, use {insert,extract}_d8_7 routines.
        Add D8_6.
        (IF4A, IF4B): Use "D7" instead of "D7S".
        (IF4C, IF4D): Use "D8_7" instead of "D8".
        (IF4E, IF4F): New.  Use "D8_6".
        (v850_opcodes): Use IF4A/IF4B for sld.b/sst.b.  Use IF4C/IF4D for
        sld.h/sst.h.  Use IF4E/IF4F for sld.w/sst.w.
So we can assemble sst/sld instructions correctly.
1996-08-31 18:23:02 +00:00
Jeff Law
c6b9c13532 * v850-opc.c (insert_d16_15, extract_d16_15): New functions.
(v850_operands): Change D16 to D16_15, use special insert/extract
        routines.  New new D16 that uses the generic insert/extract code.
        (IF7A, IF7B): Use D16_15.
        (IF7C, IF7D): New.  Use D16.
        (v850_opcodes): Use IF7C and IF7D for ld.b and st.b.
1996-08-31 17:43:28 +00:00
Jeff Law
fb8c25a3e4 * v850-opc.c (insert_d9, insert_d22): Slightly improve error
message.  Issue an error if the branch offset is odd.
1996-08-31 17:23:49 +00:00
Jeff Law
69ae4b82dc * v850-opc.c: Add notes about needing special insert/extract
for all the load/store insns, except "ld.b" and "st.b".
So we don't forget!
1996-08-31 07:32:01 +00:00
Jeff Law
574b9cb3d3 * v850-opc.c (insert_d22, extract_d22): New functions.
(v850_operands): Use insert_d22 and extract_d22 for
        D22 operands.
        (insert_d9): Fix range check.
1996-08-31 07:28:22 +00:00
J.T. Conklin
d44b697b78 * v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flag
and set bits field to D9 and D22 operands.
1996-08-31 01:04:39 +00:00
Jeff Law
e9ebb36451 * v850-opc.c (v850_operands): Define SR2 operand.
(v850_opcodes): "ldsr" uses R1,SR2.
ldsr is kinda weird.
1996-08-30 19:44:42 +00:00
Jeff Law
e7f3e5fbbf * v850-opc.c (v850_opcodes): Fix opcode specs for
sld.w, sst.b, sst.h, sst.w, and nop.
1996-08-29 17:11:13 +00:00
Jeff Law
e7dd77751d * v850-opc.c (v850_opcodes): Add null opcode to mark the
end of the opcode table.
For the simulator
1996-08-28 21:56:03 +00:00
J.T. Conklin
c6d5c52650 Remove v850-opc.c from things-to-keep 1996-08-26 17:36:45 +00:00
Jeff Law
d3edb57f12 * v850-opc.c (v850_operands): Define EP operand.
(IF4A, IF4B, IF4C, IF4D): Use EP.
1996-08-23 20:55:15 +00:00
Jeff Law
18c97701b4 * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov"
with immediate operand, "movhi".  Tweak "ldsr".
More fixes.
1996-08-23 20:27:25 +00:00
Jeff Law
fb6da8680e * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw]
correct.  Get sld.[bhw] and sst.[bhw] closer.
1996-08-23 19:32:41 +00:00
Jeff Law
38c7a4504d * v850-opc.c (v850_operands): "not" is a two byte insn. 1996-08-23 19:12:05 +00:00
Jeff Law
6c1fc4d3fa * v850-opc.c (v850_opcodes): Correct bit pattern for setf. 1996-08-23 18:58:57 +00:00