binutils* dwarf.c (do_checks): New global variable.
(display_formatted_table): Warn about an unexpected number of
columns in the table, if checks are enabled. Do not complain
about the lack of data following the number of entries in the
table if the table is empty.
(display_debug_lines_decoded): Only warn about an unexpected
number of columns in a table if checks are enabled.
* dwarf.h (do_checks): Add a prototype.
* elfcomm.c (error): Remove weak attribute.
(warn): Likewise.
* readelf.c (do_checks): Delete.
(warn): Delete.
(process_section_headers): Only warn about empty sections if
checks are enabled.
gas * dwarf2dbg.c (out_dir_and_file_list): Add comments describing the
construction of a DWARF-5 directory name table.
* testsuite/gas/elf/pr25917.d: Update expected output.
PR 25917
* dwarf.c (display_debug_lines_decoded): Warn if encountering a
supicious number of entries for DWARF-5 format directory and file
name tables. Do not display file name table header if the table
is empty. Do not allocate space for empty tables.
This fixes PR 25863 by fixing the condition in the parsing of vmul in
do_mve_vmull. It also simplifies the code in there fixing latent issues that
would lead to NEON code being accepted when it shouldn't.
gas/ChangeLog:
2020-05-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR gas/25863
* config/tc-arm.c (do_mve_vmull): Fix scalar and NEON parsing of vmul.
* testsuite/gas/arm/mve-scalar-vmult-it.d: New test.
* testsuite/gas/arm/mve-scalar-vmult-it.s: New test.
PR 25917
* dwarf2dbg.c (out_dir_and_file_list): Check for the directory
table's existence before looking at its entries.
* testsuite/gas/elf/pr25917.s: New test source file.
* testsuite/gas/elf/pr25917.d: New test driver.
* testsuite/gas/elf/elf.exp (run_elf_list_test): Run the new test.
Starting with RH.0 release Xtensa ISA adds immediate parameter to
simcall opcode. For assembly source compatibility treat "simcall"
instruction without parameter as "simcall 0" when parameter is required.
2020-04-29 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (XTENSA_MARCH_EARLIEST): Define macro as 0
if it's not defined.
(microarch_earliest): New static variable.
(xg_translate_idioms): Translate "simcall" to "simcall 0" when
simcall opcode has mandatory parameter.
(xg_init_global_config): Initialize microarch_earliest.
PR 22699
opcodes * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
* sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
IMM0_8U case.
gas * config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to
IMM0_8S and add support for IMM0_8U.
* testsuite/gas/sh/sh4a.s: Add test of a logical insn using an
unsigned 8-bit immediate.
* testsuite/gas/sh/sh4a.d: Extended expected disassembly.
The 64-bit version of binutils got support for the PE COFF BIG OBJ format a
couple of years ago. The BIG OBJ format is a slightly different COFF format
which extends the size of the number of section field in the header from a
uint16_t to a uint32_t and so greatly increases the number of sections allowed.
However the 32-bit version of bfd never got support for this. The GHC Haskell
compiler generates a great deal of symbols due to it's use of
-ffunction-sections and -fdata-sections.
This meant that we could not build the 32-bit version of the GHC Compiler for
many releases now as binutils didn't have this support.
This patch adds the support to the 32-bit port of binutils as well and also does
come cleanup in the code.
bfd/ChangeLog:
* coff-i386.c (COFF_WITH_PE_BIGOBJ): New.
* coff-x86_64.c (COFF_WITH_PE_BIGOBJ): New.
* config.bfd (targ_selvecs): Rename x86_64_pe_be_vec
to x86_64_pe_big_vec as it not a big-endian format.
(vec i386_pe_big_vec): New.
* configure.ac: Likewise.
* targets.c: Likewise.
* configure: Regenerate.
* pe-i386.c (TARGET_SYM_BIG, TARGET_NAME_BIG,
COFF_WITH_PE_BIGOBJ): New.
* pe-x86_64.c (TARGET_SYM_BIG, TARGET_NAME_BIG):
New.
(x86_64_pe_be_vec): Moved.
gas/ChangeLog:
* NEWS: Add news entry for big-obj.
* config/tc-i386.c (i386_target_format): Support new format.
* doc/c-i386.texi: Add i386 support.
* testsuite/gas/pe/big-obj.d: Rename test to not be x64 specific.
* testsuite/gas/pe/pe.exp (big-obj): Make test run on i386 as well.
ld/ChangeLog:
* pe-dll.c (pe_detail_list): Add pe-bigobj-i386.
PR 25878
* dwarf2dbg.c (struct file_entry): Add auto_assigned field.
(assign_file_to_slot): New function. Fills in an entry in the
files table.
(allocate_filenum): Use new function.
(allocate_filename_to_slot): Use new function. If the specified
slot entry is already in use, but was chosen automatically then
reassign the automatic entry.
Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences
(subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32}
for negative differences (subtracted symbol follows diminished symbol).
Don't generate XTENSA_DIFF relocations in the assembler, generate
XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position.
Handle XTENSA_DIFF in BFD for compatibility with old object files.
Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value
as unsigned.
2020-04-22 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* bfd-in2.h: Regenerated.
* elf32-xtensa.c (elf_howto_table): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
(elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc)
(relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and
R_XTENSA_NDIFF{8,16,32}.
* libbfd.h (bfd_reloc_code_real_names): Add names for
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
* reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32}
and BFD_RELOC_XTENSA_NDIFF{8,16,32}.
binutils/
* readelf.c (is_none_reloc): Recognize
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
gas/
* config/tc-xtensa.c (md_apply_fix): Replace
BFD_RELOC_XTENSA_DIFF{8,16,32} generation with
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32} generation.
* testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16
with BFD_RELOC_XTENSA_PDIFF16 in the expected output.
include/
* elf/xtensa.h (elf_xtensa_reloc_type): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
ld/
* testsuite/ld-xtensa/relax-loc.d: New test definition.
* testsuite/ld-xtensa/relax-loc.s: New test source.
* testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
* config/obj-elf.c (elf_frob_symbol): Unconditionally remove
symbol for ".symver .. remove".
* doc/as.texi (.symver): Update.
* testsuite/gas/symver/symver11.s: Make foo weak.
* testsuite/gas/symver/symver11.d: Expect an error.
* testsuite/gas/symver/symver7.d: Allow other random symbols.
The MC68000/10 decodes the second operand of CMPI strictly as destination
operand, which disallows PC relative addressing, even though the insn
doesn't write to the operand. This restriction has only been lifted for
the MC68020+ and CPU32.
opcodes:
PR 25848
* m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
cmpi only on m68020up and cpu32.
gas:
PR 25848
* testsuite/gas/m68k/operands.s: Add tests for cmpi.
* testsuite/gas/m68k/operands.d: Update.
* testsuite/gas/m68k/op68000.d: Update for new error messages.
The check in bfd_get_full_section_contents is trying to check that we don't
allocate more space for a section than the size of the section is on disk.
Previously we excluded linker created sections since they didn't have a size on
disk. However we also need to exclude sections with no content as well such as
the BSS section. Space for these would not have been allocated by the assembler
and so the check would incorrectly fail.
bfd/ChangeLog:
PR binutils/24753
* compress.c (bfd_get_full_section_contents): Exclude sections with no
content.
gas/ChangeLog:
PR binutils/24753
* testsuite/gas/arm/pr24753.d: New test.
* testsuite/gas/arm/pr24753.s: New test.
Extend .symver directive to update visibility of the original symbol and
assign one original symbol to different versioned symbols:
.symver foo, foo@VERS_1, local # Change foo to a local symbol.
.symver foo, foo@VERS_2, hidden # Change foo to a hidden symbol.
.symver foo, foo@@VERS_3, remove # Remove foo from symbol table.
.symver foo, bar@V1 # Assign foo to bar@V1 and baz@V2.
.symver foo, baz@V2
PR gas/23840
PR gas/25295
* NEWS: Mention .symver extension.
* config/obj-elf.c (obj_elf_find_and_add_versioned_name): New
function.
(obj_elf_symver): Call obj_elf_find_and_add_versioned_name to
add a version name. Add local, hidden and remove visibility
support.
(elf_frob_symbol): Handle the list of version names. Update the
original symbol to local, hidden or remove it from the symbol
table.
(elf_frob_file_before_adjust): Handle the list of version names.
* config/obj-elf.h (elf_visibility): New.
(elf_versioned_name_list): Likewise.
(elf_obj_sy): Change local to bitfield. Add rename, bad_version
and visibility. Change versioned_name pointer to struct
elf_versioned_name_list.
* doc/as.texi: Update .symver directive.
* testsuite/gas/symver/symver.exp: Run all *.d tests. Add more
error checking tests.
* testsuite/gas/symver/symver6.d: New file.
* testsuite/gas/symver/symver7.d: Likewise.
* testsuite/gas/symver/symver7.s: Likewise.
* testsuite/gas/symver/symver8.d: Likewise.
* testsuite/gas/symver/symver8.s: Likewise.
* testsuite/gas/symver/symver9.s: Likewise.
* testsuite/gas/symver/symver9a.d: Likewise.
* testsuite/gas/symver/symver9b.d: Likewise.
* testsuite/gas/symver/symver10.s: Likewise.
* testsuite/gas/symver/symver10a.d: Likewise.
* testsuite/gas/symver/symver10b.d: Likewise.
* testsuite/gas/symver/symver11.d: Likewise.
* testsuite/gas/symver/symver11.s: Likewise.
* testsuite/gas/symver/symver12.d: Likewise.
* testsuite/gas/symver/symver12.s: Likewise.
* testsuite/gas/symver/symver13.d: Likewise.
* testsuite/gas/symver/symver13.s: Likewise.
* testsuite/gas/symver/symver14.d: Likewise.
* testsuite/gas/symver/symver14.l: Likewise.
* testsuite/gas/symver/symver15.d: Likewise.
* testsuite/gas/symver/symver15.l: Likewise.
* testsuite/gas/symver/symver6.l: Removed.
* testsuite/gas/symver/symver6.s: Updated.
This patch implements the TSB instructions:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
tsb-csync-trace-synchronization-barrier
Since TSB and PSB both use the same (and only) argument "CSYNC", this patch
reuses it for TSB. However, the same argument would imply different value
for CRm:Op2 which are anyway fixed values, so I have diverted the
inserter/extracter function to dummy versions instead of the "hint" version.
The operand checker part still uses the existing infratructure for
AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly.
gas/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_barrier_psb): Update error messages
to include TSB.
* testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests.
* testsuite/gas/aarch64/system-2.s: Add new tsb tests.
* testsuite/gas/aarch64/system.d: Update.
opcodes/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm.c (aarch64_ins_none): New.
* aarch64-asm.h (ins_none): New declaration.
* aarch64-dis.c (aarch64_ext_none): New.
* aarch64-dis.h (ext_none): New declaration.
* aarch64-opc.c (aarch64_print_operand): Update case for
AARCH64_OPND_BARRIER_PSB.
* aarch64-tbl.h (aarch64_opcode_table): Add tsb.
(AARCH64_OPERANDS): Update inserter/extracter for
AARCH64_OPND_BARRIER_PSB to use new dummy functions.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
There are a few instruction in AArch64 that are in the HINT space. Any of
these instructions should be accepted by the assembler/disassembler at any
architecture version. This patch fixes the existing instructions that are
not behaving accordingly.
I have used all of the instructions mentioned in the following to make the
changes:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
hint-hint-instruction
gas/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/bti.d: Update -march option.
* testsuite/gas/aarch64/illegal-bti.d: Remove.
* testsuite/gas/aarch64/illegal-bti.l: Remove.
* testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
* testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.
opcodes/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
(aarch64_feature_ras, RAS): Likewise.
(aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
(aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
autiaz, autiasp, autibz, autibsp to be CORE_INSN.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
BFIN has lots of instructions that contain "=", so "sym = expression"
is disabled for that target. This makes an exception for assignment
to dot, fixing the recent regression of ld-scripts/pr18963.
* config/tc-bfin.h (TC_EQUAL_IN_INSN): Allow assignment to dot.
PR 25803
gas * config/obj-elf.c (obj_elf_type): Reject ifunc symbols on MIPS
targets.
* testsuite/gas/elf/elf.exp: Add MIPS targets to the list to skip
for the type-2 test.
* testsuite/gas/elf/type-noifunc.e: Update to allow for MIPS
targets running this test.
bfd * elfxx-mips.c (_bfd_mips_elf_adjust_dynamic_symbol): Replace an
abort with a more helpful error message.
Add support for the JMP32 class of eBPF instructions.
cpu/ChangeLog
* bpf.cpu (define-cond-jump-insn): Renamed from djci.
(dcji) New version with support for JMP32
gas/ChangeLog
* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
* testsuite/gas/bpf/jump32.s: New file.
* testsuite/gas/bpf/jump32.d: Likewise.
opcodes/ChangeLog
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Regenerate.
* bpf-opc.h: Likewise.
The m32c target header has a duplicate entry for MD_PCREL_FROM_SECTION.
The duplication was present since the initial commit of the port.
* config/tc-m32c.h (MD_PCREL_FROM_SECTION): Delete duplicate define.
(md_pcrel_from_section): Remove duplicate prototype.
The moxie target header uses md_pcrel_from, thus the local prototype and
the macro definition for MD_PCREL_FROM_SECTION are not needed.
* config/tc-moxie.h (MD_PCREL_FROM_SECTION): Delete define.
(md_pcrel_from): Remove prototytpe.
Fix
gas/doc/c-z80.texi:244: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:278: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:284: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:291: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:295: warning: `.' or `,' must follow @xref, not )
* doc/c-z80.texi: Fix @xref warnings.
A couple of ld ifunc tests currently FAIL on 64-bit Solaris/x86:
FAIL: ld-ifunc/ifunc-10-x86-64
FAIL: ld-ifunc/ifunc-11-x86-64
FAIL: ld-ifunc/ifunc-12-x86-64
FAIL: ld-ifunc/ifunc-13-x86-64
FAIL: ld-ifunc/ifunc-14a-x86-64
FAIL: ld-ifunc/ifunc-14b-x86-64
FAIL: ld-ifunc/ifunc-14c-x86-64
FAIL: ld-ifunc/ifunc-14d-x86-64
FAIL: ld-ifunc/ifunc-14e-x86-64
FAIL: ld-ifunc/ifunc-14f-x86-64
FAIL: ld-ifunc/ifunc-15-x86-64
FAIL: ld-ifunc/ifunc-17a-x86-64
FAIL: ld-ifunc/ifunc-17b-x86-64
FAIL: ld-ifunc/ifunc-2-local-x86-64-now
FAIL: ld-ifunc/ifunc-2-local-x86-64
FAIL: ld-ifunc/ifunc-2-x86-64-now
FAIL: ld-ifunc/ifunc-2-x86-64
FAIL: ld-ifunc/ifunc-20-x86-64
FAIL: ld-ifunc/pr17154-x86-64-now
FAIL: ld-ifunc/pr17154-x86-64
For one, the actual error is weird:
./ld-new: target elf64-x86-64 not found
failed with: <./ld-new: target elf64-x86-64 not found>, no expected output
FAIL: ld-ifunc/ifunc-10-x86-64
although ld -V does report the elf_x86_64 emulation as supported:
$ ./ld/ld-new -V
GNU ld (GNU Binutils) 2.34.50.20200328
Supported emulations:
elf_x86_64_sol2
elf_x86_64
[...]
When using ld -m elf_x86_64_sol2 instead, one of the testcases links
successfully.
However, there's no point in pursuing this: Solaris does not support
ifunc, as can be seen in <sys/elf.h>:
/*
* GNU/Linux specific symbol type not used by Solaris
*/
#define STT_GNU_IFUNC 10
and never will, given that it has symbol capabilities as solution to
effectively the same problem:
http://www.linker-aliens.org/blogs/rie/entry/symbol_capabilitie/
Therefore this patch disables ifunc testing on Solaris completely by
removing Solaris from binutils/testsuite/lib/binutils-common.exp
(supports_gnu_osabi). The ifunc part is justified above. SHF_GNU_MBIND is
in the OS-specific range and conflicts with
#define SHF_SUNW_REALLOC 0x01000000 /* internal: krtld realloc */
While the comment suggests this might be relocatable without too much
problems, the description of mbind (no formal spec AFAICS, just the
comment in the binutils patch submission) strongly suggests that this
isn't relevant to Solaris at all.
Indirectly, clearing supports_gnu_osabi on Solaris disables
supports_gnu_unique. Again, Solaris <sys/elf.h> has
/*
* GNU/Linux specific binding not used by Solaris
*/
#define STB_GNU_UNIQUE 10
so this seems the right thing to do.
Afterwards, one can remove the explicit mentions of *-*-solaris2* in
quite a number of (but not all) the ld-ifunc dump file notarget lists.
There's one fallout, though: two gas tests now XPASS because they are
xfail'ed for !supports_gnu_osabi:
XPASS: mbind sections 12
XPASS: mbind section contents 16
XPASS: mbind sections 16
XPASS: mbind section contents 16
To fix that, I've changed
#xfail: ![supports_gnu_osabi]
to notarget.
Tested on x86_64-pc-solaris2.11, i386-pc-solaris2.11,
x86_64-pc-linux-gnu, and i686-pc-linux-gnu.
ld:
* testsuite/ld-ifunc/ifunc-10-i386.d: Remove *-*-solaris2* from
notarget.
* ifunc-11-i386.d: Likewise.
* ifunc-12-i386.d: Likewise.
* ifunc-13-i386.d: Likewise.
* ifunc-14a-i386.d: Likewise.
* ifunc-14b-i386.d: Likewise.
* ifunc-14c-i386.d: Likewise.
* ifunc-14d-i386.d: Likewise.
* ifunc-14e-i386.d: Likewise.
* ifunc-14f-i386.d: Likewise.
* ifunc-15-i386.d: Likewise.
* ifunc-16-i386-now.d: Likewise.
* ifunc-16-i386.d: Likewise.
* ifunc-17a-i386.d: Likewise.
* ifunc-17b-i386.d: Likewise.
* ifunc-18a-i386.d: Likewise.
* ifunc-18b-i386.d: Likewise.
* ifunc-19a-i386.d: Likewise.
* ifunc-19b-i386.d: Likewise.
* ifunc-2-i386-now.d: Likewise.
* ifunc-2-i386.d: Likewise.
* ifunc-2-local-i386-now.d: Likewise.
* ifunc-2-local-i386.d: Likewise.
* ifunc-20-i386.d: Likewise.
* ifunc-21-i386.d: Likewise.
* ifunc-22-i386.d: Likewise.
* ifunc-5a-i386.d: Likewise.
* ifunc-5a-local-i386.d: Likewise.
* ifunc-5b-i386.d: Likewise.
* ifunc-5b-local-i386.d: Likewise.
* ifunc-5r-local-i386.d: Likewise.
* ifunc-6a-i386.d: Likewise.
* ifunc-6b-i386.d: Likewise.
* ifunc-7a-i386.d: Likewise.
* ifunc-7b-i386.d: Likewise.
* ifunc-8-i386.d: Likewise.
* ifunc-9-i386.d: Likewise.
* pr17154-i386-now.d: Likewise.
* pr17154-i386.d: Likewise.
* ifunc-23a-x86.d: Remove notarget.
* ifunc-24a-x86.d: Likewise.
* ifunc-25a-x86.d: Likewise.
gas:
* testsuite/gas/elf/section12a.d: Use notarget instead of xfail.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section16a.d: Likewise.
* testsuite/gas/elf/section16b.d: Likewise.
binutils:
* testsuite/lib/binutils-common.exp (supports_gnu_osabi): Don't
enable on *-*-solaris*.
Define TC_FORCE_RELOCATION_ABS to force relocation against local
absolute symbol.
PR gas/25756
* config/tc-i386.h (TC_FORCE_RELOCATION_ABS): New.
* testsuite/gas/i386/localpic.s: Add a test for relocation
against local absolute symbol.
* testsuite/gas/i386/x86-64-localpic.s: Likewise.
* testsuite/gas/i386/localpic.d: Updated.
* testsuite/gas/i386/x86-64-localpic.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
As reported in PR gas/25732, some testcases currently FAIL on
Solaris/x86:
FAIL: x86-64 branch 2
FAIL: x86-64 branch 3
FAIL: x86-64 MPX branch
FAIL: x86-64 branch with BND prefix
FAIL: x86-64 jump
Since https://sourceware.org/ml/binutils/2019-03/msg00163.html, gas
doesn't emit R_X86_64_PLT32 as branch marker on Solaris. Since the
testsuite lacks a way to preprocess dump files, adjusted copies of the
affected dumps are now used on Solaris. Unfortunately, those dumps
weren't adapted when the original testcases were changed or other
testcases started to differ between non-Solaris and Solaris targets.
The following patch fixes that, re-syncing the affected dump files or
creating new Solaris-specific ones.
Tested on i386-pc-solaris2.11, x86_64-pc-solaris2.11,
x86_64-pc-linux-gnu, and i686-pc-linux-gnu.
PR gas/25732
* testsuite/gas/i386/solaris/x86-64-branch-2.d: New file.
* testsuite/gas/i386/solaris/x86-64-branch-3.d: New file.
* testsuite/gas/i386/solaris/x86-64-jump.d: Incorporate changes to
testsuite/gas/i386/x86-64-jump.d.
* gas/testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d:
Incorporate changes to
gas/testsuite/gas/i386/x86-64-mpx-branch-1.d.
* testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d : Incorporate
changes to testsuite/gas/i386/x86-64-mpx-branch-2.d.
* testsuite/gas/i386/x86-64-branch-2.d: Skip on *-*-solaris*.
* testsuite/gas/i386/x86-64-branch-3.d: Likewise.
Correct an issue with commit 5496f3c635 ("Add support for generating
DWARF-5 format directory and file name tables from the assembler.") and
remove a duplicate direct inclusion of "bignum.h" from dwarf2dbg.c that
causes a GAS compilation error:
In file included from .../gas/dwarf2dbg.c:33:
.../gas/bignum.h:42: error: redefinition of typedef 'LITTLENUM_TYPE'
.../gas/bignum.h:42: error: previous declaration of 'LITTLENUM_TYPE' was here
make[4]: *** [dwarf2dbg.o] Error 1
with some GCC versions, as this header has been already included via
"as.h" and then "flonum.h".
gas/
PR 25611
PR 25614
* dwarf2dbg.c: Do not include "bignum.h".
As explained in the PR, the addition of MVE makes the parser strip 't' and 'e'
as suffixes when MVE is enabled. This leads to vadd and vsub in it blocks with
lt and le conditions to be initially parsed as vaddl and vsubl. This means the
operand parsing for these must allow for the same operands as the scalar vadd
and vsub. I had forgotten to do this and this patch remedies that oversight.
gas/ChangeLog:
2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25660
* config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ.
(parse_operands): Handle new operand codes.
(do_neon_dyadic_long): Make shape check accept the scalar variants.
(asm_opcode_insns): Fix operand codes for vaddl and vsubl.
* testsuite/gas/arm/mve-vaddsub-it.s: New test.
* testsuite/gas/arm/mve-vaddsub-it.d: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.s: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.l: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.d: New test.
* testsuite/gas/arm/nomve-vaddsub-it.d: New test.
Add 3 command-line options to generate lfence for load, indirect near
branch and ret to help mitigate:
https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00334.htmlhttp://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-0551
1. -mlfence-after-load=[no|yes]:
-mlfence-after-load=yes generates lfence after load instructions.
2. -mlfence-before-indirect-branch=[none|all|memory|register]:
a. -mlfence-before-indirect-branch=all generates lfence before indirect
near branches via register and a warning before indirect near branches
via memory.
b. -mlfence-before-indirect-branch=memory issue a warning before
indirect near branches via memory.
c. -mlfence-before-indirect-branch=register generates lfence before
indirect near branches via register.
Note that lfence won't be generated before indirect near branches via
register with -mlfence-after-load=yes since lfence will be generated
after loading branch target register.
3. -mlfence-before-ret=[none|or|not]
a. -mlfence-before-ret=or generates or with lfence before ret.
b. -mlfence-before-ret=not generates not with lfence before ret.
A warning will be issued and lfence won't be generated before indirect
near branch and ret if the previous item is a prefix or a constant
directive, which may be used to hardcode an instruction, since there
is no clear instruction boundary.
* config/tc-i386.c (lfence_after_load): New.
(lfence_before_indirect_branch_kind): New.
(lfence_before_indirect_branch): New.
(lfence_before_ret_kind): New.
(lfence_before_ret): New.
(last_insn): New.
(load_insn_p): New.
(insert_lfence_after): New.
(insert_lfence_before): New.
(md_assemble): Call insert_lfence_before and insert_lfence_after.
Set last_insn.
(OPTION_MLFENCE_AFTER_LOAD): New.
(OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH): New.
(OPTION_MLFENCE_BEFORE_RET): New.
(md_longopts): Add -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
(md_parse_option): Handle -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
(md_show_usage): Display -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
(i386_cons_align): New.
* config/tc-i386.h (i386_cons_align): New.
(md_cons_align): New.
* doc/c-i386.texi: Document -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
PR 25611
PR 25614
* dwarf.h (DWARF2_Internal_LineInfo): Add li_address_size and
li_segment_size fields.
* dwarf.c (read_debug_line_header): Record the address size and
segment selector size values (if present) in the lineinfo
structure.
(display_formatted_table): Warn if the format count is empty but
the table itself is not empty.
Display the format count and entry count at the start of the table
dump.
(display_debug_lines_raw): Display the address size and segement
selector size fields, if present.
* testsuite/binutils-all/dw5.W: Update expected output.
gas * dwarf2dbg.c (DWARF2_FILE_TIME_NAME): Default to -1.
(DWARF2_FILE_SIZE_NAME): Default to -1.
(DWARF2_LINE_VERSION): Default to the current dwarf level or 3,
whichever is higher.
(DWARF2_LINE_MAX_OPS_PER_INSN): Provide a default value of 1.
(NUM_MD5_BYTES): Define.
(struct file entry): Add md5 field.
(get_filenum): Delete and replace with...
(get_basename): New function.
(get_directory_table_entry): New function.
(allocate_filenum): New function.
(allocate_filename_to_slot): New function.
(dwarf2_where): Use new functions.
(dwarf2_directive_filename): Add support for extended .file
pseudo-op.
(dwarf2_directive_loc): Allow the use of file number zero with
DWARF 5 or higher.
(out_file_list): Rename to...
(out_dir_and_file_list): Add DWARF 5 support.
(out_debug_line): Emit extra values into the section header for
DWARF 5.
(out_debug_str): Allow for file 0 to be used with DWARF 5.
* doc/as.texi (.file): Update the description of this pseudo-op.
* testsuite/gas/elf-dwarf-5-file0.s: Add more lines.
* testsuite/gas/elf-dwarf-5-file0.d: Update expected dump output.
* testsuite/gas/lns/lns-diag-1.l: Update expected error message.
* NEWS: Mention the new feature.
These all follow an almost common pattern, again with the exception of
being commutative, which can be easily taken care of.
Note that, as an intended side effect (and in fact one of the reason to
introduce templates), AVX long-form pseudo-ops get introduced alongside
the already existing AVX512 ones.
Fixes a fail on hppa64-hp-hpux, where anything in the first column is
a label.
* testsuite/gas/elf/dwarf-5-file0.s: Don't start directives in
first column.
PR 25614
* dwarf2dbg.c (dwarf2_directive_filename): Allow a file number of
0 if the dwarf_level is 5 or more. Complain if a filename follows
a file 0.
* testsuite/gas/elf/dwarf-5-file0.s: New test.
* testsuite/gas/elf/dwarf-5-file0.d: New test driver.
* testsuite/gas/elf/elf.exp: Run the new test.
PR 25612
* config/tc-ia64.h (DWARF2_VERISION): Fix typo.
* doc/as.texi: Fix another typo.
PR 25612
* as.c (dwarf_level): Define.
(show_usage): Add --gdwarf-3, --gdwarf-4 and --gdwarf-5.
(parse_args): Add support for the new options.
as.h (dwarf_level): Prototype.
* dwarf2dbg.c (DWARF2_VERSION): Use dwarf_level as default version
value.
* config/tc-ia64.h (DWARF2_VERISION): Update definition.
(DWARF2_LINE_VERSION): Remove definition.
* doc/as.texi: Document the new options.
Presumably as a result of various changes over the last several months,
and - for some of them - with a generalization of logic in
match_mem_size() plus mirroring of this generalization into the
broadcast handling logic of check_VecOperands(), various register-only
templates can be foled into their respective memory forms. This in
particular then also allows dropping a few more instances of IgnoreSize.
Even after commit dc2be329b9 ("i386: Only check suffix in instruction
mnemonic"), by which many of its uses have become unnecessary (some were
unnecessary even before), IgnoreSize is still used for various slightly
different purposes:
- to suppress emission of an operand size prefix,
- in Intel syntax mode to zap "derived" suffixes in certain cases and to
skip certain checks of remaining "derived" suffixes,
- to suppress ambiguous operand size / missing suffix diagnostics,
- for prefixes to suppress the "stand-alone ... prefix" warning.
Drop entirely unnecessary ones and where possible also replace instances
by the more focused (because of having just a single purpose) NoRex64.
To further restrict when IgnoreSize is needed, also generalize the logic
when to skip a template because of a present or derived L or Q suffix,
by skipping immediate operands. Additionally consider mask registers and
VecSIB there.
Note that for the time being the attribute needs to be kept in place on
MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand
template of them allows for only non-SIMD-register actuals) allowing for
Dword operands - the logic when to emit a data size prefix would need
further adjustment first.
Note also that the memory forms of {,v}pinsrw get their permission for
an L or Q suffix dropped. I can only assume that it being this way was a
cut-and-paste mistake from the register forms, as the latter
specifically have NoRex64 set, and the {,v}pextrw counterparts don't
allow these suffixes either.
Convert VexW= again to their respective VexW* on lines touched anyway.
The Q and L suffix exclusion checks in match_template() ought to be
(kept) in sync as far as their FPU and SIMD aspects go. This was
already violated by only the Q one checking for active broadcast.
Convert the code such that there'll be only one instance of the logic,
the more that subsequently the logic is liable to need further
refinement / extension. (The alternative would be to drop all SIMD-ness
from the L part, but it is in principle possible to enable all sorts of
SIMD support with just a pre-386 CPU, via suitable .arch directives.)
When the template specifies any of the possible VexW settings, we can
use this instead of a separate NoRex64 to suppress the setting of REX_W.
Note that this ends up addressing an inconsistency between VEX- and
EVEX-encoded VEXTRACTPS, VPEXTR{B,W}, and VPINSR{B,W} - while the former
avoided setting VEX.W, the latter pointlessly set EVEX.W when there is a
64-bit GPR operand. Adjust the testcase to cover both cases.
Convert VexW= to their respective VexW* on lines touched anyway.
It is almost entirely redundant with Size64, and the sole case (CRC32)
where direct replacement isn't possible can easily be taken care of in
another way.
Since 16-bit addressing isn't allowed, Disp32 needs to be forced; Disp16
fails to match the templates.
The SDM leaves open whether BNDC[LNU] with a GPR operand require an
operand size override; this aspect is therefore left untouched here.
For proper code generation in 16-bit mode (or to avoid the "same type of
prefix used twice" diagnostic there), IgnoreSize is needed on certain
templates allowing for just 32-(and maybe 64-)bit operands.
Beyond adding tests for the previously broken cases, also add ones for
the previously working cases where IgnoreSize is needed for the same
reason (leaving out MPX for now, as that'll require an assembler change
first). Some minor adjustments to tests get done such that re-use of the
same code for 16-bit code generation testing becomes easier.
Allowing 64-bit registers is misleading here: Elsewhere these get allowed
when there's no difference between either variant, because of 32-bit
destination registers having their upper halves zeroed in 64-bit mode.
Here, however, they're source registers, and hence specifying 64-bit
registers would lead to the ambiguity of whether the upper 32 bits
actually matter.
Additionally, for proper code generation in 16-bit mode, IgnoreSize is
needed on both.
And finally, just like for e.g. MONITOR/MWAIT, add variants with all
input registers explicitly specified.
gas/
* config/tc-riscv.c: Support the modifier %got_pcrel_hi.
* doc/c-riscv.texi: Add documentation.
* testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
modifier %got_pcrel_hi.
* testsuite/gas/riscv/no-relax-reloc.s: Likewise.
* testsuite/gas/riscv/relax-reloc.d: Likewise.
* testsuite/gas/riscv/relax-reloc.s: Likewise.
gas/
* doc/c-riscv.texi (relocation modifiers): Add documentation.
(RISC-V-Formats): Update the section name from "Instruction Formats"
to "RISC-V Instruction Formats".
* config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is
detected in a section which does not have at least 4 byte
alignment.
* testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive.
* testsuite/gas/arm/ldr-t.s: Likewise.
* testsuite/gas/arm/sp-pc-usage-t.s: Likewise.
* testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of
disassembly, ignoring any NOPs that may have been inserted because
of section alignment.
* testsuite/gas/arm/ldr-t.d: Likewise.
According to gas manual, suffix in instruction mnemonics isn't always
required:
When there is no sizing suffix and no (suitable) register operands to
deduce the size of memory operands, with a few exceptions and where long
operand size is possible in the first place, operand size will default
to long in 32- and 64-bit modes.
This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they
must be allowed without suffix in AT&T syntax.
gas/
PR gas/25622
* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
x86-64-default-suffix-avx.
* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
* testsuite/gas/i386/noreg64.d: Updated.
* testsuite/gas/i386/noreg64.l: Likewise.
* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
opcodes/
PR gas/25622
* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
* i386-tbl.h: Regenerated.
According to intel SDM manual, not all compare flag-modifying instructions
are marcro-fusible with subsequent jcc instructions. For those non-fusible
instructions, -malign-branch doesn't need to align them, only jcc itself
needs to be aligned.
Here are 2 restrictions which separate macro-fusible instruction from not
Restriction 1:
If TEST/AND/CMP/ADD/SUB/INC/DEC is one of the following format:
cmp m, imm
add m, imm
sub m, imm
test m, imm
and m, imm
inc m
dec m
it is unfusible with any jcc instruction.
Restriction 2:
/* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
Note it also works for Skylake and Cascadelake.
---------------------------------------------------------------------
| JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
| ------ | ----------- | ------- | -------- |
| Jo | N | N | Y |
| Jno | N | N | Y |
| Jc/Jb | Y | N | Y |
| Jae/Jnb | Y | N | Y |
| Je/Jz | Y | Y | Y |
| Jne/Jnz | Y | Y | Y |
| Jna/Jbe | Y | N | Y |
| Ja/Jnbe | Y | N | Y |
| Js | N | N | Y |
| Jns | N | N | Y |
| Jp/Jpe | N | N | Y |
| Jnp/Jpo | N | N | Y |
| Jl/Jnge | Y | Y | Y |
| Jge/Jnl | Y | Y | Y |
| Jle/Jng | Y | Y | Y |
| Jg/Jnle | Y | Y | Y |
Update maybe_fused_with_jcc_p to check if operands of CMP like instructions
can be fused with condition jump.
* gas/config/tc-i386.h (i386_tc_frag_data): Add member mf_type.
(TC_FRAG_INIT): Init mf_type.
* gas/config/tc-i386.c (enum mf_jcc_kind): New enum.
(enum mf_cmp_kind): Ditto.
(maybe_fused_with_jcc_p): Add argument mf_cmp_p to get
mf_type of corresponding instructons, exclude unfusible
instructions.
(add_fused_jcc_padding_frag_p): Likewise.
(add_branch_padding_frag_p): Likewise.
(output_insn): Record mf_type for corresponding instructions.
(i386_macro_fusible_p): New function.
(i386_next_fusible_jcc_frag): Rename from i386_next_jcc_frag,
add argument cmp_fragP to return next fusible jcc frag only.
(i386_classify_machine_dependant_frag): Seperate macro-fusible
instructions from condition jump.
* gas/testsuite/gas/i386/align-branch-9.s: New file.
* gas/testsuite/gas/i386/align-branch-9.d: Ditto.
* gas/testsuite/gas/i386/x86-64-align-branch-9.s: Ditto.
* gas/testsuite/gas/i386/x86-64-align-branch-9.d: Ditto.
* gas/testsuite/gas/i386/i386.exp: Run new tests.
This patch arranges for symbols defined in .sdata and .sbss to be
reported by nm with 'g' and 's' flags, for coff targets that support
.sdata and .sbss.
The assembler changes regarding SEC_SMALL_DATA are really just
documentation. As far as I'm aware, this won't change any assembler
output.
bfd/
* coff-alpha.c (alpha_ecoff_le_vec): Add SEC_SMALL_DATA to
applicable section flags.
* coff-mips.c (mips_ecoff_le_vec, mips_ecoff_be_vec): Likewise.
(mips_ecoff_bele_vec): Likewise.
* coffcode.h (sec_to_styp_flags): Set SEC_SMALL_DATA for .sdata
and .sbss sections.
* ecoff.c (_bfd_ecoff_new_section_hook): Likewise.
(_bfd_ecoff_styp_to_sec_flags): Likewise.
gas/
* config/tc-m32r.c (md_begin): Set SEC_SMALL_DATA on .scommon section.
* config/tc-mips.c (s_change_sec): Set SEC_SMALL_DATA for .sdata
and .sbss sections.
* config/tc-score.c: Delete !BFD_ASSEMBLER code throughout.
(s3_s_change_sec): Set SEC_SMALL_DATA for .sbss section.
(s3_s_score_lcomm): Likewise.
* config/tc-score7.c: Similarly.
* read.c (bss_alloc): Set SEC_SMALL_DATA for .sbss section.
When there is multi-labels on the same insn, the current code
will take care about the last one. it may cause that no sync
is added at the target.
Here we scan all labels with same value of
S_GET_VALUE(label_list->label)
by label_list->next.
2020-02-28 YunQiang Su <syq@debian.org>
PR gas/25539
* config/tc-mips.c (fix_loongson3_llsc): Compare label value
to handle multi-labels.
(has_label_name): New.
The implementation of the Arm CDE CX*A instructions doesn't allow a
condition code on the instructions but does allow the instruction in an
ITBlock.
The specification has been recently updated, though this is yet to be
published.
The instructions now should allow a suffix, and should behave in the
standard way around ITBlocks.
This patch removes the custom pred_instruction_type and handling for
these instructions, and uses the standard INSIDE_IT_INSN predication
type to describe the new instructions.
gas/ChangeLog:
2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (enum pred_instruction_type): Remove
NEUTRAL_IT_NO_VPT_INSN predication type.
(cxn_handle_predication): Modify to require condition suffixes.
(handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases.
* testsuite/gas/arm/cde-scalar.s: Update test.
* testsuite/gas/arm/cde-warnings.l: Update test.
* testsuite/gas/arm/cde-warnings.s: Update test.
gettext("") returns the header entry with meta information, not the
empty string.
* config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use
N_() on empty string.
Avoid a warning that the buffer may not be zero terminated.
* read.c (read_a_source_file): Call strncpy with length one
less than size of original_case_string.
CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write CSR
when RS1 isn't zero. The CSR is read only if the [11:10] bits of CSR address
is 0x3. The read-only CSR can not be written by the CSR instructions.
gas/
* config/tc-riscv.c (riscv_ip): New boolean insn_with_csr to indicate
we are assembling instruction with CSR. Call riscv_csr_read_only_check
after parsing all arguments.
(enum csr_insn_type): New enum is used to classify the CSR instruction.
(riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These
are used to check if we write a read-only CSR by the CSR instruction.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test
all CSR for the read-only CSR checking.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test
all CSR instructions for the read-only CSR checking.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
Add new .option `csr-check/no-csr-check` and GAS option `-mcsr-check
/-mno-csr-check` to enbale/disable the CSR checking. Disable the CSR
checking by default.
gas/
* config/tc-riscv.c: Add new .option and GAS options to enbale/disable
the CSR checking. We disable the CSR checking by default.
(reg_lookup_internal): Check the `riscv_opts.csr_check`
before we doing the CSR checking.
* doc/c-riscv.texi: Add description for the new .option and assembler
options.
* testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable
the CSR checking.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information. We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option. Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.
gas/
* config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
whether or not this CSR is legal in the current ISA string.
(struct riscv_csr_extra): New structure to hold all extra information
of CSR.
(riscv_init_csr_hash): New function. According to the DECLARE_CSR and
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
Call hash_reg_name to insert CSR address into reg_names_hash.
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
Decide whether the CSR is valid according to the csr_extra_hash.
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
not a boolean. This is same as riscv_init_csr_hash, so keep the
consistent usage.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
f-ext CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
source file is `priv-reg.s`, and the ISA is rv64if, so the
rv32-only CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
include/
* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
record riscv_csr_class.
opcodes/
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
gdb/
* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
* riscv-tdep.h: Likewise.
* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
rv32-only CSR.
* features/riscv/64bit-csr.xml: Regernated.
binutils/
* dwarf.c: Updated since the DECLARE_CSR is changed.
This allows pdp11 to handle 32-bit fixups that can be applied by gas,
and improves the error message emitted when the required reloc isn't
available.
* config/tc-pdp11.c (md_apply_fix): Handle BFD_RELOC_32.
(tc_gen_reloc): Only give a BAD_CASE assertion on pcrel relocs.
This patch fixes an ancient wart in aout support, in that text and
data section sizes are rounded up for alignment rather that just the
corresponding header sizes. Changing section sizes could conceivably
result in buffer overflows if section contents were held in memory.
Also, keeping the original section sizes allows this PR to be fixed
nicely.
bfd/
PR 25569
* aoutx.h (adjust_o_magic, adjust_z_magic, adjust_n_magic): Use
"text", "data" and "bss" section pointer vars. Don't update
section size, just exec header sizes.
(adjust_sizes_and_vmas): Don't update text section size. Set
initial exec header a_text. Print exec headers sizes.
* pdp11.c (adjust_o_magic, adjust_z_magic, adjust_n_magic),
(adjust_sizes_and_vmas): Similarly. Formatting.
(final_link): Correct final file extension.
gas/
PR 25569
* config/obj-aout.c (obj_aout_frob_file_before_fix): Don't loop
on section size adjustment, instead perform another write if
exec header size is larger than section size.
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
gas/
* testsuite/gas/riscv/c-add-addi.d: New testcase.
* testsuite/gas/riscv/c-add-addi.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
c.mv/c.li if rs1 is zero.
Change-Id: Id939b5e6db80d267a832545f3ffef7b9ba881f7d
* config/tc-i386.c (output_insn): Mark cvtpi2ps and cvtpi2pd
with GNU_PROPERTY_X86_FEATURE_2_MMX.
* testsuite/gas/i386/i386.exp: Run property-3 and
x86-64-property-3.
* testsuite/gas/i386/property-3.d: New file.
* testsuite/gas/i386/property-3.s: Likewise.
* testsuite/gas/i386/x86-64-property-3.d: Likewise.
AMD ABM has 2 instructions: popcnt and lzcnt. ABM CPUID feature bit has
been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt
which used to be the part of SSE4.2. This patch removes CpuABM and adds
CpuPOPCNT. It changes ABM to enable both lzcnt and popcnt, changes SSE4.2
to also enable popcnt.
gas/
* config/tc-i386.c (cpu_arch): Add .popcnt.
* doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt.
Add a tab before @samp{.sse4a}.
opcodes/
* i386-gen.c (cpu_flag_init): Replace CpuABM with
CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
CPU_POPCNT_FLAGS.
(cpu_flags): Remove CpuABM. Add CpuPOPCNT.
* i386-opc.h (CpuABM): Removed.
(CpuPOPCNT): New.
(i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
popcnt. Remove CpuABM from lzcnt.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
There's no need to have separate Cpu64 and CpuNo64 templates: There
already is special logic handling the attribute, and all that's needed
is rejecting 16-bit address registers in 64-bit mode. Suppress suffix
guessing and group all involved logic together, outside of suffix
processing (arguably it doesn't even belong in process_suffix()).
Also, since no AddrPrefixOpReg template permits any suffixes, move the
No_*Suf specifiers for them to a central place. Along with this drop
the no longer relevant NoRex64 from there.
Generally, the documentation doesn't allow for any explicit operands
to be specified with MONITOR/MWAIT. To permit the more legible
overriding of the address size via specifying operands, the option is
being retained even in Intel mode, but operand swapping is being
suppressed by this patch. This is both because it makes no sense here
(all of the operands are inputs) and because, as a result, old gcc
(prior to 4.8) actually expects it this way with -mintel-syntax (and
hence gets fixed by this change rather than, as claimed by a reply in
the bug report, broken).
Conversions which shrink element size and which have a memory source
can't be disambiguated between their 128- and 256-bit variants by
looking at the register operand. "operand size mismatch", however, is a
pretty misleading diagnostic. Generalize the logic introduced for
VFPCLASSP{S,D} such that, with suitable similar adjustments to the
respective templates, it'll cover these cases too.
For VCVTNEPS2BF16 also fold the two previously separate AVX512VL
templates to achieve the intended effect. This is then also accompanied
by a respective addition to the inval-avx512f testcase.
commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is
a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel
SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also
adds .sse4a and nosse4a.
gas/
* config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore
nosse4.
* doc/c-i386.texi: Document sse4a and nosse4a.
opcodes/
* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
CPU_ANY_SSE4_FLAGS.
For these to get treatment consistent with other operand size checking
the special logic shouldn't live in md_assemble(), but process_suffix().
And there's more logic involved than simply zapping the suffix.
Note however that MOVS[BW]* and MOVZ[BW]* still won't be fully
consistent, due to the objection to fold MOVS* templates just like was
done for MOVZ* in c07315e0c6 ("x86: allow suffix-less movzw and 64-bit
movzb").
Note further that it is against my own intentions to have MOVSX/MOVZX
silently default to a byte source in AT&T mode. This should happen only
when the destination register is a 16-bit one. In all other cases there
is an ambiguity, and the user should be warned. But it was explicitly
requested for this to be done in a way inconsistent with everything
else.
Note finally that the assembler change points out (and this patch fixes)
a wrong Intel syntax test introduced by bc31405ebb ("x86-64: Properly
encode and decode movsxd"): When source code specifies a 16-bit
destination register, disassembly expectations shouldn't have been to
find a 32-bit one.
Since we already suppress the prefix altogether when it's the default
one for the chosen addressing mode, let's do so also when instruction
prefix and override specified with the memory operand match. (Note that
insn prefix specified segment overrides never get discarded.)
For one both possible forms should be warned about. And then, to guard
against future surprises, qualify the original opcode check by excluding
VEX/EVEX-like templates.
Document different mnemonics of movsx, movsxd and movzx in AT&T syntax.
PR gas/25438
* doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T
syntax.
