Finally; sorry for the delay. There were a few false starts, where I
misinterpreted the error-messages and the comment that Alan added:
it's not the fix size that's too large (and the frag too small), it's
stating the wrong size of what will be "fixed up" - that of the actual
target value, not the size of the field that needs to be adjusted.
Comments added for clarity.
Test-suite committed separately.
gas:
PR gas/25331
* config/tc-mmix.c (md_assemble) <fixup for
BFD_RELOC_MMIX_BASE_PLUS_OFFSET>: This fixup affects 1 byte, not 8.
Also, set its fx_no_overflow.
(md_convert_frag) <case ENCODE_RELAX (STATE_PUSHJSTUB, STATE_ZERO)>:
Similarly this fixup affects 4 bytes, not 8 and needs its
fx_no_overflow set.
* config/tc-mmix.h (TC_FX_SIZE_SLACK): Don't define.
To support Intel AMX instructions with 8-bit immediate opcode extension,
but without operands:
tilerelease, 0, 0x49, 0xc0, 1, CpuAMX_TILE|Cpu64, Vex|VexOpcode=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
process ImmExt without operands.
* config/tc-i386.c (md_assemble): Process ImmExt without
operands.
Rename VecSIB to SIB to support Intel Advanced Matrix Extensions which
introduces instructions with a mandatory SIB byte which isn't a vector
SIB (VSIB).
gas/
* config/tc-i386.c (check_VecOperands): Replace vecsib with sib.
Replace VecSIB128, VecSIB256 and VecSIB512 with VECSIB128,
VECSIB256 and VECSIB512, respectively.
(build_modrm_byte): Replace vecsib with sib.
opcodes/
* i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
(VecSIB128): Renamed to ...
(VECSIB128): This.
(VecSIB256): Renamed to ...
(VECSIB256): This.
(VecSIB512): Renamed to ...
(VECSIB512): This.
(VecSIB): Renamed to ...
(SIB): This.
(i386_opcode_modifier): Replace vecsib with sib.
* i386-opc.tbl (VexSIB128): New.
(VecSIB256): Likewise.
(VecSIB512): Likewise.
Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VexSIB128, VecSIB256
and VecSIB512, respectively.
This patch adds GNU attribute support to m68k and utilises it to tag the
floating-point calling convention used (hard-float or soft-float). It enables
the linker to ensure linked objects use a consistent floating-point ABI and
allows tools like GDB to infer the ABI used from the ELF file. It is based on
similar work done for PowerPC.
bfd/
* elf32-m68k.c (m68k_elf_merge_obj_attributes): New function.
(elf32_m68k_merge_private_bfd_data): Merge GNU attributes.
binutils/
* readelf.c (display_m68k_gnu_attribute): New function.
(process_arch_specific): Call display_m68k_gnu_attribute for EM_68K.
gas/
* config/tc-m68k.c (m68k_elf_gnu_attribute): New function.
(md_pseudo_table): Handle "gnu_attribute".
* doc/as.texi: Document GNU attribute for M68K.
include/
* elf/m68k.h: Add enum for GNU object attribute with floating point
tag name and values.
ld/
* testsuite/ld-m68k/attr-gnu-4-0.s: New file.
* testsuite/ld-m68k/attr-gnu-4-1.s: Likewise.
* testsuite/ld-m68k/attr-gnu-4-2.s: Likewise.
* testsuite/ld-m68k/attr-gnu-4-00.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-01.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-02.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-10.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-11.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-12.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-20.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-21.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-22.d: Likewise.
* testsuite/ld-m68k/m68k.exp: Run the new tests.
With abuses of ImmExt gone, all templates using it have operands. Move
its main invocation into process_operands(), matching its secondary one
for the SSE2AVX case.
Use of an explicit data size or REX.W prefix is sufficient indication of
the intended operation when operand size can't be derived from suffix or
register operands. Avoid the ambiguity warning and make in particular
immediate handling (sizing) cope with explicitly specified prefixes.
Extending/reusing the noreg16 test made me notice a few cases of
unintentional 32-bit addressing, which gets corrected at the same time.
Just like for the data size prefix (see commit 7a8655d2bb ["x86: don't
abort() upon DATA16 prefix on (E)VEX encoded insn"]), any form of REX
prefix is invalid with VEX/XOP/EVEX.
Legacy encoded insns do so, and their automatic conversion to AVX ones
ought to produce functionally identical code. Therefore explicit REX
prefixes cannot simply be ignored. This is in particular relevant
because at least PCMPESTR{I,M}'s 64-bit forms couldn't be expressed in
older gas by other than using a REX64 prefix.
The data size prefix alters the meaning of legacy encoded SIMD insns,
and hence shouldn't be accepted there. Use of it also leads to
inconsistencies in SSE2AVX mode. Don't match insns with data size prefix
against SSE2AVX templates.
We should generate the ELF priv attributes only if,
1. The priv attributes are already set in the assembly file.
2. The CSR are explicited used.
3. The privileged instruction are explicited used.
* There are four privileged instruction defined in the v1.11 priv spec:
`mret`, `sret`, `wfi` and `sfence.vma`.
* `sfence.vm` is dropped in the v1.10 priv spec.
* `uret` is actually a N-ext instruction. So it is better to regard it as
an user instruction rather than the priv instruction.
* `hret` is used to return from traps in H-mode. H-mode is removed since
the v1.10 priv spec, but probably be added in the new hypervisor spec.
Therefore, `hret` should be controlled by the hypervisor spec rather than
priv spec in the future.
* `dret` is a debug instruction. We should record the debug spec versions
once it is explicited used in the future.
gas/
* config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to
explicit_priv_attr. It used to indicate CSR or priv instructions are
explictly used.
(riscv_is_priv_insn): Return True if it is a privileged instruction.
(riscv_ip): Call riscv_is_priv_insn to check whether the instruction
is privileged or not. If it is, then set explicit_priv_attr to TRUE.
(riscv_write_out_attrs): Clarification of when to generate the elf
priv spec attributes.
* testsuite/gas/riscv/attribute-11.s: Add comments.
* testsuite/gas/riscv/attribute-14.s: New testcase. Use symbol
`priv_insn_<n>` to decide which priv instruction is expected to used.
(<n> is a to g.)
* testsuite/gas/riscv/attribute-14a.d: Likewise.
* testsuite/gas/riscv/attribute-14b.d: Likewise.
* testsuite/gas/riscv/attribute-14c.d: Likewise.
* testsuite/gas/riscv/attribute-14d.d: Likewise.
* testsuite/gas/riscv/attribute-14e.d: Likewise.
We do know some conflicts among different privileged specs. For linker,
the safest approach is that don't allow the object linked with others which
may cause conflicts. But this may cause inconvenience since not all objects
with conflicting priv specs are linked will cause problems. But it is hard
to know the detailed conflict cases for linker, so we probably need a option
to tell linker that we do know there are no conflicts, or we are willing to
take risks to link the objects with conflicted priv specs. But the option
is still under discussion.
Therefore, we can report warnings rather than errors when linking the objects
with conflicted priv specs. This not only makes the linker more flexible,
but also warns people that the conflicts may happen. We also need to update
the output priv spec version once the input priv spec is newer.
bfd/
* elfxx-riscv.c (struct priv_spec_t priv_specs[]): Move them from
opcodes/riscv-opc.c to bfd/elfxx-riscv.c, since we need it in linker.
(riscv_get_priv_spec_class): Likewise.
(riscv_get_priv_spec_name): Likewise.
(riscv_get_priv_spec_class_from_numbers): New function, convert
the version numbers into string, then call riscv_get_priv_spec_class
to get the priv spec class.
* elfxx-riscv.h (riscv_get_priv_spec_class): Move forward declaration
from include/opcode/riscv.h to bfd/elfxx-riscv.h.
(riscv_get_priv_spec_name): Likewise.
(riscv_get_priv_spec_class_from_numbers): New forward declaration.
(opcode/riscv.h): Include it in the header rather than elfxx-riscv.c.
* elfnn-riscv.c (riscv_merge_attributes): Get the priv spec classes
of input and output objects form their priv spec attributes by
riscv_get_priv_spec_class_from_numbers. Report warning rather than
errors when linking objects with differnet priv spec versions. We do
know v1.9.1 may have conflicts to other versions, so report the
warning, too. After that, update the output priv spec version to the
newest one so far.
gas/
* config/tc-riscv.c (buf_size, buf): Remove the unused variables.
(riscv_set_default_priv_spec): Get the priv spec version from the
priv spec attributes by riscv_get_priv_spec_class_from_numbers.
include/
* opcode/riscv.h (riscv_get_priv_spec_class): Move the function
forward declarations to bfd/elfxx-riscv.h.
(riscv_get_priv_spec_name): Likewise.
opcodes/
* riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
* riscv-dis.c: Include elfxx-riscv.h.
ld/
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Updated.
Upon re-consideration in commit 569d50f1c6 ("x86: further refine SSE
check (SSE4a, SHA, GFNI)") I went too far: Mixing of SSE and AVX insns
doesn't suffer as bad a penalty on AMD CPUs as on Intel ones. SSE4a
being an AMD-only extension, it shouldn't be part of the ISA extensions
set for which the diagnostic may get issued. Undo that part.
2020-06-15 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* elf32-xtensa.c (XSHAL_ABI, XTHAL_ABI_UNDEFINED)
(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros.
(elf32xtensa_abi): New global variable.
(xtensa_abi_choice): New function.
(elf_xtensa_create_plt_entry): Use xtensa_abi_choice instead of
XSHAL_ABI to select PLT code.
gas/
* config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
macros.
(elf32xtensa_abi): New declaration.
(option_abi_windowed, option_abi_call0): New enum constants.
(md_longopts): Add entries for --abi-windowed and --abi-call0.
(md_parse_option): Add handlers for --abi-windowed and
--abi-call0.
(xtensa_add_config_info): Use xtensa_abi_choice instead of
XSHAL_ABI to format ABI tag.
* doc/as.texi (Target Xtensa options): Add --abi-windowed and
--abi-call0 to the list of options.
* doc/c-xtensa.texi: Add description for options --abi-windowed
and --abi-call0.
* testsuite/gas/xtensa/abi-call0.d: New test definition.
* testsuite/gas/xtensa/abi-windowed.d: New test definition.
* testsuite/gas/xtensa/abi.s: New test source.
include/
* elf/xtensa.h (xtensa_abi_choice): New declaration.
ld/
* emultempl/xtensaelf.em (XSHAL_ABI): Remove macro definition.
(XTHAL_ABI_UNDEFINED, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
macros.
(elf32xtensa_abi): New declaration.
(xt_config_info_unpack_and_check): Set elf32xtensa_abi if it is
undefined. Use xtensa_abi_choice instead of XSHAL_ABI to test
ABI tag consistency.
(xtensa_add_config_info): Use xtensa_abi_choice instead of
XSHAL_ABI to format ABI tag.
(PARSE_AND_LIST_PROLOGUE): Define OPTION_ABI_WINDOWED,
OPTION_ABI_CALL0 and declare elf32xtensa_abi.
(PARSE_AND_LIST_LONGOPTS): Add entries for --abi-windowed and
--abi-call0.
(PARSE_AND_LIST_OPTIONS): Add help text for --abi-windowed and
--abi-call0.
(PARSE_AND_LIST_ARGS_CASES): Add handlers for --abi-windowed and
--abi-call0.
* ld.texi: Add description for options --abi-windowed and
--abi-call0.
An unwanted side effect of 5990e377e5 ("x86-64: Intel64 adjustments
for insns dealing with far pointers") was that with -mintel64 LCALL and
LJMP would now default to 64-bit operand size. Since 64-bit far branches
aren't portable, the default operand size should still be 32-bit.
However, since the 64-bit variant is permitted, an ambiguous operand
warning should be issued.
As to the actual code change, please note that the conditional
surrounding the switch() that gets adjusted covers several cases which
are of no interest to or benign in 64-bit mode, hence the new
conditional added can be quite a bit less involved.
{vex}, {vex3}, and {evex} are mandatory prefixes, and hence should not
be randomly ignored. Fix this for insns without operands as well as for
insns referencing the high 16 [XYZ]MM registers. To achieve the former,
re-purpose VEX_check_operands(), renaming it to VEX_check_encoding() and
moving its only operand check to check_VecOperands().
This involves fixing a testcase relying on {vex2} to get ignored.
With the introduction of what right now is the very first conditional
in the function's loop (commit dc821c5f9a ["x86: replace Reg8, Reg16,
Reg32, and Reg64"]), the last if() in the same loop has become
pointless - retain just its body.
First of all, these registers have never been available on any 64-bit
CPU, and hence should not be recognized in 64-bit mode. But even before
that they had already disappeared - also don't recognize them when 586
or 686 architectures were explicitly set.
In 0e0eea7820 ("x86: x87-related adjustments") I screwed up CFI
directives with FPU support disabled, by moving the conditional there
across a check of "allow_pseudo_reg". Add the missing check.
Register aliases (created e.g. via .set) check their target register at
the time of creation of the alias. While this makes sense, it's not
enough: The underlying register must also be "visible" at the time of
use. Wrong use of such aliases would lead to internal errors in e.g.
add_prefix() or build_modrm_byte().
Split the checking part of parse_real_register() into a new helper
function and use it also from the latter part of parse_register() (at
the same time replacing a minor open coded part of it).
Since parse_register() returning NULL already has a meaning, a fake new
"bad register" indicator gets added, which all callers need to check
for.
These relocations should have had REL in their names, to reflect the
fact that they are pc-relative. Fix that now by adding _PCREL.
I've added some back-compatibility code to support anyone using
.reloc with the old relocations.
include/
* elf/ppc64.h (elf_ppc64_reloc_type): Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
bfd/
* reloc.c: Rename
BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34,
BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34,
BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34,
BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34.
* elf64-ppc.c: Update throughout for reloc renaming.
(ppc64_elf_reloc_name_lookup): Handle old reloc names.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c: Update throughout for reloc renaming.
elfcpp/
* powerpc.h: Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
gold/
* powerpc.cc: Update throughout for reloc renaming.
The GAS struct frag ends with a field `fr_literal' whose purpose is to
mark the begining of the frag's data:
struct frag {
...
/* Data begins here. */
char fr_literal[1];
};
The code in gas/config/tc-bpf.c recently committed:
where = fixP->fx_frag->fr_literal + fixP->fx_where;
where[1] = target_big_endian ? 0x01 : 0x10;
triggers the stringop-overflow warning in GCC 10+, since the compiler
assumes the size of the modified buffer is 1 byte. This patch
slightly modifies the code to make tc-bpf.c buildable with GCC 10+.
2020-06-05 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (md_apply_fix): Avoid GCC 10 warning
stringop-overflow.
gas/
* config/tc-riscv.c (explicit_csr): New static boolean.
Used to indicate CSR are explictly used.
(riscv_ip): Set explicit_csr to TRUE if any CSR is used.
(riscv_write_out_attrs): If we already have set elf priv
attributes, then generate them. Otherwise, don't generate
them when no CSR are used.
* testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-11.s: New testcase.
* testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is
used, so we should output the ELF priv attributes.
* testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is
used, so output the priv attributes according to the -mpriv-spec.
* testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't
used, so ignore the -mpriv-spec setting.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
* testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
Fix ip2k-elf and xstormy16-elf build due to
commit e9bffec9af
Author: Jose E. Marchesi <jose.marchesi@oracle.com>
Date: Thu Jun 4 16:15:53 2020 +0200
opcodes: discriminate endianness and insn-endianness in CGEN ports
* config/tc-ip2k. (ip2k_apply_fix): Pass endianness to
cgen_get_insn_value.
* config/tc-xstormy16.c (xstormy16_md_apply_fix): Pass
endianness to cgen_get_insn_value and cgen_put_insn_value.
cpu/ChangeLog:
2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64.
* bpf.opc (bpf_print_insn): Do not set endian_code here.
gas/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to
bpf_cgen_cpu_open.
(md_assemble): Remove no longer needed hack.
opcodes/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* disassemble.c (disassemble_init_for_target): Set endian_code for
bpf targets.
* bpf-desc.c: Regenerate.
* bpf-opc.c: Likewise.
* bpf-dis.c: Likewise.
The CGEN support code in opcodes accesses instruction contents using a
couple of functions defined in cgen-opc.c: cgen_get_insn_value and
cgen_put_insn_value. These functions use the "instruction endianness"
in the CPU description to order the read/written bytes.
The process of writing an instruction to the object file is:
a) cgen_put_insn_value ;; Writes out the opcodes.
b) ARCH_cgen_insert_operand
insert_normal
insert_1
cgen_put_insn_value ;; Writes out the bytes of the
;; operand.
Likewise, the process of reading an instruction from the object file
is:
a) cgen_get_insn_value ;; Reads the opcodes.
b) ARCH_cgen_extract_operand
extract_normal
extract_1
cgen_get_insn_value ;; Reads in the bytes of the
;; operand.
As can be seen above, cgen_{get,put}_insn_value are used to both
process the instruction opcodes (the constant fields conforming the
base instruction) and also the values of the instruction operands,
such as immediates.
This is problematic for architectures in which the endianness of
instructions is different to the endianness of data. An example is
BPF, where instructions are always encoded big-endian but the data may
be either big or little.
This patch changes the cgen_{get,put}_insn_value functions in order to
get an extra argument with the endianness to use, and adapts the
existin callers to these functions in order to provide cd->endian or
cd->insn_endian, whatever appropriate. Callers like extract_1 and
insert_1 pass cd->endian (since they are reading/writing operand
values) while callers reading/writing the base instruction pass
cd->insn_endian instead.
A few little adjustments have been needed in some existing CGEN based
ports:
* The BPF assembler uses cgen_put_insn_value. It has been adapted to
pass the new endian argument.
* The mep port has code in mep.opc that uses cgen_{get,put}_insn_value.
It has been adapted to pass the new endianargument. Ditto for a
call in the assembler.
Tested with --enable-targets=all.
Regested in all supported targets.
No regressions.
include/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/cgen.h: Get an `endian' argument in both
cgen_get_insn_value and cgen_put_insn_value.
opcodes/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
(cgen_put_insn_value): Likewise.
(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
* cgen-dis.in (print_insn): Likewise.
* cgen-ibld.in (insert_1): Likewise.
(insert_1): Likewise.
(insert_insn_normal): Likewise.
(extract_1): Likewise.
* bpf-dis.c: Regenerate.
* bpf-ibld.c: Likewise.
* bpf-ibld.c: Likewise.
* cgen-dis.in: Likewise.
* cgen-ibld.in: Likewise.
* cgen-opc.c: Likewise.
* epiphany-dis.c: Likewise.
* epiphany-ibld.c: Likewise.
* fr30-dis.c: Likewise.
* fr30-ibld.c: Likewise.
* frv-dis.c: Likewise.
* frv-ibld.c: Likewise.
* ip2k-dis.c: Likewise.
* ip2k-ibld.c: Likewise.
* iq2000-dis.c: Likewise.
* iq2000-ibld.c: Likewise.
* lm32-dis.c: Likewise.
* lm32-ibld.c: Likewise.
* m32c-dis.c: Likewise.
* m32c-ibld.c: Likewise.
* m32r-dis.c: Likewise.
* m32r-ibld.c: Likewise.
* mep-dis.c: Likewise.
* mep-ibld.c: Likewise.
* mt-dis.c: Likewise.
* mt-ibld.c: Likewise.
* or1k-dis.c: Likewise.
* or1k-ibld.c: Likewise.
* xc16x-dis.c: Likewise.
* xc16x-ibld.c: Likewise.
* xstormy16-dis.c: Likewise.
* xstormy16-ibld.c: Likewise.
gas/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen.c (gas_cgen_finish_insn): Pass the endianness to
cgen_put_insn_value.
(gas_cgen_md_apply_fix): Likewise.
(gas_cgen_md_apply_fix): Likewise.
* config/tc-bpf.c (md_apply_fix): Pass data endianness to
cgen_put_insn_value.
* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
cgen_put_insn_value.
cpu/ChangeLog:
2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* mep.opc (print_slot_insn): Pass the insn endianness to
cgen_get_insn_value.
These failures were caused by the PDP11's mix of little-endian octets
in shorts but shorts in big endian order for long or quad so regexps
did not match. Also tests used addresses as values in .long which
required BRD_RELOC_32 that was not implemented.
* gas/config/tc-pdp11.c (md_number_to_chars): Implement .quad
* gas/testsuite/gas/all/gas.exp: Select alternate test scripts for
pdp11, skip octa test completely.
* gas/testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s
* gas/testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order.
* gas/testsuite/gas/all/cond-pdp11.l: Match different octet order.
* bfd/pdp11.c: Implement BRD_RELOC_32 to relocate the low 16 bits of
addreses in .long (used in testsuites) and .stab values.
PR gas/26001
* gas/config/tc-pdp11.c (parse_reg): Distinguish register names from
symbols that begin with a register name.
* gas/testsuite/gas/pdp11/pdp11.exp: Add test of such symbols.
* gas/testsuite/gas/pdp11/pr26001.s: Likewise.
* gas/testsuite/gas/pdp11/pr26001.d: Likewise.
The next pointer of struct riscv_csr_extra was not always initilized
to NULL or a valid pointer, causing the assembler to attempt to read
through an uninitialized pointer on startup.
gas/ChangeLog:
* config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next
pointer when creating struct riscv_csr_extra.
opcode/crx.h has
typedef enum
{
...
MAX_REG
}
reg;
typedef enum
{
c0 = MAX_REG,
}
copreg;
tc-crx.c has
static int
getreg_image (reg r)
{
...
/* Check whether the register is in registers table. */
if (r < MAX_REG)
rreg = &crx_regtab[r];
/* Check whether the register is in coprocessor registers table. */
else if (r < (int) MAX_COPREG)
rreg = &crx_copregtab[r-MAX_REG];
}
Change getreg_image's argument type to int and replace fragP->fr_literal
with &fragP->fr_literal[0] to silence GCC 10 warning.
PR gas/26044
* config/tc-crx.c (getreg_image): Change argument type to int.
(md_convert_frag): Replace fragP->fr_literal with
&fragP->fr_literal[0].
The frag code makes a distinction between inserting frags before the frag
chains are chained together and afterward. After chaining, we need to set
now_seg before creating the frag. tc-xtensa.c has a function called
fix_new_exp_in_seg that handles this right, but switches segments twice each
time it is called. In this case, we can inline it and pull the save and
restore out of the loop to get better code.
gas/
PR 26025
* config/tc-riscv.c (riscv_pre_output_hook): Change s type from const
asection to segT. New locals seg and subseg. Call subseg_set before
fix_new_exp. Call subseg_set after loop to restore original values.
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.
2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.
3. Spilt the patches to reduce the burdens of review.
[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.
[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.
4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.
include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
(enum riscv_isa_spec_class): New enum class. All supported ISA spec
belong to one of the class
(struct riscv_ext_version): New structure holds version information
for the specific ISA.
* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
define_version and abort_version. The define_version means which
privilege spec is started to define the CSR, and the abort_version
means which privilege spec is started to abort the CSR. If the CSR is
valid for the newest spec, then the abort_version should be
PRIV_SPEC_CLASS_DRAFT.
(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
* opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define
the current supported privilege spec versions.
(struct riscv_csr_extra): Add new fields to store more information
about the CSR. We use these information to find the suitable CSR
address when user choosing a specific privilege spec.
binutils * dwarf.c: Updated since DECLARE_CSR is changed.
opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store
all information about the supported spec and the corresponding ISA
versions. Currently, only Zicsr is supported to verify the
correctness of Z sub extension settings. Others will be supported
in the future patches.
(struct isa_spec_t, isa_specs): List for all supported ISA spec
classes and the corresponding strings.
(riscv_get_isa_spec_class): New function. Get the corresponding ISA
spec class by giving a ISA spec string.
* riscv-opc.c (struct priv_spec_t): New structure.
(struct priv_spec_t priv_specs): List for all supported privilege spec
classes and the corresponding strings.
(riscv_get_priv_spec_class): New function. Get the corresponding
privilege spec class by giving a spec string.
(riscv_get_priv_spec_name): New function. Get the corresponding
privilege spec string by giving a CSR version class.
* riscv-dis.c: Updated since DECLARE_CSR is changed.
* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
according to the chosen version. Build a hash table riscv_csr_hash to
store the valid CSR for the chosen pirv verison. Dump the direct
CSR address rather than it's name if it is invalid.
(parse_riscv_dis_option_without_args): New function. Parse the options
without arguments.
(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
parse the options without arguments first, and then handle the options
with arguments. Add the new option -Mpriv-spec, which has argument.
* riscv-dis.c (print_riscv_disassembler_options): Add description
about the new OBJDUMP option.
ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
priv attributes according to the -mpriv-spec option.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
get_default_version. It is used to find the default version for
the specific extension.
* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
default_major_version and default_minor_version. Add new bfd_boolean
parameter *use_default_version. Set it to TRUE if we need to call
the callback rps->get_default_version to find the default version.
(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
the default version in riscv_parsing_subset_version, and then call
riscv_add_subset to add the subset into subset list.
(riscv_parse_prefixed_ext): Likewise.
(riscv_std_z_ext_strtab): Support Zicsr extensions.
* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
strings rather than characters.
riscv_merge_arch_attr_info): The callback function get_default_version
is only needed for assembler, so set it to NULL int the linker.
* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
* elfxx-riscv.h: Updated.
gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
Static variables which are used to set the ISA extensions. You can
use -march (or ELF build attributes) and -misa-spec to set them,
respectively.
(ext_version_hash): The hash table used to handle the extensions
with versions.
(init_ext_version_hash): Initialize the ext_version_hash according
to riscv_ext_version_table.
(riscv_get_default_ext_version): The callback function of
riscv_parse_subset_t. According to the choosed ISA spec,
get the default version for the specific extension.
(riscv_set_arch): Set the callback function.
(enum options, struct option md_longopts): Add new option -misa-spec.
(md_parse_option): Do not call riscv_set_arch for -march. We will
call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
to set default_isa_spec class.
(riscv_after_parse_args): Call init_ext_version_hash to initialize the
ext_version_hash, and then call riscv_set_arch to set the architecture
with versions according to default_arch_with_ext.
* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
x extensions.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
already set it's version to 2p1 by march, so no need to use the default
2p2 version. For m-ext, we do not set the version by -march and ELF arch
attribute, so set the default 2p0 to it. For zicsr, it is not defined in
ISA spec 2p2, so set 0p0 to it.
* testsuite/gas/riscv/attribute-10.d: New testcase. The version of
zicsr is 2p0 according to ISA spec 20191213.
* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
You can set them by configure options --with-arch and
--with-isa-spec, respectively.
(riscv_set_default_isa_spec): New function used to set the
default ISA spec.
(md_parse_option): Call riscv_set_default_isa_spec rather than
call riscv_get_isa_spec_class directly.
(riscv_after_parse_args): If the -isa-spec is not set, then we
set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
calling riscv_set_default_isa_spec.
* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
the --with-isa-spec may be set to different ISA spec.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* configure.ac: Add configure options, --with-arch and
--with-isa-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (default_priv_spec): Static variable which is
used to check if the CSR is valid for the chosen privilege spec. You
can use -mpriv-spec to set it.
(enum reg_class): We now get the CSR address from csr_extra_hash rather
than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
(riscv_init_csr_hashes): Only need to initialize one hash table
csr_extra_hash.
(riscv_csr_class_check): Change the return type to void. Don't check
the ISA dependency if -mcsr-check isn't set.
(riscv_csr_version_check): New function. Check and find the CSR address
from csr_extra_hash, according to default_priv_spec. Report warning
for the invalid CSR if -mcsr-check is set.
(reg_csr_lookup_internal): Updated.
(reg_lookup_internal): Likewise.
(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
(md_parse_option): Call riscv_set_default_priv_version to set
default_priv_spec.
(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
privilege spec to the newest one.
(enum riscv_csr_class, struct riscv_csr_extra): Move them to
include/opcode/riscv.h.
* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
to check the ISA dependency for CSR, so fix the spec version by adding
-mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
version warnings for the test case.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
Check whether the CSR is valid when privilege version 1.9 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
Check whether the CSR is valid when privilege version 1.10 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
Check whether the CSR is valid when privilege version 1.11 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
setting. You can set it by configure option --with-priv-spec.
(riscv_set_default_priv_spec): New function used to set the default
privilege spec.
(md_parse_option): Call riscv_set_default_priv_spec rather than
call riscv_get_priv_spec_class directly.
(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
calling riscv_set_default_priv_spec.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
the --with-priv-spec may be set to different privilege spec.
* testsuite/gas/riscv/priv-reg.d: Likewise.
* configure.ac: Add configure option --with-priv-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
explicit_attr. Set it to TRUE if any ELF attribute is found.
(riscv_set_default_priv_spec): Try to set the default_priv_spec if
the priv attributes are set.
(md_assemble): Set the default_priv_spec according to the priv
attributes when we start to assemble instruction.
(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
riscv_write_out_attrs. Update the arch and priv attributes. If we
don't set the corresponding ELF attributes, then try to output the
default ones.
(riscv_set_public_attributes): If any ELF attribute or -march-attr
options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
to update the arch and priv attributes.
(s_riscv_attribute): Make sure all arch and priv attributes are set
before any instruction.
* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
ELF attribute or -march-attr is set. If the priv attributes are not
set, then try to update them by the default setting (-mpriv-spec or
--with-priv-spec).
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
set by priv attributes must be supported.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
priv attributes according to the -mpriv-spec option.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg.d: Removed.
* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
CSR according to the priv spec 1.9.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
CSR according to the priv spec 1.9.1.
* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
CSR according to the priv spec 1.10.
* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
CSR according to the priv spec 1.11.
* config/tc-riscv.c (md_show_usage): Add descriptions about
the new GAS options.
* doc/c-riscv.texi: Likewise.
