In commit:
commit 7b01c1cc1d
Date: Mon Apr 4 22:38:04 2022 +0100
sim: fixes for libopcodes styled disassembler
changes were made to the simulator source to handle the new libopcodes
disassembler styling API.
Unfortunately, these changes broke building GDB with the erc32 (sparc)
simulator, like this:
../src/configure --target=sparc-linux
make all-gdb
....
/usr/bin/ld: ../sim/erc32/libsim.a(interf.o): in function `sim_open':
/tmp/build/sim/../../src/sim/erc32/interf.c:247: undefined reference to `fprintf_styled'
collect2: error: ld returned 1 exit status
The problem is that in commit 7b01c1cc1d the fprintf_styled function
was added into sis.c. This file is only used when building the 'run'
binary, that is, the standalone simulator, and is not included in the
libsim.a library.
Now, the obvious fix would be to move fprintf_styled into libsim.a,
however, that turns out to be tricky.
The erc32 simulator currently has two copies of the function run_sim,
one in sis.c, and one in interf.c, both of these copies are global.
Currently, the 'run' binary links fine, though I suspect this might be
pure luck. When I tried moving fprintf_styled into interf.c, I ran
into multiple-definition (of run_sim) errors. I suspect that by
requiring the linker to pull in fprintf_styled from libsim.a I was
changing the order in which symbols were loaded, and the linker was
now seeing both copies of run_sim, while currently we only see one
copy.
The ideal solution of course, would be to merge the two similar, but
slightly different copies of run_sim, and just use the one copy. Then
we could safely move fprintf_styled into interf.c too, and all would
be good.
But I don't have time right now to start debugging the erc32
simulator, so I wanted a solution that fixes the build without
introducing multiple definition errors.
The easiest solution I think is to just have two copies of
fprintf_styled, one in sis.c, and one in interf.c. Unlike run_sim,
these two copies are both static, so we will not run into multiple
definition issues with this function. The functions themselves are
not very big, so it's not a huge amount of duplicate code.
I am very aware that this is not an ideal solution, and I would
welcome anyone who wants to take on fixing the run_sim problem
properly, and then cleanup the fprintf_styled duplication.
When generating TLS dynamic relocations the existing xtensa BFD code
treats linking to a PIE exactly as linking to a shared object, resulting
in generation of wrong relocations for TLS entries. Fix that and add
tests.
bfd/
* elf32-xtensa.c (elf_xtensa_check_relocs): Use bfd_link_dll
instead of bfd_link_pic. Add elf_xtensa_dynamic_symbol_p test
when generating GOT entries.
(elf_xtensa_relocate_section): Use bfd_link_dll instead of
bfd_link_pic.
ld/
* testsuite/ld-xtensa/tlspie.dd: New file.
* testsuite/ld-xtensa/tlspie.rd: New file.
* testsuite/ld-xtensa/tlspie.sd: New file.
* testsuite/ld-xtensa/tlspie.td: New file.
* testsuite/ld-xtensa/xtensa-linux.exp (TLS PIE transitions):
New test.
objdump output for l32r opcode was changed in commit b3ea76397a
("opcodes: xtensa: display loaded literal value"), but xtensa linker TLS
relaxation tests weren't adjusted accordingly.
readelf output was changed in commit 2335639744 ("Adjust readelf's
output so that section symbols without a name as shown with their
section name."), but xtensa linker TLS relaxation tests weren't adjusted
accordingly.
Fix expected output changes in xtensa ld TLS relaxation tests.
ld/
* testsuite/ld-xtensa/tlsbin.dd: Adjust expected output for l32r
opcodes.
* testsuite/ld-xtensa/tlsbin.rd: Adjust expected output to allow
for named section symbols.
* testsuite/ld-xtensa/tlspic.dd: Adjust expected output for l32r
opcodes.
* testsuite/ld-xtensa/tlspic.rd: Adjust expected output to allow
for named section symbols.
This patch makes possible to print the highest address (-1) and the addresses
related to gp which value is -1. This is particularly useful if the highest
address space is used for I/O registers and corresponding symbols are defined.
Besides, despite that it is very rare to have GP the highest address, it would
be nice because we enabled highest address printing on regular cases.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-topaddr.s: New test for the top
address (-1) printing.
* testsuite/gas/riscv/dis-addr-topaddr-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-64.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp.s: New test for
GP-relative addressing when GP is the highest address (-1).
* testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise.
opcodes/ChangeLog:
* riscv-dis.c (struct riscv_private_data): Add `to_print_addr' to
enable printing the highest address.
(maybe_print_address): Utilize `to_print_addr'.
(riscv_disassemble_insn): Likewise.
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an
incorrectly sign-extended address is produced when printing. This commit
fixes this by fitting an address into a 32-bit value on RV32.
Besides, H. Peter Anvin discovered that we have wrong address computation
for JALR instruction (the initial bug is back in 2018). This commit also
fixes that based on the idea of Palmer Dabbelt.
gas/
pr29342
* testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix.
* testsuite/gas/riscv/dis-addr-overflow.s: New testcase.
* testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.
opcodes/
pr29342
* riscv-dis.c (maybe_print_address): Fit address into 32-bit on RV32.
(print_insn_args): Fix JALR address by adding EXTRACT_ITYPE_IMM.
Address sequences involving ADDIW/C.ADDIW instructions require special
handling to sign-extend lower 32-bits of the original result.
This commit tests whether this sign-extension works.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw.s: New to test the address
computation with sign extension as used in ADDIW/C.ADDIW.
* testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0.
* testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw-a.d: New test.
* testsuite/gas/riscv/dis-addr-addiw-b.d: New test.
* testsuite/gas/riscv/dis-addr-addiw.s: New test.
The commit bf11021653 "* MAINTAINERS: Perform some obvious fixups."
back in 2009 changed the mailing list address gdb-patches@sources.redhat.com
to gdb-patches@sourceware.org.
This commit does the same to sim/MAINTAINERS.
sim/ChangeLog:
* MAINTAINERS: Update mailing list address.
Change-Id: I56c6bf21a4bddfb35ffc3336ffcba7ff9b39926e
When running the gdb/configure script on ubuntu 22.04 with
python-3.10.4, I see:
checking for python... no
checking for python3... /usr/bin/python3
[...]/gdb/python/python-config.py:7: DeprecationWarning: The distutils package is deprecated and slated for removal in Python 3.12. Use setuptools or check PEP 632 for potential alternatives
from distutils import sysconfig
[...]/gdb/python/python-config.py:7: DeprecationWarning: The distutils.sysconfig module is deprecated, use sysconfig instead
from distutils import sysconfig
[...]/gdb/python/python-config.py:7: DeprecationWarning: The distutils package is deprecated and slated for removal in Python 3.12. Use setuptools or check PEP 632 for potential alternatives
from distutils import sysconfig
[...]/gdb/python/python-config.py:7: DeprecationWarning: The distutils.sysconfig module is deprecated, use sysconfig instead
from distutils import sysconfig
[...]/gdb/python/python-config.py:7: DeprecationWarning: The distutils package is deprecated and slated for removal in Python 3.12. Use setuptools or check PEP 632 for potential alternatives
from distutils import sysconfig
[...]/gdb/python/python-config.py:7: DeprecationWarning: The distutils.sysconfig module is deprecated, use sysconfig instead
from distutils import sysconfig
checking for python... yes
The distutils module is deprecated as per the PEP 632[1] and will be
removed in python-3.12.
This patch migrates gdb/python/python-config.py from distutils.sysconfig
to the sysconfig module[2].
The sysconfig module has has been introduced in the standard library in
python 3.2. Given that support for python < 3.2 has been removed by
edae3fd660: "gdb/python: remove Python 2 support", this patch does not
need to support both implementations for backward compatibility.
Tested on ubuntu-22.04 and ubuntu 20.04.
[1] https://peps.python.org/pep-0632/
[2] https://docs.python.org/3/library/sysconfig.html
Change-Id: Id0df2baf3ee6ce68bd01c236b829ab4c0a4526f6
PR mi/10347 points out that using interpreter-exec inside of a
"define" command will crash gdb. The bug here is that
gdb_setup_readline doesn't check for the case where instream==nullptr.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=10347
PR mi/15811 points out that "source"ing a file that uses
interpreter-exec will put gdb in a weird state, where the CLI stops
working. The bug is that tui_interp::suspend does not unregister the
event file descriptor.
The test case is from Andrew Burgess.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=15811
gdb_setup_readline makes new streams and assigns to the various stream
members of struct ui. However, these assignments cause the previous
values to leak. As far as I can, this code is simply unnecessary and
can be removed -- with the exception of the assignment to gdb_stdtarg,
which is not initialized anywhere else.
A few spots setting some gdb output stream variables have a "for
moment" comment. These comments aren't useful and I think the moment
has passed -- these are permanent now.
This changes gdb so that, if ui::input_fd is set to -1, then it will
not be registered with the event loop. This is useful for the DAP
support code I wrote, but as it turns out to also be useful to
Insight, it seems best to check it in separately.
First, some background on the RISC-V registers fflags, frm, and fcsr.
These three registers all relate to the floating-point status and
control mechanism on RISC-V. The fcsr is the floatint-point control
status register, and consists of two parts, the flags (bits 0 to 4)
and the rounding-mode (bits 5 to 7).
The fcsr register is just one of many control/status registers (or
CSRs) available on RISC-V. The fflags and frm registers are also
CSRs. These CSRs are aliases for the relevant parts of the fcsr
register. So fflags is an alias for bits 0 to 4 of fcsr, and frm is
an alias for bits 5 to 7 of fcsr.
This means that a user can change the floating-point rounding mode
either, by writing a complete new value into fcsr, or by writing just
the rounding mode into frm.
How this impacts on GDB is like this: a target description could,
legitimately include all three registers, fcsr, fflags, and frm. The
QEMU target currently does this, and this makes sense. The target is
emulating the complete system, and has all three CSRs available, so
why not tell GDB about this.
In contrast, the RISC-V native Linux target only has access to the
fcsr. This is because the ptrace data structure that the kernel uses
for reading and writing floating point state only contains a copy of
the fcsr, after all, this one field really contains both the fflags
and frm fields, so why carry around duplicate data.
So, we might expect that the target description for the RISC-V native
Linux GDB would only contain the fcsr register. Unfortunately, this
is not the case. The RISC-V native Linux target uses GDB's builtin
target descriptions by calling riscv_lookup_target_description, this
will then add an fpu feature from gdb/features/riscv, either
32bit-fpu.xml or 64bit-fpu.xml. The problem, is that these features
include an entry for fcsr, fflags, and frm. This means that GDB
expects the target to handle reading and writing these registers. And
the RISC-V native Linux target currently doesn't.
In riscv_linux_nat_target::store_registers and
riscv_linux_nat_target::fetch_registers only the fcsr register is
handled, this means that, for RISC-V native Linux, the fflags and frm
registers always show up as <unavailable> - they are present in the
target description, but the target doesn't know how to access the
registers.
A final complication relating to these floating pointer CSRs is which
target description feature the registers appear in.
These registers are CSRs, so it would seem sensible that these
registers should appear in the CSR target description feature.
However, when I first added RISC-V target description support, I was
using a RISC-V simulator that didn't support any CSRs other than the
floating point related ones. This simulator bundled all the float
related CSRs into the fpu target feature. This didn't feel completely
unreasonable to me, and so I had GDB check for these registers in
either target feature.
In this commit I make some changes relating to how GDB handles the
three floating point CSR:
1. Remove fflags and frm from 32bit-fpu.xml and 64bit-fpu.xml. This
means that the default RISC-V target description (which RISC-V native
FreeBSD), and the target descriptions created for RISC-V native Linux,
will not include these registers. There's nothing stopping some other
target (e.g. QEMU) from continuing to include all three of these CSRs,
the code in riscv-tdep.c continues to check for all three of these
registers, and will handle them correctly if they are present.
2. If a target supplied fcsr, but does not supply fflags and/or frm,
then RISC-V GDB will now create two pseudo registers in order to
emulate the two missing CSRs. These new pseudo-registers do the
obvious thing of just reading and writing the fcsr register.
3. With the new pseudo-registers we can no longer make use of the GDB
register numbers RISCV_CSR_FFLAGS_REGNUM and RISCV_CSR_FRM_REGNUM.
These will be the numbers used if the target supplies the registers in
its target description, but, if GDB falls back to using
pseudo-registers, then new, unique numbers will be used. To handle
this I've added riscv_gdbarch_tdep::fflags_regnum and
riscv_gdbarch_tdep::frm_regnum, I've then updated the RISC-V code to
compare against these fields.
When adding the pseudo-register support, it is important that the
pseudo-register numbers are calculated after the call to
tdesc_use_registers. This is because we don't know the total number
of physical registers until after this call, and the psuedo-register
numbers must follow on from the real (target supplied) registers.
I've updated some tests to include more testing of the fflags and frm
registers, as well as adding a new test.
This commit adds a new function to the target description API within
GDB. This new function is not used in this commit, but will be used
in the next commit, I'm splitting it out into a separate patch for
easier review.
What I want to do in the next commit is check to see if a target
description supplied a particular register, however, the register in
question could appear in one of two possible features.
The new function allows me to ask the tdesc_arch_data whether a
register was found and assigned a particular GDB register number once
all of the features have been checked. I think this is a much simpler
solution than adding code such that, while checking each feature, I
spot if the register I'm processing is the one I care about.
No tests here as the new code is not used, but this code will be
exercised in the next commit.
On RISC-V the FCSR (float control/status register) is split into two
parts, FFLAGS (the flags) and FRM (the rounding mode). Both of these
two fields are part of the FCSR register, but can also be accessed as
separate registers in their own right. And so, we have three separate
registers, $fflags, $frm, and $fcsr, with the last of these being the
combination of the first two.
Here's how the bits of FCSR are split between FRM and FFLAGS:
,--------- FFLAGS
|---|
76543210 <----- FCSR
|-|
'--------------FRM
Here's how GDB currently displays these registers:
(gdb) info registers $fflags $frm $fcsr
fflags 0x0 RD:0 NV:0 DZ:0 OF:0 UF:0 NX:0
frm 0x0 FRM:0 [RNE (round to nearest; ties to even)]
fcsr 0x0 RD:0 NV:0 DZ:0 OF:0 UF:0 NX:0 FRM:0 [RNE (round to nearest; ties to even)]
Notice the 'RD' field which is present in both $fflags and $fcsr.
This field contains the value of the FRM field, which makes sense when
displaying the $fcsr, but makes no sense when displaying $fflags, as
the $fflags doesn't include the FRM field.
Additionally, the $fcsr already includes an FRM field, so the
information in 'RD' is duplicated. Consider this:
(gdb) set $frm = 0x3
(gdb) info registers $fflags $frm $fcsr │
fflags 0x0 RD:0 NV:0 DZ:0 OF:0 UF:0 NX:0
frm 0x3 FRM:3 [RUP (Round up towards +INF)]
fcsr 0x60 RD:3 NV:0 DZ:0 OF:0 UF:0 NX:0 FRM:3 [RUP (Round up towards +INF)]
See how the 'RD' field in $fflags still displays 0, while the 'RD' and
'FRM' fields in $fcsr show the same information.
The first change I propose in this commit is to remove the 'RD'
field. After this change the output now looks like this:
(gdb) info registers $fflags $frm $fcsr
fflags 0x0 NV:0 DZ:0 OF:0 UF:0 NX:0
frm 0x0 FRM:0 [RNE (round to nearest; ties to even)]
fcsr 0x0 NV:0 DZ:0 OF:0 UF:0 NX:0 FRM:0 [RNE (round to nearest; ties to even)]
Next, I spotted that the text that goes along with the 'FRM' field was
not wrapped in the i18n markers for internationalisation, so I added
those.
Next, I spotted that:
(gdb) set $frm=0x7
(gdb) info registers $fflags $frm $fcsr
fflags 0x0 RD:0 NV:0 DZ:0 OF:0 UF:0 NX:0
frm 0x7 FRM:3 [RUP (Round up towards +INF)]
fcsr 0xe0 RD:7 NV:0 DZ:0 OF:0 UF:0 NX:0 FRM:3 [RUP (Round up towards +INF)]
Notice that despite being a 3-bit field, FRM masks to 2-bits.
Checking the manual I can see that the FRM field is 3-bits, and is
defined for all 8 values. That GDB masks to 2-bits is just a bug I
think, so I've fixed this.
Finally, the 'FRM' text for value 0x7 is wrong. Currently we use the
text 'dynamic rounding mode' for value 0x7. However, this is not
really correct.
A RISC-V instruction can either encode the rounding mode within the
instruction, or a RISC-V instruction can choose to use a global,
dynamic rounding mode.
So, for the rounding-mode field of an _instruction_ the value 0x7
indicates "dynamic round mode", the instruction should defer to the
rounding mode held in the FRM field of the $fcsr.
But it makes no sense for the FRM of $fcsr to itself be set to
0x7 (dynamic rounding mode), and indeed, section 11.2, "Floating-Point
Control and Status Register" of the RISC-V manual, says that a value
of 0x7 in the $fcsr FRM field is invalid, and if an instruction has
_its_ round-mode set to dynamic, and the FRM field is also set to 0x7,
then an illegal instruction exception is raised.
And so, I propose changing the text for value 0x7 of the FRM field to
be "INVALID[7] (Dynamic rounding mode)". We already use the text
"INVALID[5]" and "INVALID[6]" for the two other invalid fields,
however, I think adding the extra "Dynamic round mode" hint might be
helpful.
I've added a new test that uses 'info registers' to check what GDB
prints for the three registers related to this patch. There is one
slight oddity with this test - for the fflags and frm registers, the
test accepts both the "normal" output (as described above), but also
allows these registers to be reported as '<unavailable>'.
The reason why I accept <unavailable> is that currently, the RISC-V,
native Linux target advertises these registers in its target
description, but then doesn't support reading or writing of these
registers, this results in the registers being reported as
unavailable.
A later patch in this series will address this issue, and will remove
this check for <unavailable>.
The following GDB behavior was also reported as a GDB bug in
https://sourceware.org/bugzilla/show_bug.cgi?id=28396
I will reiterate the problem a bit and give some more information here.
This patch closes the above mentioned bug.
The DWARF 5 standard 2.23 'Template Parameters' reads:
A template type parameter is represented by a debugging information
entry with the tag DW_TAG_template_type_parameter. A template value
parameter is represented by a debugging information entry with the tag
DW_TAG_template_value_parameter. The actual template parameter entries
appear in the same order as the corresponding template formal
parameter declarations in the source progam.
A type or value parameter entry may have a DW_AT_name attribute, whose
value is a null-terminated string containing the name of the
corresponding formal parameter.
So the DW_AT_name attribute for DW_TAG_template_type_parameter and
DW_TAG_template_value_parameter is optional.
Within GDB, creating a new symbol from some read DIE usually requires the
presence of a DW_AT_name for the DIE (an exception here is the case of
unnamed namespaces or the existence of a linkage name).
This patch makes the presence of the DW_AT_name for template value/type
tags optional, similar to the unnamed namespaces.
For unnamed namespaces dwarf2_name simply returns the constant string
CP_ANONYMOUS_NAMESPACE_STR '(anonymous namespace)'. For template tags a
case was added to the switch statement calling the
unnamed_template_tag_name helper. Within the scope of parent which
the template parameter is a child of, the helper counts the position
of the template tag within the unnamed template tags and returns
'<unnamedNUMBER>' where NUMBER is its position. This way we end up with
unique names within the respective scope of the function/class/struct
(these are the only currenltly supported template kinds within GDB and
usually the compilers) where we discovered the template tags in.
While I do not know of a way to bring GCC to emit template tags without
names there is one for clang/icpx. Consider the following example
template<typename A, typename B, typename C>
class Foo {};
template<typename, typename B, typename>
class Foo;
int main () {
Foo<double, int, float> f;
return 0;
}
The forward declaration for 'Foo' with the missing template type names
'A' and 'C' makes clang emit a bunch of template tags without names:
...
<2><43>: Abbrev Number: 3 (DW_TAG_variable)
<44> DW_AT_location : 2 byte block: 91 78 (DW_OP_fbreg: -8)
<47> DW_AT_name : (indirect string, offset: 0x63): f
<4b> DW_AT_decl_file : 1
<4c> DW_AT_decl_line : 8
<4d> DW_AT_type : <0x59>
...
<1><59>: Abbrev Number: 5 (DW_TAG_class_type)
<5a> DW_AT_calling_convention: 5 (pass by value)
<5b> DW_AT_name : (indirect string, offset: 0x74): Foo<double, int, float>
<5f> DW_AT_byte_size : 1
<60> DW_AT_decl_file : 1
<61> DW_AT_decl_line : 2
<2><62>: Abbrev Number: 6 (DW_TAG_template_type_param)
<63> DW_AT_type : <0x76>
<2><67>: Abbrev Number: 7 (DW_TAG_template_type_param)
<68> DW_AT_type : <0x52>
<6c> DW_AT_name : (indirect string, offset: 0x6c): B
<2><70>: Abbrev Number: 6 (DW_TAG_template_type_param)
<71> DW_AT_type : <0x7d>
...
Befor this patch, GDB would not create any symbols for the read template
tag DIEs and thus lose knowledge about them. Breaking at the return
statement and printing f's type would read
(gdb) ptype f
type = class Foo<double, int, float> [with B = int] {
<no data fields>
}
After this patch GDB does generate symbols from the DWARF (with their
artificial names:
(gdb) ptype f
type = class Foo<double, int, float> [with <unnamed0> = double, B = int,
<unnamed1> = float] {
<no data fields>
}
The same principle theoretically applies to template functions. Also
here, GDB would not record unnamed template TAGs but I know of no visual
way to trigger and test this changed behavior. Template functions do
not emit a '[with...]' list and their name generation also does not
suffer from template tags without names. GDB does not check whether or
not a template tag has a name in 'dwarf2_compute_name' and thus, the
names of the template functions are created independently of whether or
not the template TAGs have a DW_TAT_name attribute. A testcase has
been added in the gdb.dwarf2 for template classes and structs.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=28396
When writing a dwarf testcase for some C++ code I wanted to use the
MACRO_AT_range which in turn uses the function_range proc in dwarf.exp
to extract the bounds of 'main'.
However, the macro failed as GDB prints the C++ 'main' with its
arguments as 'main(int, char**)' or 'main()'.
The reason for this is that in read.c::dwarf2_compute_name we call
c_type_print_args on C++ functions and append their arguments to the
function name. This happens to all C++ functions, but is only visible
when the function doesn't have a linkage name.
An example might make this more clear. Given the following code
>> cat c.cpp
int foo (int a, float b)
{
return 0;
}
int main (int argc, char **argv)
{
return 0;
}
which is legal in both languages, C and C++, and compiling it with
e.g. clang or gcc will make the disassemble command look like:
>> clang --version
clang version 10.0.0-4ubuntu1
...
>> clang -O0 -g ./c.cpp
>> gdb -q ./a.out -ex "start"
...
(gdb) disassemble main
Dump of assembler code for function main(int, char**):
0x0000000000401120 <+0>: push %rbp
0x0000000000401121 <+1>: mov %rsp,%rbp
...
0x0000000000401135 <+21>: ret
End of assembler dump.
(gdb) disassemble foo
Dump of assembler code for function _Z3fooif:
0x0000000000401110 <+0>: push %rbp
0x0000000000401111 <+1>: mov %rsp,%rbp
...
0x000000000040111f <+15>: ret
End of assembler dump.
Note, that main is emitted with its arguments while for foo the linkage
name is being printed, as also visible in its DWARF:
>> objdump ./a.out --dwarf=info | grep "foo" -A3 -B3
<2b> DW_AT_low_pc : 0x401110
<33> DW_AT_high_pc : 0x10
<37> DW_AT_frame_base : 1 byte block: 56 (DW_OP_reg6 (rbp))
<39> DW_AT_linkage_name: (indirect string, offset: 0x39): _Z3fooif
<3d> DW_AT_name : (indirect string, offset: 0x42): foo
<41> DW_AT_decl_file : 1
<42> DW_AT_decl_line : 1
<43> DW_AT_type : <0x9a>
Now, let's rename the C++ file and compile it as C:
>> mv c.cpp c.c
>> clang -O0 -g ./c.c
>> gdb -q ./a.out -ex "start'
...
(gdb) disassemble main
Dump of assembler code for function main:
0x0000000000401120 <+0>: push %rbp
0x0000000000401121 <+1>: mov %rsp,%rbp
...
0x0000000000401135 <+21>: ret
End of assembler dump.
(gdb) disassemble foo
Dump of assembler code for function foo:
0x0000000000401110 <+0>: push %rbp
0x0000000000401111 <+1>: mov %rsp,%rbp
...
0x000000000040111f <+15>: ret
End of assembler dump.
Note, for foo we did not get a linkage name emitted in DWARF, so
it is printed by its name:
>> objdump --dwarf=info ./a.out | grep foo -A3 -B3
<2b> DW_AT_low_pc : 0x401110
<33> DW_AT_high_pc : 0x10
<37> DW_AT_frame_base : 1 byte block: 56 (DW_OP_reg6 (rbp))
<39> DW_AT_name : (indirect string, offset: 0x37): foo
<3d> DW_AT_decl_file : 1
<3e> DW_AT_decl_line : 1
<3f> DW_AT_prototyped : 1
To make the macro and proc work with C++ as well, an optional argument
list was added to the regex matching the function name in the
disassemble command in function_range. This does not change any used
behavior as currently, there exists no C++ test using the proc
function_range.
Signed-off-by: Nils-Christian Kempke <nils-christian.kempke@intel.com>
The call to debuginfod_debuginfo_query in elf_symfile_read is given
objfile->original_name as the filename to print when downloading the
objfile's debuginfo.
In some cases original_name is prefixed with gdb's working directory
even though the objfile is not located in the working directory. This
causes debuginfod to display the wrong path of the objfile during a download.
Fix this by using the objfile's bfd filename instead.
Initially, since c6c37250e9 (in 1999),
in order to fix linking against Microsoft import libraries, ld did
internally rename members of such libraries. At that point, the
criteria for being considered a Microsoft import library was that
every archive member had the same name (no regard for exactly what
that name was).
This was later amended in 44dbf3639f
(in 2003) to allow for Microsoft import libraries with intermixed
static object files. At this point, the criteria were extended, so
that all members following the first member named *.dll either had
the exact same member name, or be named *.obj. (Curiously, this would
allow members with any name if it precedes the first one named *.dll.)
In practice, Microsoft style import libraries can contain
members for linking against more than one DLL (built by merging
multiple regular import libraries into one).
Instead of trying to do validation of the whole archive before
considering it a Microsoft style import library, relax the criteria
for doing the member renaming: If an archive member is named *.dll
and it contains .idata sections, assume that that member is a
Microsoft import file, and apply the renaming scheme.
This works for imports for any number of DLLs in the same library,
intermixed with other static object files (regardless of their
names), and vastly simplifies the code.
LLVM generates Microsoft style import libraries, and Rust builds
seem to bundle up multiple import libraries together with some
Rust specific static objects. This fixes linking directly against
them with ld.bfd.
When building with Clang 14 (using gcc 12 libstdc++ headers), I get:
CXX dwarf2/read.o
In file included from /home/simark/src/binutils-gdb/gdb/dwarf2/read.c:94:
/home/simark/src/binutils-gdb/gdb/../gdbsupport/parallel-for.h:142:21: error: 'result_of<(lambda at /home/simark/src/binutils-gdb/gdb/dwarf2/read.c:7124:5) (__gnu_debug::_Safe_iterator<__gnu_cxx::__normal_iterator<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter> *, std::__cxx1998::vector<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter>>>, std::vector<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter>>, std::random_access_iterator_tag>, __gnu_debug::_Safe_iterator<__gnu_cxx::__normal_iterator<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter> *, std::__cxx1998::vector<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter>>>, std::vector<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter>>, std::random_access_iterator_tag>)>' is deprecated: use 'std::invoke_result' instead [-Werror,-Wdeprecated-declarations]
= typename std::result_of<RangeFunction (RandomIt, RandomIt)>::type;
^
/home/simark/src/binutils-gdb/gdb/dwarf2/read.c:7122:14: note: in instantiation of function template specialization 'gdb::parallel_for_each<__gnu_debug::_Safe_iterator<__gnu_cxx::__normal_iterator<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter> *, std::__cxx1998::vector<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter>>>, std::vector<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter>>, std::random_access_iterator_tag>, (lambda at /home/simark/src/binutils-gdb/gdb/dwarf2/read.c:7124:5)>' requested here
= gdb::parallel_for_each (1, per_bfd->all_comp_units.begin (),
^
/usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/12.1.1/../../../../include/c++/12.1.1/type_traits:2597:9: note: 'result_of<(lambda at /home/simark/src/binutils-gdb/gdb/dwarf2/read.c:7124:5) (__gnu_debug::_Safe_iterator<__gnu_cxx::__normal_iterator<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter> *, std::__cxx1998::vector<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter>>>, std::vector<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter>>, std::random_access_iterator_tag>, __gnu_debug::_Safe_iterator<__gnu_cxx::__normal_iterator<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter> *, std::__cxx1998::vector<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter>>>, std::vector<std::unique_ptr<dwarf2_per_cu_data, dwarf2_per_cu_data_deleter>>, std::random_access_iterator_tag>)>' has been explicitly marked deprecated here
{ } _GLIBCXX17_DEPRECATED_SUGGEST("std::invoke_result");
^
/usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/12.1.1/../../../../include/c++/12.1.1/x86_64-pc-linux-gnu/bits/c++config.h:120:45: note: expanded from macro '_GLIBCXX17_DEPRECATED_SUGGEST'
# define _GLIBCXX17_DEPRECATED_SUGGEST(ALT) _GLIBCXX_DEPRECATED_SUGGEST(ALT)
^
/usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/12.1.1/../../../../include/c++/12.1.1/x86_64-pc-linux-gnu/bits/c++config.h:96:19: note: expanded from macro '_GLIBCXX_DEPRECATED_SUGGEST'
__attribute__ ((__deprecated__ ("use '" ALT "' instead")))
^
It complains about the use of std::result_of, which is deprecated in
C++17 and removed in C++20:
https://en.cppreference.com/w/cpp/types/result_of
Given we'll have to transition to std::invoke_result eventually, make a
GDB wrapper to mimimc std::invoke_result, which uses std::invoke_result
for C++ >= 17 and std::result_of otherwise. This way, it will be easy
to remove the wrapper in the future, just replace gdb:: with std::.
Tested by building with gcc 12 in -std=c++11 and -std=c++17 mode, and
clang in -std=c++17 mode (I did not test fully with clang in -std=c++11
mode because there are other unrelated issues).
Change-Id: I50debde0a3307a7bc67fcf8fceefda51860efc1d
GDB overwrites Python's sys.stdout and sys.stderr, but does not
properly implement the 'flush' method -- it only ever will flush
stdout. This patch fixes the bug. I couldn't find a straightforward
way to write a test for this.
PR 29529
* dwarf2.c (struct line_info_table): Add new field:
use_dir_and_file_0.
(concat_filename): Use new field to help select the correct table
slot.
(read_formatted_entries): Do not skip entry 0.
(decode_line_info): Set new field depending upon the version of
DWARF being parsed. Initialise filename based upon the setting of
the new field.
The print_one_detail_ranged_breakpoint has been renamed to
ranged_breakpoint::print_one_detail in this commit:
commit ec45bb676c
Date: Sat Jan 15 16:34:51 2022 -0700
Convert ranged breakpoints to vtable ops
So their comments should be updated as well.
Running configure and make in binutils-gdb.
$ ./configure
$ make
In file included from ./as.h:37,
from ./config/loongarch-lex.l:21,
from config/loongarch-lex-wrapper.c:20:
./config.h:206: error: “PACKAGE” redefined [-Werror]
#define PACKAGE "gas"
...
gas/config
* loongarch-lex-wrapper.c
Three-part patch set from Tsukasa OI to support zmmul in assembler.
The 'Zmmul' is a RISC-V extension consisting of only multiply instructions
(a subset of 'M' which has multiply and divide instructions).
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'.
(riscv_supported_std_z_ext): Add 'Zmmul' extension.
(riscv_multi_subset_supports): Add handling for new instruction class.
gas/
* testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'.
* testsuite/gas/riscv/option-arch-02.d: Likewise.
* testsuite/gas/riscv/m-ext.s: New test.
* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
* testsuite/gas/riscv/zmmul-32.d: New expected output.
* testsuite/gas/riscv/zmmul-64.d: Likewise.
* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
by using RV64-only instructions in RV32).
* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test
(RV32 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test
(RV64 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test
(no Zmmul or M).
* testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise.
include/
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in
these testcases, so just replaced m by a.
* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed.
opcodes/
* riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
When running the included test-case, we run into:
...
(gdb) break _start^M
read.h:309: internal-error: set_length: \
Assertion `m_length == length' failed.^M
...
The problem is that while there are two CUs:
...
$ readelf -wi debug-names-missing-cu | grep @
Compilation Unit @ offset 0x0:
Compilation Unit @ offset 0x2d:
...
the CU table in the .debug_names section only contains the first one:
...
CU table:
[ 0] 0x0
...
The incomplete CU table makes create_cus_from_debug_names_list set the size of
the CU at 0x0 to the actual size of both CUs combined.
This eventually leads to the assert, when we read the actual size from the CU
header.
While having an incomplete CU table in a .debug_names section is incorrect,
we need a better failure mode than asserting.
The easiest way to fix this is to set the length to 0 (meaning: unkown) in
create_cus_from_debug_names_list.
This makes the failure mode to accept the incomplete CU table, but to ignore
the missing CU.
It would be nice to instead reject the .debug_names index, and build a
complete CU list, but the point where we find this out is well after
dwarf2_initialize_objfile, so it looks rather intrusive to restart at that
point.
Tested on x86_64-linux.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29453
I tried out the script gdb/gdb_mbuild.sh, and ran into:
...
score-elf ...
... configure --target=score-elf
... make score-elf
... run score-elf
score-elf: gdb dumped core
Terminated
...
Gdb runs into this internal error in initialize_current_architecture:
...
if (! gdbarch_update_p (info))
internal_error (__FILE__, __LINE__,
_("initialize_current_architecture: Selection of "
"initial architecture failed"));
...
The call to gdbarch_update_p fails because commit 575b4c298a ("gdb: Remove
support for S+core") removed support for the architecture.
Fix this by adding score-*-* to the list of obsolete targets in
gdb/configure.tgt, such that we're no longer able to build the configuration:
...
*** Configuration score-unknown-elf is obsolete.
*** Support has been REMOVED.
make: *** [Makefile:12806: configure-gdb] Error 1
...
Also remove the related line from the "Target Instruction Set Architectures"
list in gdb/MAINTAINERS, such that gdb/gdb_mbuild.sh no longer tries to build
it.
