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8248 Commits

Author SHA1 Message Date
Alan Modra
e21126b7b3 Documentation fix 
PR 22544
	* doc/as.texinfo (8byte): Correct.
 2017-12-04 22:26:32 +10:30
Alan Modra
48f7f3036a Run powerpc vle gas tests for all powerpc ELF targets 
* testsuite/gas/ppc/ppc.exp: Don't exclude VLE tests when little-endian.
	* testsuite/gas/ppc/efs.d: Add -mbig to assembler options.
	* testsuite/gas/ppc/efs2.d: Likewise.
	* testsuite/gas/ppc/lsp-checks.d: Likewise.
	* testsuite/gas/ppc/lsp.d: Likewise.
	* testsuite/gas/ppc/spe.d: Likewise.
	* testsuite/gas/ppc/spe2-checks.d: Likewise.
	* testsuite/gas/ppc/spe2.d: Likewise.
	* testsuite/gas/ppc/spe_ambiguous.d: Likewise.
	* testsuite/gas/ppc/vle-mult-ld-st-insns.d: Likewise.
	* testsuite/gas/ppc/vle-reloc.d: Likewise.
	* testsuite/gas/ppc/vle-simple-1.d: Likewise.
	* testsuite/gas/ppc/vle-simple-2.d: Likewise.
	* testsuite/gas/ppc/vle-simple-3.d: Likewise.
	* testsuite/gas/ppc/vle-simple-4.d: Likewise.
	* testsuite/gas/ppc/vle-simple-5.d: Likewise.
	* testsuite/gas/ppc/vle-simple-6.d: Likewise.
	* testsuite/gas/ppc/vle.d: Likewise.
 2017-12-04 10:23:57 +10:30
Jim Wilson
fed44c60b3 Fix for texinfo 4.8. 
gas/
	* doc/c-riscv.texi (RISC-V-Directives): Move @section immediately after
	@node.
 2017-12-03 15:14:11 -08:00
Jim Wilson
b57e49f726 Update and clean up RISC-V gas documentation. 
gas/
	* doc/as.texinfo (RISC-V): Alphabetize RISC-V entries.  Change
	RISC-V-Opts to RISC-V-Options.  Delete redundant space.  Add -fpic
	and related options to option list.
	* doc/c-riscv.texi: (RISC-V-Options): Renamed from RISC-V-Opts.
	(RISC-V Options): Renamed from Options.  Add missing period.
	(-fpic): Also mention -fPIC.
	(RISC-V Directives): New node.
 2017-12-01 15:34:42 -08:00
Peter Bergner
0f873fd58b Use consistent types for holding instructions, instruction masks, etc. 
include/
	* opcode/ppc.h (PPC_INT_FMT): Define.
	(struct powerpc_opcode) <opcode>: Update type.
	(struct powerpc_opcode) <mask>: Likewise.
	(struct powerpc_opcode) <bitm>: Likewise.
	(struct powerpc_opcode) <insert>: Likewise.
	(struct powerpc_opcode) <extract>: Likewise.
	(ppc_optional_operand_value): Likewise.

gas/
	* config/tc-ppc.c (last_insn): Update type.
	(insn_validate) <omask, mask>: Likewise.
	(ppc_setup_opcodes) <mask, right_bit>: Likewise.
	<PRINT_OPCODE_TABLE>: Update types and printf format specifiers.
	(ppc_insert_operand): Update return and argument types and remove
	unneeded type casts.
	<min, max, right, tmp>: Update type.
	(md_assemble): Remove unneeded type casts.
	<insn, val, tmp_insn>: Update type.

opcodes/
	* opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
	(operand_value_powerpc): Update return and argument type.
	<value, top>: Update type.
	(skip_optional_operands): Update argument type.
	(lookup_powerpc): Likewise.
	(lookup_vle): Likewise.
	<table_opcd, table_mask, insn2>: Update type.
	(lookup_spe2): Update argument type.
	<table_opcd, table_mask, insn2>: Update type.
	(print_insn_powerpc) <insn, value>: Update type.
	Use PPC_INT_FMT for printing instructions and operands.
	* opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
	insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
	insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
	extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
	extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
	insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
	extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
	insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
	extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
	insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
	extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
	insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
	extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
	insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
	extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
	insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
	extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
	insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
	extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
	extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
	extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
	insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
	extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
	insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
	extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
	extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
	(OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
	BD24, BBO, Y_MASK  , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
	DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
	SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
	VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
	VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
	VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
	XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
	XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
	XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
	XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
 2017-12-01 11:20:15 -06:00
Jan Beulich
b5014f7af2 x86: drop Vec_Disp8 
This is fully redundant with Disp8MemShift being non-zero, and hence can
be folded with normal Disp8 handling.
 2017-11-30 11:47:38 +01:00
Jan Beulich
fd4e034759 x86/Intel: issue diagnostics for redundant segment override prefixes 
While we shouldn't outright reject such (as was wrongly done by commit
4d36230d59 ("x86: Update segment register check in Intel syntax"), as
MASM accepts them even silently, issue (by default) a warning for such
questionable constructs.
 2017-11-30 11:46:26 +01:00
Jan Beulich
e21440ba62 Revert "x86: Update segment register check in Intel syntax" 
This reverts commit 4d36230d59.
I was committed without maintainer ack and regresses intended
functionality. A replacement will be committed shortly.
 2017-11-30 11:44:27 +01:00
Jim Wilson
6cf829987c Give Palmer co-credit for last patch. 2017-11-29 10:51:36 -08:00
Jim Wilson
36877bfb88 Fix riscv malloc error on small alignment after norvc. 
gas/
	* config/tc-riscv.c (riscv_frag_align_code): New local insn_alignment.
	Early return if bytes less than or equal to insn_alignment.
	* testsuite/gas/riscv/align-1.l: New.
	* testsuite/gas/riscv/align-1.s: New.
	* testsuite/gas/riscv/riscv.exp: Use run_dump_tests.  Use run_list_test
	for align-1.
 2017-11-29 10:36:46 -08:00
Jim Wilson
f923328821 In x86 -n docs, mention that you need an explicit nop fill byte. 
gas/
	PR gas/22464
	* doc/c-i386.texi (-n): Clarify docs.
 2017-11-29 10:22:26 -08:00
Renlin Li
f10e937a1c [GAS][AARCH64]Fix a typo for IP1 register alias. 
This should be an obvious fix.
It corrects the register number for IP1 to 17.

gas/

2017-11-29  Renlin Li  <renlin.li@arm.com>

	* config/tc-aarch64.c (reg_names): Fix IP1 register alias error.
	* testsuite/gas/aarch64/register_aliases.s: Add IP0 and IP1 tests.
	* testsuite/gas/aarch64/register_aliases.d: Update.
 2017-11-29 17:19:59 +00:00
Stefan Stroe
ca39c2f4dd Support --localedir, --datarootdir and --datadir 
bfd/
	* po/Make-in (datadir): Define as @datadir@.
	(localedir): Define as @localedir@.
	(gnulocaledir, gettextsrcdir): Use @datarootdir@.
binutils/
	* po/Make-in (datadir): Define as @datadir@.
	(localedir): Define as @localedir@.
	(gnulocaledir, gettextsrcdir): Use @datarootdir@.
gas/
	* po/Make-in (datadir): Define as @datadir@.
	(localedir): Define as @localedir@.
	(gnulocaledir, gettextsrcdir): Use @datarootdir@.
gold/
	* po/Make-in (datadir): Define as @datadir@.
	(localedir): Define as @localedir@.
	(gnulocaledir, gettextsrcdir): Use @datarootdir@.
gprof/
	* po/Make-in (datadir): Define as @datadir@.
	(localedir): Define as @localedir@.
	(gnulocaledir, gettextsrcdir): Use @datarootdir@.
ld/
	* po/Make-in (datadir): Define as @datadir@.
	(localedir): Define as @localedir@.
	(gnulocaledir, gettextsrcdir): Use @datarootdir@.
opcodes/
	* po/Make-in (datadir): Define as @datadir@.
	(localedir): Define as @localedir@.
	(gnulocaledir, gettextsrcdir): Use @datarootdir@.
 2017-11-29 20:10:52 +10:30
Nick Clifton
ed9c7ee037 Use the record_alignment function when creating a .note section, in case the user has already created the section. 
PR 22492
	* config/obj-elf.c (obj_elf_version): Use record_alignment rather
	than bfd_set_section_alignment.
 2017-11-29 09:32:49 +00:00
Jim Wilson
f0531ed6a4 Compress loads/stores with implicit 0 offset. 
gas/
	* config/tc-riscv.c (riscv_handle_implicit_zero_offset): New.
	(riscv_ip): Cases 'k', 'l', 'm', 'n', 'M', 'N', add call to
	riscv_handle_implicit_zero_offset.  At label load_store, replace
	existing code with call to riscv_handle_implicit_zero_offset.
	* testsuite/gas/riscv/c-ld.d, testsuite/gas/riscv/c-ld.s: New.
	* testsuite/gas/riscv/c-lw.d, testsuite/gas/riscv/c-lw.s: New.
	* testsuite/gas/riscv/riscv.exp: Run new tests.
 2017-11-27 19:20:53 -08:00
Max Filippov
407e114084 gas: xtensa: speed up find_trampoline_seg 
find_trampoline_seg takes noticeable time when assembling source with
many sections. Cache the result of the most recent search and check it
first. No functional changes.

gas/
2017-11-27  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (find_trampoline_seg): Add static variable
	that caches the result of the most recent search.
 2017-11-27 15:16:22 -08:00
Max Filippov
148d638429 gas: xtensa: implement trampoline coalescing 
There is a recurring pattern in assembly files generated by a compiler
where a lot of jumps in a function are going to the same place. When
these jumps are relaxed with trampolines the assembler generates a
separate jump thread from each source.
Create an index of trampoline jump targets for each segment and see if a
jump being relaxed goes to a location from that index, in which case
replace its target with a location of existing trampoline jump that
results in the shortest path to the original target.

gas/
2017-11-27  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (trampoline_chain_entry, trampoline_chain)
	(trampoline_chain_index): New structures.
	(trampoline_index): Add chain_index field.
	(xg_order_trampoline_chain_entry, xg_sort_trampoline_chain)
	(xg_find_chain_entry, xg_get_best_chain_entry)
	(xg_order_trampoline_chain, xg_get_trampoline_chain)
	(xg_find_best_eq_target, xg_add_location_to_chain)
	(xg_create_trampoline_chain, xg_get_single_symbol_slot): New
	functions.
	(xg_relax_fixups): Call xg_find_best_eq_target to adjust jump
	target to point to an existing jump. Call
	xg_create_trampoline_chain to create new jump target. Call
	xg_add_location_to_chain to add newly created trampoline jump
	to the corresponding chain.
	(add_jump_to_trampoline): Extract loop searching for a single
	slot with a symbol into a separate function, replace that code
	with a call to that function.
	(relax_frag_immed): Call xg_find_best_eq_target to adjust jump
	target to point to an existing jump.
	* testsuite/gas/xtensa/all.exp: Add trampoline-2 test.
	* testsuite/gas/xtensa/trampoline.d: Adjust absolute addresses
	as many duplicate trampoline chains are now coalesced.
	* testsuite/gas/xtensa/trampoline.s: Add _nop so that objdump
	stays in sync with instruction stream.
	* testsuite/gas/xtensa/trampoline-2.l: New test result file.
	* testsuite/gas/xtensa/trampoline-2.s: New test source file.
 2017-11-27 15:15:46 -08:00
Max Filippov
76a493ab99 gas: xtensa: reuse trampoline placement code 
There's almost exact copy of the trampoline placement code in the
search_trampolines function that is used for jumps generated for relaxed
branch instructions. Get rid of the duplication and reuse
xg_find_best_trampoline function for that.

gas/
2017-11-27  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (search_trampolines, get_best_trampoline):
	Remove definitions.
	(xg_find_best_trampoline_for_tinsn): New function.
	(relax_frag_immed): Replace call to get_best_trampoline with a
	call to xg_find_best_trampoline_for_tinsn.
	* testsuite/gas/xtensa/trampoline.d: Adjust absolute addresses
	as the placement of trampolines for relaxed branches has been
	changed.
 2017-11-27 15:14:48 -08:00
Max Filippov
fe6c2f1b64 gas: xtensa: rewrite xg_relax_trampoline 
Replace linked list of trampoline frags with an ordered array, so that
instead of indexing fixups trampolines could be indexed. Keep each array
in the trampoline_seg structure, so there's no need to rebuild it for
every new processed segment. Don't run relaxation for each trampoline
frag, instead run it for each fixup in the current segment that needs
relaxation at the beginning of each relaxation pass. This way the
complexity of this process drops from about O(n^2 * m) to about
O(log n * m), where n is the number of trampoline frags and m is the
number of fixups that need relaxation in the segment.

gas/
2017-11-27  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (trampoline_index): New structure.
	(trampoline_seg): Replace trampoline list with trampoline index.
	(xg_find_trampoline, xg_add_trampoline_to_index)
	(xg_remove_trampoline_from_index, xg_add_trampoline_to_seg)
	(xg_is_trampoline_frag_full, xg_get_fulcrum)
	(xg_find_best_trampoline, xg_relax_fixup, xg_relax_fixups)
	(xg_is_relaxable_fixup): New functions.
	(J_MARGIN): New macro.
	(xtensa_create_trampoline_frag): Use xg_add_trampoline_to_seg
	instead of open-coded addition to the linked list.
	(dump_trampolines): Iterate through the trampoline_seg::index.
	(cached_fixupS, cached_fixup, fixup_cacheS, fixup_cache)
	(fixup_order, xtensa_make_cached_fixup)
	(xtensa_realloc_fixup_cache, xtensa_cache_relaxable_fixups)
	(xtensa_find_first_cached_fixup, xtensa_delete_cached_fixup)
	(xtensa_add_cached_fixup, check_and_update_trampolines): Remove
	definitions.
	(xg_relax_trampoline): Extract logic into separate functions,
	replace body with a call to xg_relax_fixups.
	(search_trampolines): Replace search in linked list with search
	in index. Change data type of address-tracking variables from
	int to offsetT. Replace abs with labs.
	(xg_append_jump): Finish the trampoline frag if it's full.
	(add_jump_to_trampoline): Remove trampoline frag from the index
	if the frag is full.
	* config/tc-xtensa.h (xtensa_frag_type): Remove next_trampoline.
	* testsuite/gas/xtensa/trampoline.d: Adjust absolute addresses
	as the placement of trampolines has slightly changed.
	* testsuite/gas/xtensa/trampoline.s: Add _nop so that objdump
	stays in sync with instruction stream.
 2017-11-27 15:13:52 -08:00
Max Filippov
46888d7100 gas: xtensa: merge trampoline_frag into xtensa_frag_type 
The split between fragS and trampoline_frag doesn't save much space, but
makes trampolines management much more awkward. Merge trampoline_frag
data into the xtensa_frag_type, which is a part of fragS. No functional
changes.

gas/
2017-11-27  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (init_trampoline_frag): Replace pointer to
	struct trampoline_frag parameter with pointer to fragS.
	(xg_append_jump): Remove jump_around parameter.
	(struct trampoline_frag): Remove.
	(struct trampoline_seg): Change type of trampoline_list from
	struct trampoline_frag to fragS.
	(xtensa_create_trampoline_frag): Don't allocate struct
	trampoline_frag. Initialize new fragS::tc_frag_data fields.
	(dump_trampolines, xg_relax_trampoline, search_trampolines)
	(get_best_trampoline, init_trampoline_frag)
	(add_jump_to_trampoline, relax_frag_immed): Replace pointer to
	struct trampoline_frag with a pointer to fragS.
	(xg_append_jump): Remove jump_around parameter, use
	fragS::tc_frag_data.jump_around_fix instead.
	(xg_relax_trampoline, init_trampoline_frag)
	(add_jump_to_trampoline): Don't pass jump_around parameter to
	xg_append_jump.
	* config/tc-xtensa.h (struct xtensa_frag_type): Add new fields:
	needs_jump_around, next_trampoline and jump_around_fix.
 2017-11-27 15:13:00 -08:00
Max Filippov
1c2649f50f gas: xtensa: reuse find_trampoline_seg 
xtensa_create_trampoline_frag has opencoded fragment equivalent to
find_trampoline_seg. Drop the fragment and use find_trampoline_seg
instead. No functional changes.

gas/
2017-11-27  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (find_trampoline_seg): Move above the first
	use.
	(xtensa_create_trampoline_frag): Replace trampoline seg search
	code with a call to find_trampoline_seg.
 2017-11-27 15:12:21 -08:00
Max Filippov
fec68fb168 gas: xtensa: extract jump assembling for trampolines 
init_trampoline_frag, add_jump_to_trampoline and xg_relax_trampoline add
a jump to the end of a trampoline frag. Extract it into a separate
funciton and use it in all these places. No functional changes.

gas/
2017-11-27  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (xg_append_jump): New function.
	(xg_relax_trampoline, init_trampoline_frag)
	(add_jump_to_trampoline): Replace trampoline jump assembling
	code with a call to xg_append_jump.
 2017-11-27 15:11:38 -08:00
Max Filippov
120bc8b8b9 gas: extract xg_relax_trampoline from xtensa_relax_frag 
To make measurement and changes easier extract trampoline relaxation
function. No functional changes.

gas/
2017-11-27  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (xg_relax_trampoline): New function.
	(xtensa_relax_frag): Replace trampoline relaxation code with a
	call to xg_relax_trampoline.
 2017-11-27 15:10:49 -08:00
Nick Clifton
e3d4058216 When creating a .note section to contain a version note, set the section alignment to 4 bytes. 
PR 22492
	* config/obj-elf.c (obj_elf_version): Set the alignment of the
	.note section.
 2017-11-27 11:04:17 +00:00
H.J. Lu
8e2495f2f7 gas: Update x86 sse-noavx tests 
This fixed:

FAIL: i386 SSE without AVX equivalent
FAIL: x86-64 SSE without AVX equivalent
FAIL: x86-64 (ILP32) SSE without AVX equivalent

on x86-64.

	* testsuite/gas/i386/sse-noavx.s: Add tests for fisttps and
	fisttpl.
	* testsuite/gas/i386/x86-64-sse-noavx.s: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-sse-noavx.d: Updated.
	* testsuite/gas/i386/sse-noavx.d: Likewise.
	* testsuite/gas/i386/x86-64-sse-noavx.d: Likewise.
 2017-11-26 08:32:26 -08:00
Jim Wilson
0fbc35681f Add reference to implicit use in _bfd_elf_is_local_label_name. 
gas/
	* write.h (FAKE_LABEL_CHAR): Expand comment.
 2017-11-24 09:31:59 -08:00
Jan Beulich
6d2cd6b208 x86: reject further invalid AVX-512 masking constructs 
For one the register type used for masking should be validated. And then
we shouldn't accept input producing encodings which will #UD when
executed, as is the case when EVEX.Z is set while EVEX.AAA is zero.
 2017-11-24 08:42:57 +01:00
Jan Beulich
ac465521a5 x86: don't omit disambiguating suffixes from "fi*" 
"fi*" typically come in two (loads/stores: three) flavors, distinguished
by the suffix. Don't omit the 's' one when disassembling.
 2017-11-24 08:42:04 +01:00
Jim Wilson
c139731b13 Fix vax/ns32k/mmix gas testsuite regression. 
gas/
	* testsuite/gas/all/err-fakelabel.s (dg-error): Also accept fatal error
	string.
 2017-11-23 13:11:40 -08:00
Jim Wilson
5f71e59e1a Fix build error with --enable-targets=all. 
gas/
	* as.c (INITIALIZING_EMULS): Define.
	* config/obj-multi.h (FAKE_LABEL_NAME): When INITIALIZING_EMULS set,
	don't define it.
 2017-11-23 12:30:47 -08:00
Igor Tsimbalist
be7d1531e1 Add Disp8MemShift for AVX512 VAES instructions. 
opcodes/
	* i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
	* i386-tbl.h: Regenerate.

gas/
	* testsuite/gas/i386/avx512f_vaes-intel.d: Regenerate.
	* testsuite/gas/i386/avx512f_vaes.d: Likewise.
	* testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Likewise.
	* testsuite/gas/i386/avx512f_vaes-wig1.d: Likewise.
	* testsuite/gas/i386/avx512vl_vaes-intel.d: Likewise.
	* testsuite/gas/i386/avx512vl_vaes.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_vaes.s: Add instructions with disp8*N.
	* testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Regenerate.
	* testsuite/gas/i386/x86-64-avx512f_vaes.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Add instructions with disp8*N.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Regenerate.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Regenerate.
	* testsuite/gas/i386/x86-64-avx512vl_vaes.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Add instructions with disp8*N.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Regenerate.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Regenerate.
 2017-11-23 18:25:49 +03:00
Jan Beulich
65f3ed048f x86: fix AVX-512 16-bit addressing 
Despite EVEX encodings not being available in real and VM86 modes,
16-bit addressing still needs to be handled properly for 16-bit
protected mode as well as 16-bit addressing in 32-bit mode. Neither
should displacements be dropped silently by the assembler, nor should
the disassembler fail to correctly scale 8-bit displacements.
 2017-11-23 11:04:18 +01:00
Jan Beulich
43083a502b x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base reg 
Except for %eip-relative addressing, where we don't have a suitable
relocation type silently wrapping at the 4G boundary, consistently
force use of R_X86_64_32 (in ELF terms) instead of its sign-extending
counterpart. This wasn't right in case there was no base register in
the addressing expression.
 2017-11-23 11:02:30 +01:00
Jan Beulich
9bb129e82f x86: drop redundant VSIB handling code 
The vecsib && !base_reg case is already being handled (in a more correct
manner) by earlier code.
 2017-11-23 11:00:44 +01:00
Jan Beulich
66f1eba0b7 x86: correct UDn 
Make the assembler recognize UD0, supporting only the newer form
expecting a ModR/M byte.

Make assembler and disassembler properly emit / expect a ModR/M byte for
UD1.

For the testsuite, as arch-4 already tests all UDn, avoid producing a
huge delta for other tests using UD2B by making them use UD2 instead.
 2017-11-23 10:59:48 +01:00
Jan Beulich
38bf51134d x86/Intel: don't report multiple errors for a single insn operand 
Multiple errors are more confusing than helpful, as the more generic
one often implies a sufficiently different adjustment than would
actually be needed to fix the code. Additionally it makes it more
cumbersome to add missing error checks, as the testsuite then needs
extra updating.
 2017-11-23 10:57:54 +01:00
Jim Wilson
2469b3c584 Riscv ld-elf/stab failure and fake label cleanup. 
* as.c: Include write.h.
	(common_emul_init): Use FAKE_LABEL_NAME.
	* ecoff.c (add_file, ecoff_directive_end, ecoff_directive_loc):
	Likewise.
	(ecoff_build_symbols): Use FAKE_LABEL_CHAR.
	* expr.c (get_symbol_name): Use FAKE_LABEL_CHAR.  Accept only if
	input_from_string is TRUE.
	* read.c (input_from_string): New.
	(read_symbol_name): Use FAKE_LABEL_CHAR.  Accept only if
	input_from_string is TRUE.
	(temp_ilp): Set input_from_string to TRUE.
	(restore_ilp): Set input_from_string to FALSE.
	* read.h (input_from_string): Declare.
	* symbols.c: Include write.h
	(S_IS_LOCAL): Check for FAKE_LABEL_CHAR.
	(symbol_relc_make_sym): Fix comment refering to default fake label
	string.
	* write.h (FAKE_LABEL_CHAR): New.
	* config/tc-riscv.h (FAKE_LABEL_CHAR): Define.
	* testsuite/gas/all/err-fakelabel.s: New.
 2017-11-22 11:20:48 -08:00
Jim Wilson
2ca23e65f5 Update docs on filling text with nops. 
gas/
	* doc/as.texinfo (.align): Change some to most for text nop fill.
	(.balign, .p2align): Likewise.
 2017-11-22 11:09:30 -08:00
Thomas Preud'homme
5aa75429d0 [GAS/ARM] Clarify relation between reg_expected_msgs and arm_reg_type 
Uses of reg_expected_msgs rely on each arm_reg_type enumerator to have a
message entry in the same order as the enumerator declaration. This is
not clearly stated in the definition of both the arm_reg_type enum and
the reg_expected_msgs. Worse, there is nothing to ensure both are kept
in sync.

As an attempt towards this, this patch uses C99 array designators to
ensure that each message is associated with the right arm_reg_type. A
comment is also added near the definition of arm_reg_type to point to
the reg_expected_msgs array. Finally, the array is synced with
arm_reg_type by adding the missing error message for REG_TYPE_RNB.

2017-11-22  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (arm_reg_type): Comment on the link with
	reg_expected_msgs.
	(reg_expected_msgs): Initialize using array designators with
	arm_reg_type index.
 2017-11-22 14:02:49 +00:00
claziss
dc95848142 [ARC] Fix handling of ARCv2 H-register class. 
For ARCv2, h-regs are only valid unitl r31.

gas/
2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>

        * testsuite/gas/arc/hregs-err.s: New test.

opcodes/
2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>

        * arc-opc.c (insert_rhv2): Check h-regs range.
 2017-11-22 10:46:45 +01:00
H.J. Lu
0ad71725d9 x86: Add tests for -n option of x86 assembler 
The -n command-line of x86 assembler disables optimization of alignment
directives, like ".balign 8, 0x90", with multi-byte nop instructions
such as leal 0(%esi),%esi.

	PR gas/22464
	* testsuite/gas/i386/align-1.s: New file.
	* testsuite/gas/i386/align-1a.d: Likewise.
	* testsuite/gas/i386/align-1b.d: Likewise.
	* testsuite/gas/i386/i386.exp: Run align-1a and align-1b.
 2017-11-21 16:44:29 -08:00
claziss
50d2740d56 [ARC] Improve printing of pc-relative instructions. 
opcodes/
2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>

	* arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
	* arc-opc.c (SIMM21_A16_5): Make it pc-relative.

gas/
2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>

	* testsuite/gas/arc/b.d : Update test.
	* testsuite/gas/arc/bl.d: Likewise.
	* testsuite/gas/arc/jli-1.d: Likewise.
	* testsuite/gas/arc/lp.d: Likewise.
	* testsuite/gas/arc/pcl-relocs.d: Likewise.
	* testsuite/gas/arc/pcrel-relocs.d: Likewise.
	* testsuite/gas/arc/pic-relocs.d: Likewise.
	* testsuite/gas/arc/plt-relocs.d: Likewise.
	* testsuite/gas/arc/pseudos.d: Likewise.
	* testsuite/gas/arc/relax-avoid2.d: Likewise.
	* testsuite/gas/arc/relax-avoid3.d: Likewise.
	* testsuite/gas/arc/relax-b.d: Likewise.
	* testsuite/gas/arc/tls-relocs.d: Likewise.
	* testsuite/gas/arc/relax-add01.d: Likewise.
	* testsuite/gas/arc/relax-add04.d: Likewise.
	* testsuite/gas/arc/relax-ld01.d: Likewise.
	* testsuite/gas/arc/relax-sub01.d: Likewise.
	* testsuite/gas/arc/relax-sub02.d: Likewise.
	* testsuite/gas/arc/relax-sub04.d: Likewise.
	* testsuite/gas/arc/pcl-print.s: New file.
	* testsuite/gas/arc/pcl-print.d: Likewise.
	* testsuite/gas/arc/nps400-12.d: Likewise.

ld/
2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>

	* testsuite/ld-arc/jli-simple.d: Update test.
 2017-11-21 14:56:16 +01:00
Alan Modra
bf3d139947 xtensa error message 
* config/tc-xtensa.c (finish_vinsn): Avoid multiple ngettext calls
	in error message.
 2017-11-21 11:20:24 +10:30
Alan Modra
b7486a74a6 mingw gas testsuite fix 
Some x86_64 targets pad sections with nops.

	* testsuite/gas/i386/x86-64-reg-bad.l: Accept trailing padding.
 2017-11-21 00:09:23 +10:30
Tamar Christina
d0f7791c66 Add new AArch64 FP16 FM{A|S} instructions. 
This patch separates the new FP16 instructions backported from Armv8.4-a to Armv8.2-a
into a new flag order to distinguish them from the rest of the already existing optional
FP16 instructions in Armv8.2-a.

The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory on
Armv8.4-a.

gas/

	* config/tc-aarch64.c (fp16fml): New.
	* doc/c-aarch64.texi (fp16fml): New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d (fp16): Make fp16fml.
	* testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d (fp16): Make fp16fml.

include/

	* opcode/aarch64.h: (AARCH64_FEATURE_F16_FML): New.
	(AARCH64_ARCH_V8_4): Enable AARCH64_FEATURE_F16_FML by default.

opcodes/

	* aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
	and AARCH64_FEATURE_F16.
 2017-11-16 16:27:35 +00:00
Tamar Christina
fadfa6b002 Correct AArch64 crypto dependencies. 
The crypto options depend on SIMD and FP, the documentation states so but the dependency is not there the code.

We have mostly gotten away with this due to the default flags
for the architectures (e.g. Armv8.2-a  implies +simd) but this
discrepancy needs to be addressed.

gas/

2017-11-16  Tamar Christina  <tamar.christina@arm.com>

	* opcodes/aarch64-tbl.h
	(aarch64_feature_crypto): Add ARCH64_FEATURE_SIMD and AARCH64_FEATURE_FP.
	(aarch64_feature_crypto_v8_2, aarch64_feature_sm4): Likewise.
	(aarch64_feature_sha3): Likewise.
 2017-11-16 16:27:35 +00:00
Tamar Christina
68ffd9368a Update documentation for Arvm8.4-A changes to AArch64. 
gas/

2017-11-16  Tamar Christina  <tamar.christina@arm.com>

	* doc/c-aarch64.texi (armv8.4-a, sha2, sha3, sm4): New.
	(dotprod): Update default note.
 2017-11-16 16:27:35 +00:00
Tamar Christina
e9dbdd80cb Add assembler and disassembler support for the new Armv8.4-a instructions for AArch64. 
Some of these instructions have been back-ported as optional extensions to
Armv8.2-a and higher, but others are only available for Armv8.4-a.

opcodes/

	* aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
	(rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
	(sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
	(fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
	(ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
	(ldapur, ldapursw, stlur): New.
	* aarch64-dis-2.c: Regenerate.

gas/

	* testsuite/gas/aarch64/armv8_4-a-illegal.d: New.
	* testsuite/gas/aarch64/armv8_4-a-illegal.l: New.
	* testsuite/gas/aarch64/armv8_4-a-illegal.s: New.
	* testsuite/gas/aarch64/armv8_4-a.d: New.
	* testsuite/gas/aarch64/armv8_4-a.s: New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16.s: New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d: New.
	* testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d: New.
	* testsuite/gas/aarch64/armv8_4-a-crypto-fp16.d: New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.s: New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l: New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.d: New.
 2017-11-16 16:27:35 +00:00
Jan Beulich
5f847646ee x86: ignore high register select bit(s) in 32- and 16-bit modes 
While commits 9889cbb14e ("Check invalid mask registers") and
abfcb414b9 ("X86: Ignore REX_B bit for 32-bit XOP instructions") went a
bit into the right direction, this wasn't quite enough:
- VEX.vvvv has its high bit ignored
- EVEX.vvvv has its high bit ignored together with EVEX.v'
- the high bits of {,E}VEX.vvvv should not be prematurely zapped, to
  allow proper checking of them when the fields has to hold al ones
- when the high bits of an immediate specify a register, bit 7 is
  ignored
 2017-11-16 13:56:45 +01:00
Jan Beulich
c2b9da1608 ix86/Intel: don't require memory operand size specifier for PTWRITE 
Other than in 64-bit mode, in 32- and 16-bit modes operand size isn't
ambiguous.
 2017-11-16 12:28:06 +01:00