This code sets up the cc variable based on the comparison of other
registers, but it does so incrementally with bit operations, and it
never initializes the cc variable. Initialize it to 0 which the
cmpba insn is already doing.
The PRU architecture documentation [1] was used for the initial GNU
simulator implementation. But recently [2] TI confirmed the carry
behaviour was wrongly documented. In reality, the PRU carry behaves
like the carry in ARM processors.
This patch fixes simulator to align with latest recommendations from TI.
The new carry.s test was also validated to pass on real hardware -
a BeaglePlay board [3]. That test is a bit long because TI still
has not released official updates for the PRU documents. And I wanted
to ensure simulator handles all edge cases exactly as the real hardware
does.
[1] https://www.ti.com/lit/pdf/spruij2
[2] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1244359/sk-am64b-am64x-pru-assembler-how-works-this-bloody-carry
[3] https://www.beagleboard.org/boards/beagleplay
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
Since newlib allows people to opt-in to extra errno names, pull them
into our table too. The values don't conflict with each other -- the
newlib names & values are distinct from newlib's Linux compatibility.
Since this function never returns, mark it as such to fix some unused
variable warnings in error code paths.
For example, cris triggers:
sim/cris/semcrisv10f-switch.c:3558:11: error:
variable 'tmp_newval' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized]
Even though it has an "else" path that calls this error function.
Since these insns don't do anything and are effectively ignored,
return early to avoid doing any common processing at the end as
that requires initializing variables like "res" with something.
The plds Dz,MACL insn stores the Dz bit into MACL. The current code
was storing the "res" variable into Dz and then into MACL, but not
setting "res" to anything. Delete that logic and make it match the
existing plds Dz,MACH insn.
These decoders declare a lot of common variables for use by substeps,
and then shadows a few because of how the opc generator is implemented.
Easiest way around it is to rename the per-substep vars as needed as
anything more would require substantial changes to the opc logic.
The mloop files include CGEN generated switch files which have some
nested assignments that expand into repeated shadowed variables.
Fixing this looks fairly non-trivial as it appears to be interplay
between the common CGEN code and how this particular set of cris
insns are defined. Disable the warning instead.
In file included from sim/cris/mloop.in:286:
sim/cris/semcrisv10f-switch.c: In function ‘crisv10f_engine_run_full’:
sim/cris/semcrisv10f-switch.c:12383:8: error: declaration of ‘opval’ shadows a previous local [-Werror=shadow=local]
12383 | SI opval = tmp_addr;
| ^~~~~
sim/cris/semcrisv10f-switch.c:12371:9: note: shadowed declaration is here
12371 | USI opval = ({ SI tmp_addr;
| ^~~~~
And the code looks like:
USI opval = ({
...
{
SI opval = tmp_addr;
...
}
...
});
Since the CGEN code treats "opval" as an internal variable that the cpu
definitions don't have direct access to, the likelihood of this being a
real bug is low, so leave it be. The warning is suppressed for more code
that is hand written (e.g. the mloop logic), but disabling for the entire
file is the easiest way to suppress while keeping it on everywhere else in
the sim.
Remove duplicate nested variable declarations, rename some to avoid
confusion when the type is different or the original value should be
retained, and fix some weirdness with nested enums in structs.
These functions have local vars named "val" of type float, and
then create nested vars named "val" of type double. This is a
bit confusing and causes build time warnings.
The generated mloop files can trigger compile time warnings. It can
be difficult to see/understand where the original code is coming from
as all the diagnostics point to the generated output. Using #line
pragmas, we can point people to the original source files.
Unfortunately, this code is written in POSIX shell, and that lacks
support for line number tracking. The $LINENO variable, even when
available, can just be plain wrong. For example, when using dash
and subshells, $LINENO can end up having negative values. Add a
wrapper script that will uses awk to rewrite the $LINENO variable
to the right value to avoid all that.
Basically lineno.sh takes an input script, rewrites all uses of
$LINENO into the actual line number (and $0 into the original file
name), and then executes the temporary script.
This commit doesn't actually add #line pragmas to any files. That
comes next.
Replace some fall through comments with the attribute, and add some
default abort calls when the compiler can't figure out that the set
of values were already fully enumerated in the switch statement.
All funcs already call other funcs that don't return. The mips port is
the only exception because its generic exception handler can return in
the case of normal exceptions. So while the exceptions its signal handler
triggers doesn't return, we can't express that conditional logic. So add
some useless abort calls to make the compiler happy.
The compiler pointed out that we're testing LAST_TIMER_REG and
LAST_COUNTER which are the same value ... and that's because we
set LAST_TIMER_REG to the wrong register. Fix the typo.
The compiler pointed out we checked AZ twice. Sort by name to avoid
that in the future, and to make it clearer that we have coverage of
all the bits. And add the bits we were missing.
The order here doesn't matter as it's just turning a pointer into a
human readable string when store tracing is enabled.
The scache vars aren't used by ports in the pbb & fast codepaths,
nor are they documented as inputs to the callbacks, so delete them
to avoid unused variable compiler warnings.
Pull out the common parts of the genmloop invocation into the common
code. This will make it easier to add more, and make the per-port
differences a little more obvious.
Fix one minor pointer-sign warning to enable warnings in general
for this file. Reading the data as signed and then returning it
as unsigned should be functionally the same in this case.
This came up testing the CRC optimization work from Mariam@RAU.
Basically to optimize some CRC loops into table lookups or carryless
multiplies, we may need to do a bit reflection, which on the mcore
processor is done using a rotate instruction.
Unfortunately the simulator implementation of rotates has the exact same
problem as we saw with right shifts. The input value may have been sign
extended from 32 to 64 bits. When we rotate the extended value, we get
those sign extension bits and thus the wrong result.
The fix is the same. Rather than using a "long", use a uint32_t for the
type of the temporary. This fixes a handful of tests in the GCC testsuite:
The push/pop insns only have 2 operands, so delete unused "c".
The pushret/popret insns use 2 operands, but they don't implement the
logic directly, they call the push/pop implementations. So delete the
unused "a" & "b".
The pmuls encoding is incorrect -- it looks like a copy & paste error
from the padd pmuls variant. The SuperH software manual covers this.
On the flip side, the manual lists pwsb & pwad as insns that exist,
but no description of what they do, what the insn name means, or the
actual encoding. Our sim implementation stubs them both out as nops.
Let's mark the fields to avoid unused variable warnings.
Fix a few problems caught by compiler warnings:
* Some of the asr & lsr insns were setting up the c state flag,
but then forgetting to set it in the PSW. Add it like the other
asr & lsr variants.
* Some of the dmulh insns were multiplying one of the source regs
against itself instead of against the other source reg.
* The sat16_cmp parallel insn was using the wrong register in the
compare -- the reg1 src/dst pair are used in the sat16 op, and
the reg2 src/dst pair are used in the add op.
The migration to local.mk in commit 0a129eb19a
accidentally listed the deps for all mloop steps as mloop.in instead of the
various variants that m32r uses.
Reported-by: Simon Marchi <simon.marchi@polymtl.ca>
The mloop.in code does this, but these variants do not. Use it to
avoid unused function warnings. The fast_p logic in these files
also looks off, but that'll require a bit more work to fixup.
CC m32r/mloopx.o
m32r/mloopx.c:37:1: error: ‘m32rxf_fill_argbuf_tp’ defined but not used [-Werror=unused-function]
37 | m32rxf_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
| ^~~~~~~~~~~~~~~~~~~~~
CC m32r/mloop2.o
m32r/mloop2.c:37:1: error: ‘m32r2f_fill_argbuf_tp’ defined but not used [-Werror=unused-function]
37 | m32r2f_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
| ^~~~~~~~~~~~~~~~~~~~~
Reported-by: Simon Marchi <simon.marchi@polymtl.ca>
Tested-By: Simon Marchi <simon.marchi@polymtl.ca>
When generating semantics.c from .igen source files, indenting the code
makes it more readable, but confuses compiler diagnostics. The latter
is a bit more important than the former, so bias towards that.
For example, with an introduced error, we can see w/gcc-13:
(before this change)
CC mn10300/semantics.o
../../../sim/mn10300/am33-2.igen: In function ‘semantic_dcpf_D1a’:
../../../sim/mn10300/am33-2.igen:11:5: error: ‘srcreg’ undeclared (first use in this function)
11 | srcreg = translate_rreg (SD_, RN2);
| ^~~~~~
(with this change)
CC mn10300/semantics.o
../../../sim/mn10300/am33-2.igen: In function ‘semantic_dcpf_D1a’:
../../../sim/mn10300/am33-2.igen:11:3: error: ‘srcreg’ undeclared (first use in this function)
11 | srcreg = translate_rreg (SD_, RN2);
| ^~~~~~
Running the H8 port through the GCC testsuite currently takes 4h 30m on my
fastest server -- that's roughly 1.5hrs per multilib tested and many tests are
disabled for various reasons.
To put that 1.5hr/multilib in perspective, that's roughly 3X the time for other
embedded targets. Clearly something isn't working as well as it should.
A bit of digging with perf shows that we're spending a crazy amount of time
decoding instructions in the H8 simulator. It's not hard to see why --
basically we take a blob of instruction data, then try to match it to every
instruction in the H8 opcode table starting at the beginning. That table has
~8000 entries (each different addressing mode is considered a different
instruction in the table).
Naturally my first thought was to sort the table and use a binary search to
find the right entry. That's made excessively complex due to the encoding on
the H8. Just getting the sort right would be much more complex than I'd
consider advisable.
Another thought was to build a mapping to the right entry for all the
instructions that can be disambiguated based on the first nibble (4 bits) of
instruction data and a mapping for those which can be disambiguated based on
the first byte of instruction data.
That seemed feasible until I realized that the H8/SX did some truly horrid
things with encoding branches in the 0x4XYY opcode space. It uses an "always
zero" bit in the offset to encode new semantic information. So we can't select
on just 0x4X. Ugh!
We could always to a custom decoder. I've done several through the years, they
can be very fast. But no way I can justify the time to do that.
So what I settled on was to first sort the opcode table by the first nibble,
then find the index of the first instruction for each nibble. Decoding uses
that index to start its search. This cuts the overall build/test by more than
half.
Next I adjusted the sort so that instructions that are not available on the
current sub architecture are put at the end of the table. This shaves another
~15% off the total cycle time.
The net of the two changes is on my fastest server we've gone from 4:30 to 1:40
running the GCC testsuite. Same test results before/after, of course. It's
still not fast, but it's a hell of a lot better.
We suppress the warning in the generated switch file because the cris
cpu file has a hack to workaround a cgen bug, but that generates a set
but unused variable which makes the compiler upset.
Rework the code to use static inline functions when it's disabled
rather than macros so the compiler knows the various function args
are always used. The ifdef macros are a bit ugly, but get the job
done without duplicating the function prototypes.
The function returns void, not int. We only pass one argument to
syslog (the format), so use %s as the static format instead since
the emulation layer doesn't handle passing additional arguments.
The cgen code mixes virtual insn enums with insn enums, and there isn't
an obvious (to me) way to unravel this atm, so disable the warning.
sim/lm32/decode.c:45:5: error:
implicit conversion from enumeration type 'CGEN_INSN_VIRTUAL_TYPE'
to different enumeration type 'CGEN_INSN_TYPE' (aka 'enum cgen_insn_type')
[-Werror,-Wenum-conversion]
45 | { VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY },
| ~ ^~~~~~~~~~~~~~~~~~~~~~
Bug: https://sourceware.org/PR29752
Sync with the list of flags from gdbsupport, and add a few more of
our own to catch recent issues. Comment out the C++-specific flags
as we don't build with C++.
Fix some of the sim_fpu calls to use the right types. While I'm
not familiar with the MIPS ISA in these cases, these look like
simple oversights due to the name/type mismatches. This at least
fixes compiling with -Wenum-conversion.
No functional change here, but makes it a little easier to read the
generated code when editors aren't highlighting all the spurious
trailing whitespace on lines.
The sim_stop argument is an enum and should only be one of those
values, not a signal constant. Fix the logic to pass the right
sim_xxx & SIM_xxx values in the right arguments.
We only support UTF-8 nowadays, so stop using ISO-8859-1.
Maybe we should delete this logic entirely, but for now,
do the bare min conversion to keep it compiling.
Reuse the bfd/development.sh script like most other project to
determine whether the current source tree is a dev build (e.g.
git) or a release build, and disable the warnings for releases.
This code tries to use attach_type enums as hw_phb_decode, and while
they're setup to have compatible values, the compiler doesn't like it
when the cast is missing. So cast it explicitly and then use that.
sim/ppc/hw_phb.c:322:28: error:
implicit conversion from enumeration type 'attach_type'
(aka 'enum _attach_type') to different enumeration type
'hw_phb_decode' [-Werror,-Wenum-conversion]
Don't conflate HAVE_GETRUSAGE & HAVE_SYS_RESOURCE_H. Use the latter
to include the header and nothing else. Use the former to determine
whether to use the function and nothing else. If we find a system
that doesn't follow POSIX and provides only one of these, we can
figure out how to support it then. The manual local definition is
clashing with the system ones and leading to build failures with
newer C standards.
sim/ppc/emul_netbsd.c:51:5: error: a function declaration without a
prototype is deprecated in all versions of C and is treated as a
zero-parameter prototype in C2x, conflicting with a previous
declaration [-Werror,-Wdeprecated-non-prototype]
If the value to be shifted has the sign bit set, the sign
bit would get copied into bits 32..63 of the temporary. Those
would then be right shifted into the final value giving an
incorrect final result.
This was observed with upcoming GCC improvements which eliminate
unnecessary extensions.
The BPF assembler has been updated to follow the clang convention in
the interpretation of semicolons: they separate statements and
directives, and do not start line comments.
According to we have changed all E_MIPS_* to EF_MIPS_* in binutils
and glibc, we also need to change it here to keep same style.
We can refer to this commit record:
https://sourceware.org/pipermail/binutils/2023-October/129904.html
Approved-By: Pedro Alves <pedro@palves.net>
Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written
before using it to calculate destination address.
This commit also improves testutils.inc for riscv; make use of
pushsection and popsection when adding things to .data, and setup the
%gp global pointer register within the 'start' macro.
Approved-By: Andrew Burgess <aburgess@redhat.com>
