Commit Graph

3301 Commits

Author SHA1 Message Date
Alan Modra
8c5e259235 Usage of unitialized heap in tic4x_print_cond
PR 25319
	* tic4x-dis.c (tic4x_print_cond): Init all of condtable.
2019-12-29 22:13:12 +10:30
Jan Beulich
376cd05610 x86-64: fix Intel64 handling of branch with data16 prefix
The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious
direct destination to translate to an indirect _far_ branch is plain
wrong. The operand size prefix should have no effect at all on the
interpretation of the operand. The main underlying issue here is that
the Intel64 templates of the direct branches don't include Disp16, yet
various assumptions exist that it would always be there when there's
also Disp32/Disp32S, toggled by the operand size prefix (which is
being ignored by direct branches in Intel64 mode).

Along these lines it was also wrong to base the displacement width
decision solely on the operand size prefix: REX.W cancels this effect
and hence needs taking into consideration, too.

A disassembler change is needed here as well: XBEGIN was wrongly treated
the same as direct CALL/JMP, which isn't the case - the operand size
prefix does affect displacement size there, it's merely ignored when it
comes to updating [ER]IP.
2019-12-27 09:38:34 +01:00
Jan Beulich
48bcea9f48 x86: consolidate Disp<NN> handling a little
In memory operand addressing, which forms of displacement are permitted
besides Disp8 is pretty clearly limited
- outside of 64-bit mode, Disp16 or Disp32 only, depending on address
  size (MPX being special in not allowing Disp16),
- in 64-bit mode, Disp32s or Disp64 without address size override, and
  solely Disp32 with one.
Adjust assembler and i386-gen to match this, observing that templates
already get adjusted before trying to match them against input depending
on the presence of an address size prefix.

This adjustment logic gets extended to all cases, as certain DispNN
values should also be dropped when there's no such prefix. In fact
behavior of the assembler, perhaps besides the exact diagnostics wording,
should not differ between there being templates applicable to 64-bit and
non-64-bit at the same time, or there being fully separate sets of
templates, with their DispNN settings already reduced accordingly.

This adjustment logic further gets guarded such that there wouldn't be
and Disp<N> conversion based on address size prefix when this prefix
doesn't control the width of the displacement (on branches other than
absolute ones).

These adjustments then also allow folding two MOV templates, which had
been split between 64-bit and non-64-bits variants so far.

Once in this area also
- drop the bogus DispNN from JumpByte templates, leaving just the
  correct Disp8 there (compensated by i386_finalize_displacement()
  now setting Disp8 on their operands),
- add the missing Disp32S to XBEGIN.

Note that the changes make it necessary to temporarily mark a test as
XFAIL; this will get taken care of by a subsequent patch. The failing
parts are entirely bogus and will get replaced.
2019-12-27 09:22:03 +01:00
Alan Modra
100b122fc1 ubsan: crx: index 5 out of bounds for type 'operand_desc const[5]'
* crx-dis.c (get_number_of_operands): Don't access operands[]
	out of bounds.
2019-12-26 17:49:03 +10:30
Alan Modra
6c2ca6c25d ubsan: v850: left shift cannot be represented in type 'int'
Another 1 << 31 complaint.

	* v850-dis.c (disassemble): Avoid signed overflow.  Don't use
	long vars when unsigned int will do.
2019-12-26 17:49:03 +10:30
Alan Modra
ebd1c6d1d3 ubsan: arm: shift exponent 32 is too large for 32-bit type 'unsigned int'
* arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
2019-12-24 12:01:42 +10:30
Jan Beulich
0e62b37a3f ppc: misc minor build corrections
Avoid shadowing a libiberty symbol (which oldish gcc warns about by
default), and allow building cleanly on 32-bit distros.
2019-12-23 11:53:10 +01:00
Alan Modra
7936714c0c ubsan: score: left shift of 2 by 31 places cannot be represented in type 'int'
* score-dis.c (print_insn_score32): Avoid signed overflow.
	(print_insn_score48): Likewise.  Don't cast to int when printing
	hex values.
2019-12-23 18:05:19 +10:30
Alan Modra
3e1056a1a6 ubsan: iq2000: left shift of negative value
cpu/
	* iq2000.cpu (f-offset): Avoid left shift of negative values.
opcodes/
	* iq2000-ibld.c: Regenerate.
2019-12-23 18:04:12 +10:30
Alan Modra
1a1e2852a5 ubsan: d30v: left shift cannot be represented in type 'long long'
* d30v-dis.c (extract_value): Make num param a uint64_t, constify
	oper.  Use unsigned vars.
	(print_insn): Make num var uint64_t.  Constify oper and remove now
	unnecessary casts on extract_value calls.
	(print_insn_d30v): Use unsigned vars.  Adjust printf formats.
2019-12-23 18:02:44 +10:30
Alan Modra
27c1c4271a ubsan: wasm: shift is too large for 64-bit type 'bfd_vma'
bfd/
	* wasm-module.c (wasm_read_leb128): Don't allow oversize shifts.
	Catch value overflow.  Sign extend only on terminating byte.
opcodes/
	* wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
	Catch value overflow.  Sign extend only on terminating byte.
2019-12-23 17:58:09 +10:30
Alan Modra
cda8d785b3 PR25281, sh disassembler abort
PR 25281
	* sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
	and MOVY_NOPX insns.  For invalid cases include 0xf000 in the word
	printed.  Print .word in more cases.
2019-12-20 17:57:58 +10:30
Alan Modra
bcd9f578a9 ubsan: or1k: left shift of negative value
cpu/
	* or1korbis.cpu (f-disp26, f-disp21): Don't left shift negative values.
opcodes/
	* or1k-ibld.c: Regenerate.
2019-12-20 17:57:58 +10:30
Alan Modra
15d2859fdd ubsan: hppa: left shift of negative value
bfd/
	* libhppa.h (hppa_field_adjust, bfd_hppa_insn2fmt): Delete forward
	declaration.  Move ATTRIBUTE_UNUSED to definition.
	(sign_extend, low_sign_extend, sign_unext, low_sign_unext),
	(re_assemble_3, re_assemble_12, re_assemble_14, re_assemble_16),
	(re_assemble_17, re_assemble_21, re_assemble_22): Likewise.  Make
	args and return value unsigned.  Use unsigned variables.
	(hppa_rebuild_insn): Similarly.
opcodes/
	* hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
	unsigned variables.
2019-12-20 13:36:06 +10:30
Alan Modra
000fe1a756 ubsan: m68hc1x: left shift of negative value
* m68hc11-dis.c (read_memory): Delete forward decls.
	(print_indexed_operand, print_insn): Likewise.
	(print_indexed_operand): Formatting.  Don't rely on short being
	exactly 16 bits, make sign extension explicit.
	(print_insn): Likewise.  Avoid signed overflow.
2019-12-20 13:36:06 +10:30
Alan Modra
f00901886d vax decoding of indexed addressing mode
This patch prevents print_insn_mode recursing into another index mode
byte, which if repeated enough times will overflow private.the_buffer
and scribble over other memory.

	* vax-dis.c (print_insn_mode): Stop index mode recursion.
2019-12-19 15:38:39 +10:30
Dr N.W. Filardo
1d29ab86cb PR25277, microblaze opcode enumeration vs ISO/IEC TS 18661-3:2015
fadd, fmul, and fdiv are now, by ISO/IEC TS 18661-3:2015, defined to
refer to functions from the runtime subsystem.

	PR 25277
	* microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
	fdiv with "mbi_".
	* microblaze-opc.h (opcodes): Adjust to suit.
2019-12-19 10:54:47 +10:30
Alan Modra
2480b6fa94 More signed overflow fixes
The arc fix in create_map avoiding signed overflow by casting an
unsigned char to unsigned int before shifting, shows one of the
dangers of blinding doing that.  The problem in this case was that the
variable storing the value, newAuxRegister->address, was a long.
Using the unsigned cast meant that the 32-bit value was zero extended
when long is 64 bits.  Previously we had a sign extension.  Net result
was that comparisons in arcExtMap_auxRegName didn't match.  Of course,
I could have cast the 32-bit unsigned value back to signed before
storing in a long, but it's neater to just use an unsigned int for the
address.

opcodes/
	* alpha-opc.c (OP): Avoid signed overflow.
	* arm-dis.c (print_insn): Likewise.
	* mcore-dis.c (print_insn_mcore): Likewise.
	* pj-dis.c (get_int): Likewise.
	* ppc-opc.c (EBD15, EBD15BI): Likewise.
	* score7-dis.c (s7_print_insn): Likewise.
	* tic30-dis.c (print_insn_tic30): Likewise.
	* v850-opc.c (insert_SELID): Likewise.
	* vax-dis.c (print_insn_vax): Likewise.
	* arc-ext.c (create_map): Likewise.
	(struct ExtAuxRegister): Make "address" field unsigned int.
	(arcExtMap_auxRegName): Pass unsigned address.
	(dump_ARC_extmap): Adjust.
	* arc-ext.h (arcExtMap_auxRegName): Update prototype.
2019-12-18 18:38:13 +10:30
Alan Modra
eb7b504651 ubsan: visium: left shift cannot be represented in type 'int'
* visium-dis.c (print_insn_visium): Avoid signed overflow.
2019-12-17 23:15:12 +10:30
Alan Modra
29298bf66f ubsan: aarch64: left shift cannot be represented in type 'int64_t'
* aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
	(value_fit_unsigned_field_p): Likewise.
	(aarch64_wide_constant_p): Likewise.
	(operand_general_constraint_met_p): Likewise.
	* aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
2019-12-17 22:58:19 +10:30
Alan Modra
e46d79a76e ubsan: nds32: left shift cannot be represented in type 'int'
Yet more.

	* nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
	(print_insn_nds32): Use uint64_t for "given" and "given1".
2019-12-17 22:58:11 +10:30
Alan Modra
5b660084e2 Remove tic80 support
This is one way of fixing ubsan bug reports, just delete the code.

The assembler support was removed back in 2005 along with other
non-BFD assemblers, but somehow the remainder of the port stayed in.

bfd/
	* coff-tic80.c: Delete file.
	* cpu-tic80.c: Delete file.
	* archures.c: Remove tic80 support.
	* coffcode.h: Likewise.
	* coffswap.h: Likewise.
	* targets.c: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* Makefile.am: Likewise.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
binutils/
	* testsuite/binutils-all/objcopy.exp: Remove tic80 support.
	* testsuite/binutils-all/objdump.exp: Likewise.
gas/
	* doc/as.texi: Remove mention of tic80.
include/
	* coff/tic80.h: Delete file.
	* opcode/tic80.h: Delete file.
ld/
	* emulparams/tic80coff.sh: Delete file.
	* scripttempl/tic80coff.sc: Delete file.
	* configure.tgt: Remove tic80 support.
	* Makefile.am: Likewise.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
opcodes/
	* tic80-dis.c: Delete file.
	* tic80-opc.c: Delete file.
	* disassemble.c: Remove tic80 support.
	* disassemble.h: Likewise.
	* Makefile.am: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
2019-12-17 16:36:54 +10:30
Alan Modra
62e6599087 ubsan: bpf: left shift cannot be represented in type 'DI' (aka 'long')
cpu/
	* bpf.cpu (f-imm64): Avoid signed overflow.
opcodes/
	* bpf-ibld.c: Regenerate.
2019-12-17 14:32:23 +10:30
Alan Modra
f81e7e2db6 ubsan: aarch64: left shift of negative value
* aarch64-dis.c (sign_extend): Return uint64_t.  Rewrite without
	conditional.
	(aarch64_ext_imm): Avoid signed overflow.
2019-12-16 17:35:13 +10:30
Alan Modra
488d02fe77 ubsan: microblaze: left shift cannot be represented in type 'int'
* microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
2019-12-16 17:35:13 +10:30
Alan Modra
8a92faab92 ubsan: nios2: left shift cannot be represented in type 'int'
* nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
2019-12-16 17:35:13 +10:30
Alan Modra
e6ced26afd ubsan: xstormy16: left shift of negative value
cpu/
	* xstormy16.cpu (f-rel12a): Avoid signed overflow.
opcodes/
	* xstormy16-ibld.c: Regenerate.
2019-12-16 17:35:13 +10:30
Alan Modra
84e098cdea asan: score: global-buffer-overflow
I'm flying blind here, not having an s+core s3 insn set reference,
but this seems reasonably obvious from what is done by the assembler.
s3_do16_rpop does some mixing of imm and reg values to place in the
rpop reg field, but I'm not going to try to fix the disassembly
there.

	* score-dis.c (print_insn_score16): Move rpush/rpop imm field
	value adjustment so that it doesn't affect reg field too.
2019-12-16 17:34:29 +10:30
Alan Modra
36bd8ea7f0 ubsan: crx: left shift cannot be represented in type 'int'
The ubsan complaint is fixed by the SBM change, with similar possible
complaints fixed by the EXTRACT change.  The rest is just cleanup.

include/
	* opcode/crx.h (inst <match>): Make unsigned int.
opcodes/
	* crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
	(get_number_of_operands, getargtype, getbits, getregname),
	(getcopregname, getprocregname, gettrapstring, getcinvstring),
	(getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
	(powerof2, match_opcode, make_instruction, print_arguments),
	(print_arg): Delete forward declarations, moving static to..
	(getregname, getcopregname, getregliststring): ..these definitions.
	(build_mask): Return unsigned int mask.
	(match_opcode): Use unsigned int vars.
2019-12-16 17:33:53 +10:30
Alan Modra
cedfc77485 ubsan: bfin: left shift of negative value
* bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
2019-12-16 17:33:53 +10:30
Alan Modra
4bdb25fe69 ubsan: nds32: left shift cannot be represented in type 'int'
Note that using 1u in N32_BIT makes all of N32_BIT, __MASK, __MF, __GF
and __SEXT evaluate as unsigned int (the latter three when when their
v arg is int or smaller).  This would be a problem if assigning the
result to a bfd_vma, long, or other type wider than an int since the
__SEXT result would be zero extended to the wider type.  Fortunately
nds32 target code doesn't use wider types unnecessarily.

include/
	* opcode/nds32.h (N32_BIT): Define using 1u.
	(__SEXT): Use __MASK and N32_BIT.
	(N32_IMMS): Remove duplicate mask.
opcodes/
	* nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
	(struct objdump_disasm_info): Delete.
	(nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
	N32_IMMS to unsigned before shifting left.
2019-12-16 17:33:53 +10:30
Alan Modra
cf950fd4dd ubsan: moxie: left shift of negative value
Commit 8c9b417187 didn't remove a glaring left shift of a number
that had just been sign extended.

	* moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
	(print_insn_moxie): Remove unnecessary cast.
2019-12-16 17:28:52 +10:30
Alan Modra
967354c3b9 csky: tidy csky_chars_to_number
* csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
	mask.
2019-12-12 16:46:45 +10:30
Alan Modra
1d61b03226 Remove more shifts for sign/zero extension
cpu/
	* epiphany.cpu (f-sdisp11): Don't sign extend with shifts.
	* lm32.cpu (f-branch, f-vall): Likewise.
	* m32.cpu (f-lab-8-16): Likewise.
opcodes/
	* arc-dis.c (BITS): Don't truncate high bits with shifts.
	* nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
	* tic54x-dis.c (print_instruction): Likewise.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.
	* tilepro-opc.c (parse_insn_tilepro): Likewise.
	* visium-dis.c (disassem_class0): Likewise.
	* pdp11-dis.c (sign_extend): Likewise.
	(SIGN_BITS): Delete.
	* epiphany-ibld.c: Regenerate.
	* lm32-ibld.c: Regenerate.
	* m32c-ibld.c: Regenerate.
2019-12-11 21:14:19 +10:30
Alan Modra
5afa80e9a8 Re: ubsan: ns32k: left shift cannot be represented in type
* ns32k-dis.c (sign_extend): Correct last patch.
2019-12-11 13:33:26 +10:30
Alan Modra
5c05618a0a ubsan: vax: left shift cannot be represented in type 'int'
* vax-dis.c (NEXTLONG): Avoid signed overflow.
2019-12-11 11:42:09 +10:30
Alan Modra
2a81ccbbbf ubsan: v850: left shift cannot be represented in type 'long'
* v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
	sign extend using shifts.
2019-12-11 11:41:52 +10:30
Alan Modra
b84f6152ee ubsan: tic6x: shift left of int
* tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
2019-12-11 11:41:27 +10:30
Alan Modra
66152f1668 ubsan: tic4x: segv and signed shifts
* tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
	on NULL registertable entry.
	(tic4x_hash_opcode): Use unsigned arithmetic.
2019-12-11 11:41:09 +10:30
Alan Modra
205c426a9b ubsan: s12z: left shift cannot be represented in type 'int'
* s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
2019-12-11 11:40:51 +10:30
Alan Modra
fb4cb4e26d ubsan: ns32k: left shift cannot be represented in type 'int'
* ns32k-dis.c (bit_extract): Use unsigned arithmetic.
	(bit_extract_simple, sign_extend): Likewise.
2019-12-11 11:40:33 +10:30
Alan Modra
96f1f60460 ubsan: nios2: left shift cannot be represented in type 'int'
* nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
2019-12-11 11:40:17 +10:30
Alan Modra
8c9b417187 ubsan: moxie: left shift of negative value
* moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
2019-12-11 11:40:00 +10:30
Alan Modra
334175b693 ubsan: m68k: left shift cannot be represented in type 'int'
* m68k-dis.c (COERCE32): Cast value first.
	(NEXTLONG, NEXTULONG): Avoid signed overflow.
2019-12-11 11:39:42 +10:30
Alan Modra
f8a87c78e6 ubsan: h8300: left shift cannot be represented in type 'int'
This is
  *cst = (data[0] << 24) + (data[1] << 16) + (data[2] << 8) + data[3];
data is unsigned char which promotes to int.

	* h8300-dis.c (extract_immediate): Avoid signed overflow.
	(bfd_h8_disassemble): Likewise.
2019-12-11 11:39:25 +10:30
Alan Modra
159653d8c0 ussan: d30v: index out of bounds
* d30v-dis.c (print_insn): Make opind unsigned.  Don't access
	past end of operands array.
2019-12-11 11:39:07 +10:30
Alan Modra
d93bba9e0d ubsan: csky: left shift cannot be represented in type 'int'
In the following buf is an unsigned char array, so elements are
promoted to int before arithmetic operations.

  if (dis_info.info->endian == BFD_ENDIAN_BIG)
    while (n--)
      val |= buf[n] << (n*8);
  else
    for (i = 0; i < n; i++)
      val |= buf[i] << (i*8);

	* csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
	overflow when collecting bytes of a number.
2019-12-11 11:38:45 +10:30
Alan Modra
c202f69e51 ubsan: cris: signed integer overflow
This was the following in print_with_operands
case 4:
  number
    = buffer[2] + buffer[3] * 256 + buffer[4] * 65536
    + buffer[5] * 0x1000000;
and buffer[5] * 0x1000000 can indeed overflow.  So to fix this we need
to use unsigned arithmetic where overflow semantics are specified.
But number is a long, and the expression is int which will be sign
extended to long.  If we make the expression unsigned it will be zero
extended.  So make number an int32_t and rearrange a little for some
of the places that need fixing.

	* cris-dis.c (print_with_operands): Avoid signed integer
	overflow when collecting bytes of a 32-bit integer.
2019-12-11 11:38:24 +10:30
Alan Modra
0ef562a4b5 ubsan: cr16: left shift cannot be represented in type 'int'
This was:
  unsigned long mask = SBM (instruction->match_bits);
with
  #define SBM(offs)  ((((1 << (32 - offs)) -1) << (offs)))

Well, there are a couple of problems.  Firstly, the expression uses
int values (1 rather than 1u or 1ul) resulting in the ubsan error, and
secondly, a zero offs will result in a 32-bit shift which is undefined
if ints are only 32 bits.

	* cr16-dis.c (EXTRACT, SBM): Rewrite.
	(cr16_match_opcode): Delete duplicate bcond test.
2019-12-11 11:38:04 +10:30
Alan Modra
2fd2b153a3 ubsan: bfin: shift exponent is too large
This was the following in fmtconst_val, x is unsigned int.
    x = SIGNEXTEND (x, constant_formats[cf].nbits);
Problem is, the SIGNEXTEND macro assumed its arg was a long and sign
extended by shifting left then shifting right, and didn't cast the
arg.  So don't do the silly shift thing.  It's not guaranteed to work
anyway according to the C standard.  ">>" might do a logical shift
even if its args are signed.

	* bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
	(SIGNBIT): New.
	(MASKBITS, SIGNEXTEND): Rewrite.
	(fmtconst): Don't use ? expression now that SIGNEXTEND uses
	unsigned arithmetic, instead assign result of SIGNEXTEND back
	to x.
	(fmtconst_val): Use 1u in shift expression.
2019-12-11 11:37:44 +10:30