Patch from 2003-07-22 Kei Sakamoto <sakamoto.kei@renesas.com>:
* m32r-tdep.c (m32r_memory_insert_breakpoint): Fix code style -
operator at start and not end of line.
(decode_prologue): Ditto.
(m32r_frame_unwind_cache, m32r_unwind_sp, m32r_unwind_pc): Use
frame_unwind_register_unsigned instead of
frame_unwind_unsigned_register.
(m32r_read_pc): Use regcache_cooked_read_unsigned instead of
read_register.
(m32r_push_dummy_call): Use register_size instead of
REGISTER_RAW_SIZE.
(m32r_frame_sniffer): Replace m32r_frame_p.
(m32r_gdbarch_init): Call frame_unwind_append_sniffer.
* m32r-rom.c (report_transfer_performance): Delete extern
declaration.
(m32r_load, m32r_upload_command): Use print_transfer_performance
instead of report_transfer_performance.
(_initialize_m32r_rom): Use add_setshow_cmd instead of add_set_cmd
/ add_show_from_set.
on function descriptors.
(ELIMINATE_COPY_RELOCS): Expand comment.
(ppc64_elf_special_sections): Move. Don't include non-ppc64 sections.
Do include ".toc1".
2003-07-25 H.J. Lu <hongjiu.lu@intel.com>
* elf.c (_bfd_elf_new_section_hook): Set the default section
type to SHT_NULL.
(elf_fake_sections): Set the section type based on asect->flags
if it is SHT_NULL. Don't abort on processor specific section
types.
gas/
2003-07-25 H.J. Lu <hongjiu.lu@intel.com>
* config/obj-elf.c (obj_elf_change_section): Update
elf_section_type and elf_section_flags only when they are
specified.
* gencode.c (pshl): Change < to <= (shift by 16 is allowed).
Cast argument of >> to unsigned to prevent sign extension.
(psha): Change < to <= (shift by 32 is allowed).
window and give focus to a next window.
(tui_initialize_readline): Bind it to c-x o.
(tui_rl_next_keymap): Activate TUI mode when entering SingleKey mode.
* m68hc11-tdep.c (_initialize_m68hc11_tdep): Deprecate "regs" command.
(m68hc11_print_register): New function to print out one register.
(m68hc11_print_registers_info): New function to print registers.
(show_regs): Deprecate and use the above.
(m68hc11_gdbarch_init): Install the print_registers_info.
(allocate_dynrelocs): Likewise.
(sh_elf_relocate_section): Likewise. Use SYMBOL_REFERENCES_LOCAL.
(sh_elf_finish_dynamic_symbol): Use SYMBOL_REFERENCES_LOCAL.
* gencode.c: A few more fix-ups of refs and defs.
(frchg): Raise SIGILL if in double-precision mode.
(ldtlb): We don't simulate cache, so this is a no-op.
(movsxy_tab): Correct a few bit pattern errors.
near the beginning of the file. Swap order of arguments. Call
_bfd_elf_dynamic_symbol_p with "ignore_protected" set to 0.
(elf_xtensa_fix_refcounts): Adjust xtensa_elf_dynamic_symbol_p call.
(elf_xtensa_relocate_section): Likewise.
(shrink_dynamic_reloc_sections): Likewise.
(elf_xtensa_size_dynamic_sections): Use elf_discarded_section.
(elf_xtensa_combine_prop_entries): Avoid returning non-zero without
first printing an error message.
(elf_xtensa_finish_dynamic_sections): Likewise.
(elf_xtensa_discard_info_for_section): Adjust size of .got.loc when
discarding literal table entries.
(elf_xtensa_merge_private_bfd_data): Remove newline from error message.
(elf_xtensa_do_asm_simplify): Likewise.
* gencode.c (ppi_gensim): For a conditional ppi insn, if the
condition is false, we want to return (not break). A break
will take us to the end of the function where registers will
be updated, whereas the desired outcome is for nothing to change.
* gencode.c (op tab): Some fix-ups of refs and defs.
(ocbi, ocbp): Cache not simulated, but may cause memory fault.
(gensym_caselist): Add default case to switch statement.
(expand_ppi_code): Add default case to switch statement.
