Commit Graph

3176 Commits

Author SHA1 Message Date
Claudiu Zissulescu
8784b6df88 Revert "arc: Update opcode related include files for ARCv3."
This reverts commit 04414221df.
2023-09-25 17:02:41 +03:00
Claudiu Zissulescu
04414221df arc: Update opcode related include files for ARCv3.
Add new ARCv3 CPUs and required bits to decode/encode ARCv3 ISA
opcodes. Fix 32 bit relocations which were set as signed but should be
bitfield: ARC_32_ME, ARC_GLOB_DAT, ARC_JMP_SLOT, ARC_RELATIVE. Remove
non-ABI relocation ARC_32_ME_S.

include/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>
	    Cupertino Miranda  <cupertinomiranda@gmail.com>
	    Bruno Mauricio <brunoasmauricio@gmail.com>

	* include/elf/arc-cpu.def: Add new HS5x and HS6x CPUs.
	* include/elf/arc-reloc.def: Add new ARC64 relocations.
	* include/elf/arc.h (EF_ARC_CPU_ARC64): New define.
	* include/opcode/arc-attrs.h (FEATURE_LIST_NAME): Update predicate.
	* include/opcode/arc-func.h: Update formating.
	(replace_disp8ls): New function.
	(replace_disp9s): Likewise.
	(replace_disp6s): Likewise.
	(replace_disp7s): Likewise.
	(replace_disp12s): Likewise.
	* include/opcode/arc.h (ARC_OPCODE_ARC64): New define.
	(ARC_OPCODE_ARC32): Likewise.
	(ARC_OPERAND_FP): Likewise.
	(HARD_FIELDF): Likewise.
	(ARC_OPCODE_ARCVx): New macro.
	(arc_flag_class): Update structure to hold new extract/insert
	functions for flags.
	(INSN3OP): Update macro.
	(FP_SIZE, TPOF, DPOF, SOPF, COPF, CONVOPS): New enums.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-25 10:55:51 +03:00
Jan Beulich
d486800436 RISC-V: fold duplicate code in vector_macro()
There's no need to have almost identical code twice. Do away with
M_VMSGEU and instead simply use an unused (for these macros) field to
tell apart both variants.
2023-09-05 10:03:35 +02:00
Tsukasa OI
a303646f17 RISC-V: Add 'Smcntrpmf' extension and its CSRs
This commit adds now stable and approved 'Smcntrpmf' extension defined by
the RISC-V Cycle and Instret Privilege Mode Filtering specification.

Note that, because mcyclecfg and minstretcfg CSRs conflict with the
privileged specification version 1.9.1, CSRs for this extension are only
enabled on the privileged specification version 1.10 or later.

By checking the base privileged specification, we no longer need to change
the design of base CSR handling.

This is based on the specification version v1.0_rc1 (Frozen):
<32b752c40d>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add implication rule from
	the new 'Smcntrpmf' extension.  (riscv_supported_std_s_ext): Add
	'Smcntrpmf' to the supported S extension list.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add new CSR classes
	CSR_CLASS_SMCNTRPMF and CSR_CLASS_SMCNTRPMF_32.
	(riscv_csr_address): Add handling for new CSR classes.
	* testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs.  Move
	"mscounteren" and "mhcounteren" CSRs and note that they are now
	aliases.
	* testsuite/gas/riscv/csr-dw-regnums.d: Reflect the change.
	* testsuite/gas/riscv/csr.s: Add new CSRs.  Move "mscounteren"
	and "mhcounteren" CSRs and note that they are now reused for
	the 'Smcntrpmf' extension.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Reflect the changes of
	csr.s.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h: Add new CSRs noting that this extension is
	incompatible with the privileged specification version 1.9.1.
	Move "mscounteren" and "mhcounteren" CSRs, make them aliases and
	reuse the CSR numbers from the 'Smcntrpmf' extension.
	(CSR_MSCOUNTEREN, CSR_MHCOUNTEREN) Remove as "mscounteren" and
	"mhcounteren" are now aliases and new CSR macros are used instead.
	(CSR_MCYCLECFG, CSR_MINSTRETCFG, CSR_MCYCLECFGH, CSR_MINSTRETCFGH):
	New CSR macros.
2023-09-05 03:09:30 +00:00
Alan Modra
6785fd72d5 PE dos_message
I was looking at dos_message and wondering why we have H_PUT_32
in _bfd_XXi_only_swap_filehdr_out but no H_GET_32 in pe_bfd_object_p.
On a big-endian machine this would result in scrambling the code and
strings constained in dos_message.  Rather than fix the lack of
H_GET_32 in pe_bfd_object_p, I decided it doesn't make sense to store
dos_message internally as an array of ints.

include/
	* coff/internal.h (struct internal_extra_pe_filehdr): Make
	dos_message a char array.
	* coff/msdos.h (struct external_DOS_hdr): Flatten dos_message.
	* coff/pe.h (struct external_PEI_filehdr): Likewise.
bfd/
	* libcoff-in.h (struct pe_tdata): Make dos_message a char array.
	* libcoff.h: Regenerate.
	* peXXigen.c (_bfd_XXi_only_swap_filehdr_out): memcpy dos_message
	to output.
	* peicode.h (pe_mkobject): Don't memset already zeroed pe_opthdr.
	Tidy allocation of tdata.pe_obj_data.  Set up dos_message from..
	(default_dos_message): ..this.  New static array.
2023-08-27 21:21:38 +09:30
Victor Do Nascimento
a4822788d7 aarch64: Improve naming conventions for A and R-profile architecture
Historically, flags and variables relating to architectural revisions
for the A-profile architecture omitted the trailing `A' such that, for
example, assembling for `-march=armv8.4-a' set the `AARCH64_ARCH_V8_4'
flag in the assembler.

This leads to some ambiguity, since Binutils also targets the
R-profile Arm architecture.  Therefore, it seems prudent to have
everything associated with the A-profile cores end in `A' and likewise
`R' for the R-profile.  Referring back to the example above, the flag
set for `-march=armv8.4-a' is better characterized if labeled
`AARCH64_ARCH_V8_4A'.

The only exception to the rule of appending `A' to variables is found
in the handling of the `AARCH64_FEATURE_V8' macro, as it is the
baseline from which ALL processors derive and should therefore be left
unchanged.

In reflecting the `ARM' architectural nomenclature choices, where we
have `ARM_ARCH_V8A' and `ARM_ARCH_V8R', the choice is made to not have
an underscore separating the numerical revision number and the
A/R-profile indicator suffix.  This has meant that renaming of
R-profile related flags and variables was warranted, thus going from
`.*_[vV]8_[rR]' to `.*_[vV]8[rR]'.

Finally, this is more in line with conventions within GCC and adds consistency
across the toolchain.

gas/ChangeLog:
	* gas/config/tc-aarch64.c:
	(aarch64_cpus): Reference to arch feature macros updated.
	(aarch64_archs): Likewise.

include/ChangeLog:
	* include/opcode/aarch64.h:
	(AARCH64_FEATURE_V8A): Updated name: V8_A -> V8A.
	(AARCH64_FEATURE_V8_1A): A-suffix added.
	(AARCH64_FEATURE_V8_2A): Likewise.
	(AARCH64_FEATURE_V8_3A): Likewise.
	(AARCH64_FEATURE_V8_4A): Likewise.
	(AARCH64_FEATURE_V8_5A): Likewise.
	(AARCH64_FEATURE_V8_6A): Likewise.
	(AARCH64_FEATURE_V8_7A): Likewise.
	(AARCH64_FEATURE_V8_8A):Likewise.
	(AARCH64_FEATURE_V9A): Likewise.
	(AARCH64_FEATURE_V8R): Updated name: V8_R -> V8R.
	(AARCH64_ARCH_V8A_FEATURES): Updated name: V8_A -> V8A.
	(AARCH64_ARCH_V8_1A_FEATURES): A-suffix added.
	(AARCH64_ARCH_V8_2A_FEATURES): Likewise.
	(AARCH64_ARCH_V8_3A_FEATURES): Likewise.
	(AARCH64_ARCH_V8_4A_FEATURES): Likewise.
	(AARCH64_ARCH_V8_5A_FEATURES): Likewise.
	(AARCH64_ARCH_V8_6A_FEATURES): Likewise.
	(AARCH64_ARCH_V8_7A_FEATURES): Likewise.
	(AARCH64_ARCH_V8_8A_FEATURES): Likewise.
	(AARCH64_ARCH_V9A_FEATURES): Likewise.
	(AARCH64_ARCH_V9_1A_FEATURES): Likewise.
	(AARCH64_ARCH_V9_2A_FEATURES): Likewise.
	(AARCH64_ARCH_V9_3A_FEATURES): Likewise.
	(AARCH64_ARCH_V8A): Updated name: V8_A -> V8A.
	(AARCH64_ARCH_V8_1A): A-suffix added.
	(AARCH64_ARCH_V8_2A): Likewise.
	(AARCH64_ARCH_V8_3A): Likewise.
	(AARCH64_ARCH_V8_4A): Likewise.
	(AARCH64_ARCH_V8_5A): Likewise.
	(AARCH64_ARCH_V8_6A): Likewise.
	(AARCH64_ARCH_V8_7A): Likewise.
	(AARCH64_ARCH_V8_8A): Likewise.
	(AARCH64_ARCH_V9A): Likewise.
	(AARCH64_ARCH_V9_1A): Likewise.
	(AARCH64_ARCH_V9_2A): Likewise.
	(AARCH64_ARCH_V9_3A): Likewise.
	(AARCH64_ARCH_V8_R): Updated name: V8_R -> V8R.

opcodes/ChangeLog:
	* opcodes/aarch64-opc.c (SR_V8A): Updated name: V8_A -> V8A.
	(SR_V8_1A): A-suffix added.
	(SR_V8_2A): Likewise.
	(SR_V8_3A): Likewise.
	(SR_V8_4A): Likewise.
	(SR_V8_6A): Likewise.
	(SR_V8_7A): Likewise.
	(SR_V8_8A): Likewise.
	(aarch64_sys_regs): Reference to arch feature macros updated.
	(aarch64_pstatefields): Reference to arch feature macros updated.
	(aarch64_sys_ins_reg_supported_p): Reference to arch feature macros
	updated.
	* opcodes/aarch64-tbl.h:
	(aarch64_feature_v8_2a): a-suffix added.
	(aarch64_feature_v8_3a): Likewise.
	(aarch64_feature_fp_v8_3a): Likewise.
	(aarch64_feature_v8_4a): Likewise.
	(aarch64_feature_fp_16_v8_2a): Likewise.
	(aarch64_feature_v8_5a): Likewise.
	(aarch64_feature_v8_6a): Likewise.
	(aarch64_feature_v8_7a): Likewise.
	(aarch64_feature_v8r): Updated name: v8_r-> v8r.
	(ARMV8R): Updated name: V8_R-> V8R.
	(ARMV8_2A): A-suffix added.
	(ARMV8_3A): Likewise.
	(FP_V8_3A): Likewise.
	(ARMV8_4A): Likewise.
	(FP_F16_V8_2A): Likewise.
	(ARMV8_5): Likewise.
	(ARMV8_6A): Likewise.
	(ARMV8_6A_SVE): Likewise.
	(ARMV8_7A): Likewise.
	(V8_2A_INSN): `A' added to macro symbol.
	(V8_3A_INSN): Likewise.
	(V8_4A_INSN): Likewise.
	(FP16_V8_2A_INSN): Likewise.
	(V8_5A_INSN): Likewise.
	(V8_6A_INSN): Likewise.
	(V8_7A_INSN): Likewise.
	(V8R_INSN): Updated name: V8_R-> V8R.
2023-08-22 16:46:33 +01:00
David Faust
41aa80c544 bpf: correct neg and neg32 instruction encoding
The neg/neg32 BPF instructions always use BPF_SRC_K (=0) in their header
source bit, despite operating on registers.  If BPF_SRC_X (=1) is set,
the instructions are rejected by the kernel.

Because of this there are also no neg/neg32 instructions which operate
on immediates, so remove them.

bd434cc4d9 was a similar fix in the old
CGEN-based port, but was not carried forward in the new port.

include/
	* opcode/bpf.h (enum bpf_insn_id): Remove spurious entries
	BPF_INSN_NEGI and BPF_INSN_NEG32I.

opcodes/
	* bpf-opc.c (bpf_opcodes): Remove erroneous NEGI and NEG32I
	instructions.

gas/
	* doc/c-bpf.texi (BPF Instructions): Remove erroneous neg and
	neg32 instructions operating on immediates.
	* testsuite/gas/bpf/alu.s: Adapt accordingly.
	* testsuite/gas/bpf/alu.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise
	* testsuite/gas/bpf/alu32.s: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise.
	* testsuite/gas/bpf/alu32-be.d: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-08-21 10:07:25 -07:00
Luis Machado
11e3488d3f aarch64/sme2: Teach binutils/BFD about the NT_ARM_ZT register set
The Scalable Matrix Extension v2 (SME2) defines a new register, ZT0, that
the Linux Kernel handles through a new NT_ARM_ZT register set.

Teach binutils/BFD about it so that gdb can make use of it for reading
and writing core files.  This also enables readelf/objdump to show the
correct identification for the NT_ARM_ZT register set.

Validated under Fast Models.
2023-08-21 12:43:43 +01:00
Paul Iannetta
6e712424f5 kvx: New port. 2023-08-16 14:22:54 +01:00
Tsukasa OI
239af8cbd1 RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'
The documentation of the 'Zfa' extension states that "fli.h" is available
"if the Zfh or Zvfh extension is implemented" (both the latest and the
oldest editions are checked).

This fact was not reflected in Binutils ('Zvfh' implies 'Zfhmin', not full
'Zfh' extension and "fli.h" required 'Zfh' and 'Zfa' extensions).
This commit makes "fli.h" also available when both 'Zfa' and 'Zvfh'
extensions are implemented.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add new
	instruction class handling.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zfa-zvfh.s: New test.
	* testsuite/gas/riscv/zfa-zvfh.d: Ditto.

include/ChangeLog:

	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	class.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Change instruction class of "fli.h"
	from INSN_CLASS_ZFH_AND_ZFA to new INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA.
2023-08-15 06:46:18 +00:00
Tsukasa OI
2266f86318 RISC-V: Add support for the 'Zihintntl' extension
This commit adds 'Zihintntl' extension and its hint instructions.

This is based on:
<0dc91f505e>,
the first ISA Manual noting that the 'Zihintntl' extension is ratified.

Note that compressed 'Zihintntl' hints require either 'C' or
'Zca' extension.

Co-authored-by: Nelson Chu <nelson@rivosinc.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zihintntl'
	standard hint 'Z' extension.
	(riscv_multi_subset_supports): Support new instruction classes.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zihintntl.s: New test for 'Zihintntl'
	including auto-compression without C prefix and explicit C prefix.
	* testsuite/gas/riscv/zihintntl.d: Likewise.
	* testsuite/gas/riscv/zihintntl-na.d: Likewise.
	* testsuite/gas/riscv/zihintntl-base.s: New test for correspondence
	between 'Zihintntl' and base 'I' or 'C' instructions.
	* testsuite/gas/riscv/zihintntl-base.d: Likewise.

include/ChangeLog:

	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	classes: INSN_CLASS_ZIHINTNTL and INSN_CLASS_ZIHINTNTL_AND_C.
	(MASK_NTL_P1, MATCH_NTL_P1, MASK_NTL_PALL,
	MATCH_NTL_PALL, MASK_NTL_S1, MATCH_NTL_S1, MASK_NTL_ALL,
	MATCH_NTL_ALL, MASK_C_NTL_P1, MATCH_C_NTL_P1, MASK_C_NTL_PALL,
	MATCH_C_NTL_PALL, MASK_C_NTL_S1, MATCH_C_NTL_S1, MASK_C_NTL_ALL,
	MATCH_C_NTL_ALL): New.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add instructions from the
	'Zihintntl' extension.
2023-08-15 06:45:26 +00:00
Jan Beulich
02a63525ef RISC-V: remove indirection from register tables
The longest register name is 4 characters (plus a nul one), so using a
4- or 8-byte pointer to get at it is neither space nor time efficient.
Embed the names right into the array. For PIE this also reduces the
number of base relocations in the final image.

To avoid old gcc, when generating 32-bit code, bogusly warning about
bounds being exceeded in the code processing Cs/Cw, Ct/Cx, and CD,
an adjustment to EXTRACT_BITS() is needed: This macro shouldn't supply
a 64-bit value, and it also doesn't need to - all operand fields to
date are far more narrow than 32 bits. This in turn allows dropping a
number of casts elsewhere.
2023-08-15 08:34:56 +02:00
Max Filippov
db863e7870 gcc: xtensa: add data alignment properties to dynconfig
include/
	* xtensa-dynconfig.h (xtensa_config_v4): New struct.
	(XCHAL_DATA_WIDTH, XCHAL_UNALIGNED_LOAD_EXCEPTION)
	(XCHAL_UNALIGNED_STORE_EXCEPTION, XCHAL_UNALIGNED_LOAD_HW)
	(XCHAL_UNALIGNED_STORE_HW, XTENSA_CONFIG_V4_ENTRY_LIST): New
	definitions.
	(XTENSA_CONFIG_INSTANCE_LIST): Add xtensa_config_v4 instance.
	(XTENSA_CONFIG_ENTRY_LIST): Add XTENSA_CONFIG_V4_ENTRY_LIST.
2023-08-12 10:24:26 +09:30
Max Filippov
f70e702065 gcc: xtensa: add XCHAL_HAVE_{CLAMPS, DEPBITS, EXCLUSIVE, XEA3} to dynconfig
include/
	* xtensa-dynconfig.h (xtensa_config_v3): New struct.
	(xtensa_get_config_v3): New declaration.
	(XCHAL_HAVE_CLAMPS, XCHAL_HAVE_DEPBITS, XCHAL_HAVE_EXCLUSIVE)
	(XCHAL_HAVE_XEA3, XTENSA_CONFIG_V3_ENTRY_LIST): New definitions.
	(XTENSA_CONFIG_INSTANCE_LIST): Add xtensa_config_v3 instance.
	(XTENSA_CONFIG_ENTRY_LIST): Add XTENSA_CONFIG_V3_ENTRY_LIST.
2023-08-12 10:24:26 +09:30
Xi Ruoyao
079b20e89d LoongArch: implement count_{leading,trailing}_zeros
LoongArch always support clz and ctz instructions, so we can always use
__builtin_{clz,ctz} for count_{leading,trailing}_zeros.  This improves
the code of libgcc, and also benefits Glibc once we merge longlong.h
there.

Bootstrapped and regtested on loongarch64-linux-gnu.

include/
	* longlong.h [__loongarch__] (count_leading_zeros): Define.
	[__loongarch__] (count_trailing_zeros): Likewise.
	[__loongarch__] (COUNT_LEADING_ZEROS_0): Likewise.
2023-08-12 09:58:22 +09:30
Meghan Denny
82fc3423c3 Updated constants from <https://dwarfstd.org/Languages.php>
include/
	* dwarf2.h: Update with additional languages from dwarf
	standard.
2023-08-12 09:58:22 +09:30
Jason Merrill
9ba1efd215 c++: source position of lambda captures [PR84471]
include/
	* ansidecl.h (ATTRIBUTE_WARN_UNUSED_RESULT): Add __.
2023-08-12 09:58:22 +09:30
Lulu Cheng
a5e58a4164 Libvtv: Add loongarch support.
The loongarch64 specification permits page sizes of 4KiB, 16KiB and 64KiB,
but only 16KiB pages are supported for now.

Co-Authored-By: qijingwen <qijingwen@loongson.cn>

include/
	* vtv-change-permission.h (defined): Determines whether the macro
	__loongarch_lp64 is defined
	(VTV_PAGE_SIZE): Set VTV_PAGE_SIZE to 16KiB for loongarch64.
2023-08-12 09:58:22 +09:30
Tom Tromey
f559e52a8e Remove PEI_HEADERS define
I noticed a few files double-included libcoff.h, and digging deeper I
found that the PEI_HEADERS define is a sort of external include guard.

This patch adds include guards to the few files in include/coff that
were missing one, and then removes the PEI_HEADERS workaround and the
redundant includes.

I didn't see anything in these files that indicated that
double-inclusion would be useful, so it seems to me that this approach
is ok.

Tested by rebuilding with --enable-targets=all.

2023-08-02  Tom Tromey  <tromey@adacore.com>

	* pei-x86_64.c (PEI_HEADERS): Do not define.
	* pei-loongarch64.c (PEI_HEADERS): Do not define.
	* pei-aarch64.c (PEI_HEADERS): Do not define.
	* pe-x86_64.c (PEI_HEADERS): Do not define.
	* pe-aarch64.c (PEI_HEADERS): Do not define.
	* libpei.h (_LIBPEI_H): Add include guard.
	* coff-x86_64.c (PEI_HEADERS): Do not check.
	* coff-loongarch64.c (PEI_HEADERS): Do not check.
	* coff-aarch64.c (PEI_HEADERS): Do not check.

include/ChangeLog
2023-08-02  Tom Tromey  <tromey@adacore.com>

	* coff/x86_64.h (COFF_X86_64_H): Add include guard.
	* coff/loongarch64.h (COFF_LOONGARCH64_H): Add include guard.
	* coff/aarch64.h (COFF_AARCH64_H): Add include guard.
2023-08-03 07:39:15 -06:00
Sam James
b5c37946cc Revert "2.41 Release sources"
This reverts commit 675b9d612c.

See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 12:06:23 +01:00
Nick Clifton
675b9d612c 2.41 Release sources 2023-08-02 09:23:36 +01:00
Jose E. Marchesi
1e18ffc991 bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flags
This patch adds support for EF_BPF_CPUVER bits in the ELF
machine-dependent header flags.  These bits encode the BPF CPU
version for which the object file has been compiled for.

The BPF assembler is updated so it annotates the object files it
generates with these bits.

The BPF disassembler is updated so it honors EF_BPF_CPUVER to use the
appropriate ISA version if the user didn't specify an explicit ISA
version in the command line.  Note that a value of zero in
EF_BPF_CPUVER is interpreted by the disassembler as "use the later
supported version" (the BPF CPU versions start with v1.)

The readelf utility is updated to pretty print EF_BPF_CPUVER when it
prints out the ELF header:

   $ readelf -h a.out
   ELF Header:
     ...
     Flags:                             0x4, CPU Version: 4

Tested in bpf-unknown-none.

include/ChangeLog:

2023-07-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* elf/bpf.h (EF_BPF_CPUVER): Define.
	* opcode/bpf.h (BPF_XBPF): Change from 0xf to 0xff so it fits in
	EF_BPF_CPUVER.

binutils/ChangeLog:

2023-07-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* readelf.c (get_machine_flags): Recognize and pretty print BPF
	machine flags.

opcodes/ChangeLog:

2023-07-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-dis.c: Initialize asm_bpf_version to -1.
	(print_insn_bpf): Set BPF ISA version from the cpu version ELF
	header flags if no explicit version set in the command line.
	* disassemble.c (disassemble_init_for_target): Remove unused code.

gas/ChangeLog:

2023-07-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.h (elf_tc_final_processing): Define.
	* config/tc-bpf.c (bpf_elf_final_processing): New function.
2023-07-30 22:39:30 +02:00
David Faust
02f68ef297 bpf: Add atomic compare-and-exchange instructions
This patch adds the two remaining BPF v3 atomic instructions:
- BPF_INSN_ACMP{,32}: atomic compare-and-swap
- BPF_INSN_AXCHG{,32}: atomic (non-conditional) exchange

Tests and documentation are also updated.

gas/
	* doc/c-bpf.texi (BPF Instructions): Document atomic exchange and
	atomic compare-and-swap instructions.
	* testsuite/gas/bpf/atomic.s: Test ACMP, ACMP32, AXCHG, AXCGH32
	instructions.
	* testsuite/gas/bpf/atomic.d: Likewise.
	* testsuite/gas/bpf/atomic-be.d: Likewise.
	* testsuite/gas/bpf/atomic-pseudoc.s: Likewise.
	* testsuite/gas/bpf/atomic-pseudoc.d: Likewise.
	* testsuite/gas/bpf/atomic-be-pseudoc.d: Likewise.

include/
	* opcode/bpf.h (BPF_IMM32_ACMP): Fix typo.
	(enum bpf_insn_id): New entries for BPF_INSN_ACMP{,32} and
	BPF_INSN_AXCHG{,32}.

opcodes/
	* bpf-opc.c (bpf_opcodes): Add entries for ACMP{,32} and
	AXCHG{,32} instructions.
2023-07-25 13:40:06 -07:00
Jose E. Marchesi
5cbe549257 bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64}
This patch adds support for the BPF V4 ISA byte swap instructions to
opcodes, assembler and disassembler.

Tested in bpf-unknown-none.

include/ChangeLog:

2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/bpf.h (BPF_IMM32_BSWAP16): Define.
	(BPF_IMM32_BSWAP32): Likewise.
	(BPF_IMM32_BSWAP64): Likewise.
	(enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}.

opcodes/ChangeLog:

2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
	instructions.

gas/ChangeLog:

2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions.
	* testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions.
	* testsuite/gas/bpf/alu.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
2023-07-24 02:54:06 +02:00
Jose E. Marchesi
c2ca88d74b bpf: add support for jal/gotol jump instruction with 32-bit target
This patch adds support for the V4 BPF instruction jal/gotol, which is
like ja/goto but it supports a signed 32-bit PC-relative (in number of
64-bit words minus one) target operand instead of the 16-bit signed
operand of the other instruction.  This greatly increases the jump
range in BPF programs.

Tested in bpf-unkown-none.

bfd/ChangeLog:

2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32.
	* elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc.
	* libbfd.h (bfd_reloc_code_real_names): Regenerate.

gas/ChangeLog:

2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.c (struct bpf_insn): New field `id'.
	(md_assemble): Save the ids of successfully parsed instructions
	and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate.
	(md_apply_fix): Adapt to the new BFD reloc.
	* testsuite/gas/bpf/jump.s: Test JAL.
	* testsuite/gas/bpf/jump.d: Likewise.
	* testsuite/gas/bpf/jump-pseudoc.d: Likewise.
	* testsuite/gas/bpf/jump-be.d: Likewise.
	* testsuite/gas/bpf/jump-be-pseudoc.d: Likewise.
	* doc/c-bpf.texi (BPF Instructions): Document new instruction
	jal/gotol.
	Document new operand type disp32.

include/ChangeLog:

2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL.
	(enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI.

opcodes/ChangeLog:

2023-07-23  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c (bpf_opcodes): Add entry for jal.
2023-07-24 01:20:03 +02:00
Jose E. Marchesi
c24fd9547f bpf: opcodes, gas: support for signed load V4 instructions
This commit adds the signed load to register (ldxs*) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.

Tested in bpf-unknown-none.

include/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/bpf.h (enum bpf_insn_id): Add entries for signed load
	instructions.
	(BPF_MODE_SMEM): Define.

opcodes/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
	instructions.

gas/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.s: Add signed load instructions.
	* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
	* testsuite/gas/bpf/mem.d: Likewise.
	* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
	* testsuite/gas/bpf/mem-be.d: Likewise.
	* doc/c-bpf.texi (BPF Instructions): Document the signed load
	instructions.
2023-07-21 20:00:30 +02:00
Jose E. Marchesi
2f3dbc5fb5 bpf: opcodes, gas: support for signed register move V4 instructions
This commit adds the signed register move (movs) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.

Tested in bpf-unknown-none.

include/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/bpf.h (BPF_OFFSET16_MOVS8): Define.
	(BPF_OFFSET16_MOVS16): Likewise.
	(BPF_OFFSET16_MOVS32): Likewise.
	(enum bpf_insn_id): Add entries for MOVS{8,16,32}R and
	MOVS32{8,16,32}R.

opcodes/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
	MOVS32{8,16,32}R instructions.  and MOVS32I instructions.

gas/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.s: Test movs instructions.
	* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction.
	* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu.d: Add expected results.
	* testsuite/gas/bpf/alu32.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32-be.d: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-21 20:00:30 +02:00
Jose E. Marchesi
d218e7fedc DesCGENization of the BPF binutils port
CGEN is cool, but the BPF architecture is simply too bizarre for it.

The weird way of BPF to handle endianness in instruction encoding, the
weird C-like alternative assembly syntax, the weird abuse of
multi-byte (or infra-byte) instruction fields as opcodes, the unusual
presence of opcodes beyond the first 32-bits of some instructions, are
all examples of what makes it a PITA to continue using CGEN for this
port.  The bpf.cpu file is becoming so complex and so nested with
p-macros that it is very difficult to read, and quite challenging to
update.  Also, every time we are forced to change something in CGEN to
accommodate BPF requirements (which is often) we have to do extensive
testing to make sure we do not break any other target using CGEN.

This is getting un-maintenable.

So I have decided to bite the bullet and revamp/rewrite the port so it
no longer uses CGEN.  Overall, this involved:

* To remove the cpu/bpf.{cpu,opc} descriptions.

* To remove the CGEN generated files.

* To replace the CGEN generated opcodes table with a new hand-written
  opcodes table for BPF.

* To replace the CGEN generated disassembler wih a new disassembler
  that uses the new opcodes.

* To replace the CGEN generated assembler with a new assembler that uses the
  new opcodes.

* To replace the CGEN generated simulator with a new simulator that uses the
  new opcodes. [This is pushed in GDB in another patch.]

* To adapt the build systems to the new situation.

Additionally, this patch introduces some extensions and improvements:

* A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF
  relocation R_BPF_GNU_64_16 are added to the BPF BFD port.  These
  relocations are used for section-relative 16-bit offsets used in
  load/store instructions.

* The disassembler now has support for the "pseudo-c" assembly syntax of
  BPF.  What dialect to use when disassembling is controlled by a command
  line option.

* The disassembler now has support for dumping instruction immediates in
  either octal, hexadecimal or decimal.  The used output base is controlled
  by a new command-line option.

* The GAS BPF test suite has been re-structured and expanded in order to
  test the disassembler pseudoc syntax support.  Minor bugs have been also
  fixed there.  The assembler generic tests that were disabled for bpf-*-*
  targets due to the previous implementation of pseudoc syntax are now
  re-enabled.  Additional tests have been added to test the new features of
  the assembler.  .dump files are no longer used.

* The linker BPF test suite has been adapted to the command line options
  used by the new disassembler.

The result is very satisfactory.  This patchs adds 3448 lines of code
and removes 10542 lines of code.

Tested in:

* Target bpf-unknown-none with 64-bit little-endian host and 32-bit
  little-endian host.

* Target x86-64-linux-gnu with --enable-targets=all

Note that I have not tested in a big-endian host yet.  I will do so
once this lands upstream so I can use the GCC compiler farm.

I have not included ChangeLog entries in this patch: these would be
massive and not very useful, considering this is pretty much a rewrite
of the port.  I beg the indulgence of the global maintainers.
2023-07-21 12:20:40 +02:00
Jiawei
b0a101c53a RISC-V: Supports Zcb extension.
This patch support Zcb extension, contains new compressed instructions,
some instructions depend on other existed extension, like 'zba', 'zbb'
and 'zmmul'.  Zcb also imply Zca extension to enable the compressing
features.

Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>

bfd/ChangeLog:

        * elfxx-riscv.c (riscv_multi_subset_supports): New extension.
        (riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

        * config/tc-riscv.c (validate_riscv_insn): New operators.
        (riscv_ip): Ditto.
        * testsuite/gas/riscv/zcb.d: New test.
        * testsuite/gas/riscv/zcb.s: New test.

include/ChangeLog:

        * opcode/riscv-opc.h (MATCH_C_LBU): New opcode.
        (MASK_C_LBU): New mask.
        (MATCH_C_LHU): New opcode.
        (MASK_C_LHU): New mask.
        (MATCH_C_LH): New opcode.
        (MASK_C_LH): New mask.
        (MATCH_C_SB): New opcode.
        (MASK_C_SB): New mask.
        (MATCH_C_SH): New opcode.
        (MASK_C_SH): New mask.
        (MATCH_C_ZEXT_B): New opcode.
        (MASK_C_ZEXT_B): New mask.
        (MATCH_C_SEXT_B): New opcode.
        (MASK_C_SEXT_B): New mask.
        (MATCH_C_ZEXT_H): New opcode.
        (MASK_C_ZEXT_H): New mask.
        (MATCH_C_SEXT_H): New opcode.
        (MASK_C_SEXT_H): New mask.
        (MATCH_C_ZEXT_W): New opcode.
        (MASK_C_ZEXT_W): New mask.
        (MATCH_C_NOT): New opcode.
        (MASK_C_NOT): New mask.
        (MATCH_C_MUL): New opcode.
        (MASK_C_MUL): New mask.
        (DECLARE_INSN): New opcode.
        * opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func.
        (EXTRACT_ZCB_HALFWORD_UIMM): Ditto.
        (ENCODE_ZCB_BYTE_UIMM): Ditto.
        (ENCODE_ZCB_HALFWORD_UIMM): Ditto.
        (VALID_ZCB_BYTE_UIMM): Ditto.
        (VALID_ZCB_HALFWORD_UIMM): Ditto.
        (enum riscv_insn_class): New extension class.

opcodes/ChangeLog:

        * riscv-dis.c (print_insn_args): New operators.
        * riscv-opc.c: New instructions.
2023-07-18 11:45:58 +08:00
Alan Modra
478409b71d AIX_WEAK_SUPPORT
Making target code depend on a host define like _AIX52 is never
correct, so out it goes.  Also, sort some config.bfd entries a little
to make it more obvious there is a config difference between aix5.1
and aix5.2.  These two changes should make no difference to anything
in binutils.  The gas define of AIX_WEAK_SUPPORT on the other hand was
wrong, so fix that.  Finally, fix some testsuite fails on aix < 5.2 by
simply not running the tests.

include/
	* coff/internal.h (C_WEAKEXT): Don't depend on _AIX52.
bfd/
	* coffcode.h (coff_slurp_symbol_table): Don't depend on _AIX52.
	(coff_classify_symbol): Likewise.
	* config.bfd: Sort some entries.
gas/
	* configure.ac (AIX_WEAK_SUPPORT): Don't set for aix5.[01].
	* configure: Regenerate.
	* testsuite/gas/ppc/aix.exp (xcoff-visibility-1*) Don't run
	for aix < 5.2.
2023-07-14 11:43:52 +09:30
Christoph Müllner
704b30cbb2 RISC-V: Zvkh[a,b]: Remove individual instruction class
Currently we have three instruction classes defined for Zvkh[a,b]:
- INSN_CLASS_ZVKNHA
- INSN_CLASS_ZVKNHB
- INSN_CLASS_ZVKNHA_OR_ZVKNHB

The encodings of all instructions in Zvknh[a,b] are identical.
Therefore, we don't need the individual instruction classes
and can remove them.

This patch also adds the missing support of the combined instruction
class in riscv_multi_subset_supports_ext().

Fixes: 62edb233ef ("RISC-V: Add support for the Zvknh[a,b] ISA extensions")
Reported-By: Nelson Chu <nelson@rivosinc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-03 18:17:59 +08:00
Nick Clifton
d501d38488 Add markers for the 2.41 branch 2023-07-03 11:12:15 +01:00
Christoph Müllner
259a2647dc RISC-V: Add support for the Zvksh ISA extension
Zvksh is part of the vector crypto extensions.

This extension adds the following instructions:
- vsm3me.vv
- vsm3c.vi

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvksh.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvksh.d: New test.
	* testsuite/gas/riscv/zvksh.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VSM3C_VI): New.
	(MASK_VSM3C_VI): New.
	(MATCH_VSM3ME_VV): New.
	(MASK_VSM3ME_VV): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction class
	support for Zvksh.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvksh instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01 07:28:40 -06:00
Christoph Müllner
5ec6edd0a2 RISC-V: Add support for the Zvksed ISA extension
Zvksed is part of the vector crypto extensions.

This extension adds the following instructions:
- vsm4k.vi
- vsm4r.[vv,vs]

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvksed.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvksed.d: New test.
	* testsuite/gas/riscv/zvksed.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VSM4K_VI): New.
	(MASK_VSM4K_VI): New.
	(MATCH_VSM4R_VS): New.
	(MASK_VSM4R_VS): New.
	(MATCH_VSM4R_VV): New.
	(MASK_VSM4R_VV): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction class
	support for Zvksed.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvksed instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01 07:28:40 -06:00
Christoph Müllner
62edb233ef RISC-V: Add support for the Zvknh[a,b] ISA extensions
Zvknh[a,b] are parts of the vector crypto extensions.

This extension adds the following instructions:
- vsha2ms.vv
- vsha2c[hl].vv

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvknh[a,b].
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvknha.d: New test.
	* testsuite/gas/riscv/zvknha_zvknhb.s: New test.
	* testsuite/gas/riscv/zvknhb.d: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New.
	(MASK_VSHA2CH_VV): New.
	(MATCH_VSHA2CL_VV): New.
	(MASK_VSHA2CL_VV): New.
	(MATCH_VSHA2MS_VV): New.
	(MASK_VSHA2MS_VV): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction class
	support for Zvknh[a,b].

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvknh[a,b] instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01 07:28:40 -06:00
Christoph Müllner
fce8fef965 RISC-V: Add support for the Zvkned ISA extension
Zvkned is part of the vector crypto extensions.

This extension adds the following instructions:
- vaesef.[vv,vs]
- vaesem.[vv,vs]
- vaesdf.[vv,vs]
- vaesdm.[vv,vs]
- vaeskf1.vi
- vaeskf2.vi
- vaesz.vs

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvkned.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvkned.d: New test.
	* testsuite/gas/riscv/zvkned.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VAESDF_VS): New.
	(MASK_VAESDF_VS): New.
	(MATCH_VAESDF_VV): New.
	(MASK_VAESDF_VV): New.
	(MATCH_VAESDM_VS): New.
	(MASK_VAESDM_VS): New.
	(MATCH_VAESDM_VV): New.
	(MASK_VAESDM_VV): New.
	(MATCH_VAESEF_VS): New.
	(MASK_VAESEF_VS): New.
	(MATCH_VAESEF_VV): New.
	(MASK_VAESEF_VV): New.
	(MATCH_VAESEM_VS): New.
	(MASK_VAESEM_VS): New.
	(MATCH_VAESEM_VV): New.
	(MASK_VAESEM_VV): New.
	(MATCH_VAESKF1_VI): New.
	(MASK_VAESKF1_VI): New.
	(MATCH_VAESKF2_VI): New.
	(MASK_VAESKF2_VI): New.
	(MATCH_VAESZ_VS): New.
	(MASK_VAESZ_VS): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction class
	support for Zvkned.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvkned instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01 07:28:40 -06:00
Christoph Müllner
9d469329d2 RISC-V: Add support for the Zvkg ISA extension
Zvkg is part of the vector crypto extensions.

This extension adds the following instructions:
- vghsh.vv
- vgmul.vv

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvkg.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvkg.d: New test.
	* testsuite/gas/riscv/zvkg.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VGHSH_VV): New.
	(MASK_VGHSH_VV): New.
	(MATCH_VGMUL_VV): New.
	(MASK_VGMUL_VV): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction class
	support for Zvkg.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvkg instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01 07:28:40 -06:00
Nathan Huckleberry
c0a98a853d RISC-V: Add support for the Zvbc extension
Zvbc is part of the crypto vector extensions.

This extension adds the following instructions:
- vclmul.[vv,vx]
- vclmulh.[vv,vx]

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvbc.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvbc.d: New test.
	* testsuite/gas/riscv/zvbc.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VCLMUL_VV): New.
	(MASK_VCLMUL_VV): New.
	(MATCH_VCLMUL_VX): New.
	(MASK_VCLMUL_VX): New.
	(MATCH_VCLMULH_VV): New.
	(MASK_VCLMULH_VV): New.
	(MATCH_VCLMULH_VX): New.
	(MASK_VCLMULH_VX): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction class
	  support for Zvbc.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvbc instruction.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01 07:28:34 -06:00
Christoph Müllner
c8cb37347f RISC-V: Add support for the Zvbb ISA extension
Zvbb is part of the vector crypto extensions.

This extension adds the following instructions:
- vandn.[vv,vx]
- vbrev.v
- vbrev8.v
- vrev8.v
- vclz.v
- vctz.v
- vcpop.v
- vrol.[vv,vx]
- vror.[vv,vx,vi]
- vwsll.[vv,vx,vi]

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvbb.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Add 'l' as new format
	string directive.
	(riscv_ip): Likewise.
	* testsuite/gas/riscv/zvbb.d: New test.
	* testsuite/gas/riscv/zvbb.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VANDN_VV): New.
	(MASK_VANDN_VV): New.
	(MATCH_VANDN_VX): New.
	(MASK_VANDN_VX): New.
	(MATCH_VBREV8_V): New.
	(MASK_VBREV8_V): New.
	(MATCH_VBREV_V): New.
	(MASK_VBREV_V): New.
	(MATCH_VCLZ_V): New.
	(MASK_VCLZ_V): New.
	(MATCH_VCPOP_V): New.
	(MASK_VCPOP_V): New.
	(MATCH_VCTZ_V): New.
	(MASK_VCTZ_V): New.
	(MATCH_VREV8_V): New.
	(MASK_VREV8_V): New.
	(MATCH_VROL_VV): New.
	(MASK_VROL_VV): New.
	(MATCH_VROL_VX): New.
	(MASK_VROL_VX): New.
	(MATCH_VROR_VI): New.
	(MASK_VROR_VI): New.
	(MATCH_VROR_VV): New.
	(MASK_VROR_VV): New.
	(MATCH_VROR_VX): New.
	(MASK_VROR_VX): New.
	(MATCH_VWSLL_VI): New.
	(MASK_VWSLL_VI): New.
	(MATCH_VWSLL_VV): New.
	(MASK_VWSLL_VV): New.
	(MATCH_VWSLL_VX): New.
	(MASK_VWSLL_VX): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New.
	(ENCODE_RVV_VI_UIMM6): New.
	(enum riscv_insn_class): Add instruction class for Zvbb.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add 'l' as new format string
	directive.
	* riscv-opc.c: Add Zvbb instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01 07:14:45 +02:00
Christoph Müllner
1f3fc45bdd RISC-V: Add support for the Zfa extension
This patch adds support for the RISC-V Zfa extension,
which introduces additional floating-point instructions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of FP registers in case XLEN < FLEN
* fleq/fltq (quiet comparison instructions)

Zfa defines its instructions in combination with the following
extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)

This patch is based on an earlier version from Tsukasa OI:
  https://sourceware.org/pipermail/binutils/2022-September/122939.html
Most significant change to that commit is the switch from the rs1-field
value to the actual floating-point value in the last operand of the fli*
instructions. Everything that strtof() can parse is accepted and
the '%a' printf specifier is used to output hex floating-point literals
in the disassembly.

The Zfa specification is frozen (and has passed public review).  It is
available as a chapter in "The RISC-V Instruction Set Manual: Volume 1":
  https://github.com/riscv/riscv-isa-manual/releases

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for 'Zfa' extension.
	(riscv_multi_subset_supports_ext): Likewise.
	(riscv_implicit_subsets): Add 'Zfa' -> 'F' dependency.

gas/ChangeLog:

	* config/tc-riscv.c (flt_lookup): New helper to lookup a float value
	in an array.
	(validate_riscv_insn): Add 'Wfv' as new format string directive.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Add floating-point chapter and describe
	limiations of the Zfa FP literal parsing.
	* testsuite/gas/riscv/zfa-32.d: New test.
	* testsuite/gas/riscv/zfa-32.s: New test.
	* testsuite/gas/riscv/zfa-64.d: New test.
	* testsuite/gas/riscv/zfa-64.s: New test.
	* testsuite/gas/riscv/zfa-fail.d: New test.
	* testsuite/gas/riscv/zfa-fail.l: New test.
	* testsuite/gas/riscv/zfa-fail.s: New test.
	* testsuite/gas/riscv/zfa.d: New test.
	* testsuite/gas/riscv/zfa.s: New test.
	* testsuite/gas/riscv/zfa.s: New test.

	* opcode/riscv-opc.h (MATCH_FLI_H): New.
	(MASK_FLI_H): New.
	(MATCH_FMINM_H): New.
	(MASK_FMINM_H): New.
	(MATCH_FMAXM_H): New.
	(MASK_FMAXM_H): New.
	(MATCH_FROUND_H): New.
	(MASK_FROUND_H): New.
	(MATCH_FROUNDNX_H): New.
	(MASK_FROUNDNX_H): New.
	(MATCH_FLTQ_H): New.
	(MASK_FLTQ_H): New.
	(MATCH_FLEQ_H): New.
	(MASK_FLEQ_H): New.
	(MATCH_FLI_S): New.
	(MASK_FLI_S): New.
	(MATCH_FMINM_S): New.
	(MASK_FMINM_S): New.
	(MATCH_FMAXM_S): New.
	(MASK_FMAXM_S): New.
	(MATCH_FROUND_S): New.
	(MASK_FROUND_S): New.
	(MATCH_FROUNDNX_S): New.
	(MASK_FROUNDNX_S): New.
	(MATCH_FLTQ_S): New.
	(MASK_FLTQ_S): New.
	(MATCH_FLEQ_S): New.
	(MASK_FLEQ_S): New.
	(MATCH_FLI_D): New.
	(MASK_FLI_D): New.
	(MATCH_FMINM_D): New.
	(MASK_FMINM_D): New.
	(MATCH_FMAXM_D): New.
	(MASK_FMAXM_D): New.
	(MATCH_FROUND_D): New.
	(MASK_FROUND_D): New.
	(MATCH_FROUNDNX_D): New.
	(MASK_FROUNDNX_D): New.
	(MATCH_FLTQ_D): New.
	(MASK_FLTQ_D): New.
	(MATCH_FLEQ_D): New.
	(MASK_FLEQ_D): New.
	(MATCH_FLI_Q): New.
	(MASK_FLI_Q): New.
	(MATCH_FMINM_Q): New.
	(MASK_FMINM_Q): New.
	(MATCH_FMAXM_Q): New.
	(MASK_FMAXM_Q): New.
	(MATCH_FROUND_Q): New.
	(MASK_FROUND_Q): New.
	(MATCH_FROUNDNX_Q): New.
	(MASK_FROUNDNX_Q): New.
	(MATCH_FLTQ_Q): New.
	(MASK_FLTQ_Q): New.
	(MATCH_FLEQ_Q): New.
	(MASK_FLEQ_Q): New.
	(MATCH_FCVTMOD_W_D): New.
	(MASK_FCVTMOD_W_D): New.
	(MATCH_FMVH_X_D): New.
	(MASK_FMVH_X_D): New.
	(MATCH_FMVH_X_Q): New.
	(MASK_FMVH_X_Q): New.
	(MATCH_FMVP_D_X): New.
	(MASK_FMVP_D_X): New.
	(MATCH_FMVP_Q_X): New.
	(MASK_FMVP_Q_X): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction
	classes for the Zfa extension.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add support for
	new format string directive 'Wfv'.
	* riscv-opc.c: Add Zfa instructions.

Co-Developed-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Co-Developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-30 15:56:34 +02:00
mengqinggang
071726dee7 LoongArch: gas: Add LVZ and LBT instructions support
gas/ChangeLog:
	* config/tc-loongarch.c (md_parse_option): Add LARCH_opts.ase_lvz and
	LARCH_opts.ase_lbt.
	* testsuite/gas/loongarch/uleb128.d: Regenerated.
	* testsuite/gas/loongarch/lvz-lbt.d: New test.
	* testsuite/gas/loongarch/lvz-lbt.s: New test.

include/ChangeLog:
	* opcode/loongarch.h (ase_lvz): New.
	(ase_lbt): New.

opcodes/ChangeLog:
	* loongarch-dis.c (set_default_loongarch_dis_options): Add
	LARCH_opts.ase_lvz and LARCH_opts.ase_lbt.
	* loongarch-opc.c (struct loongarch_ase): Add LVZ and LBT instructions.
2023-06-30 17:32:28 +08:00
WANG Xuerui
6637ae9232 LoongArch: Deprecate $v[01], $fv[01] and $x names per spec
As outlined in the LoongArch ELF psABI spec [1], it is actually already
2 versions after the initial LoongArch support, and the $v[01] and
$fv[01] names should really get sunset by now.

In addition, the "$x" name for $r21 was never included in any released
version of the ABI spec, and such usages are all fixed to say just $r21
for every project I could think of that accepted a LoongArch port.

Plus, the upcoming LSX/LASX support makes use of registers named
"$vrNN" and "$xrNN", so having "$vN" and "$x" alongside would almost
certainly create confusion for developers.

Issue warnings for such usages per the deprecation procedure detailed
in the spec, so we can finally remove support in the next release cycle
after this.

[1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html

gas/ChangeLog:

	* config/tc-loongarch.c: Init canonical register ABI name
	mappings and deprecated register names.
	(loongarch_args_parser_can_match_arg_helper): Warn in case of
	deprecated register name usage.
	* testsuite/gas/loongarch/deprecated_reg_aliases.d: New test.
	* testsuite/gas/loongarch/deprecated_reg_aliases.l: Likewise.
	* testsuite/gas/loongarch/deprecated_reg_aliases.s: Likewise.

include/ChangeLog:

	* opcode/loongarch.h: Rename global variables.

opcodes/ChangeLog:

	* loongarch-opc.c: Rename the alternate/deprecated register name
	mappings, and move $x to the deprecated name map.

Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30 10:18:04 +08:00
WANG Xuerui
22be1ca342 opcodes/loongarch: remove unused code
Remove some unused declarations and code.

include/ChangeLog:

	* opcode/loongarch.h: Remove unused declarations.

opcodes/ChangeLog:

	* loongarch-dis.c (loongarch_parse_dis_options): Remove.
	(my_print_address_func): Likewise.
	(loongarch_disassemble_one): Likewise.

Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30 10:17:58 +08:00
WANG Xuerui
17f9439038 LoongArch: support disassembling certain pseudo-instructions
Add a flag in the pinfo field for being able to mark certain specialized
matchers as disassembler-only, so some degree of isolation between
assembler-side and disassembler-side can be achieved.

This isolation is necessary, firstly because some pseudo-instructions
cannot be fully described in the opcode table, like `li.[wd]`, so the
corresponding opcode entry cannot have meaningful match/mask values.
Secondly, some of these pseudo-instructions can be realized in more than
one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can
be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie
disassembly of such aliases with the corresponding GAS support, only one
canonical form among the above would be recognized as `li.w`, and it
would mildly impact the readability of disassembly output.
People wanting the exact disassembly can always set `-M no-aliases` to
get the original behavior back.

In addition, in certain cases, information is irreversibly lost after
assembling, so perfect round-trip would not be possible in such cases.
For example, `li.w` and `li.d` of immediates within int32_t range
produce the same code; in this patch, `addi.d rd, $zero, imm` is treated
as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`,
due to the expressible value range well within 32 bits.

gas/ChangeLog:

	* config/tc-loongarch.c (get_loongarch_opcode): Ignore
	disassembler-only aliases.
	* testsuite/gas/loongarch/64_pcrel.d: Update test case.
	* testsuite/gas/loongarch/imm_ins.d: Likewise.
	* testsuite/gas/loongarch/imm_ins_32.d: Likewise.
	* testsuite/gas/loongarch/jmp_op.d: Likewise.
	* testsuite/gas/loongarch/li.d: Likewise.
	* testsuite/gas/loongarch/macro_op.d: Likewise.
	* testsuite/gas/loongarch/macro_op_32.d: Likewise.
	* testsuite/gas/loongarch/macro_op_large_abs.d: Likewise.
	* testsuite/gas/loongarch/macro_op_large_pc.d: Likewise.
	* testsuite/gas/loongarch/nop.d: Likewise.
	* testsuite/gas/loongarch/relax_align.d: Likewise.
	* testsuite/gas/loongarch/reloc.d: Likewise.

include/ChangeLog:

	* opcode/loongarch.h (INSN_DIS_ALIAS): Add.

ld/ChangeLog:

	* testsuite/ld-loongarch-elf/jmp_op.d: Update test case.
	* testsuite/ld-loongarch-elf/macro_op.d: Likewise.
	* testsuite/ld-loongarch-elf/macro_op_32.d: Likewise.
	* testsuite/ld-loongarch-elf/relax-align.dd: Likewise.

opcodes/ChangeLog:

	* loongarch-dis.c: Move register name map declarations to top.
	(get_loongarch_opcode_by_binfmt): Consider aliases when
	disassembling without the no-aliases option.
	(parse_loongarch_dis_option): Support the no-aliases option.
	* loongarch-opc.c: Collect pseudo instructions into a new
	dedicated table.

Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30 10:17:56 +08:00
Indu Bhagat
ce9a87252c sframe: bfd: gas: ld: format bump to SFrame version 2
SFrame version 2 encodes the size of repetitive insn block explicitly
in the format.  Add information in the SFrame FDE to convey the size
of the block of repeating instructions.  This information is used only
for SFrame FDEs of type SFRAME_FDE_TYPE_PCMASK.

Introduce two extra bytes for padding: this ensures that the memory
accesses to the members of the SFrame Frame Descriptor Entry (FDE) are
naturally aligned.

gas generates SFrame section with version SFRAME_VERSION_2 by default.

libsframe provides two new APIs to:
  - get an SFrame FDE data from the decoder context, and
  - add an SFrame FDE to the encoder context.
The additional argument (for rep_block_size) is useful for SFrame FDEs
where FDE type is SFRAME_FDE_TYPE_PCMASK.

The linker will generate the output SFrame sections in the
SFRAME_VERSION_2 format.  If the input sections offered to the linker
are not all in the SFRAME_VERSION_2 format, the linker issues an error
to the user.

objdump/readelf will show the following message to the user if .sframe
section in SFRAME_VERSION_1 format is seen:

 "No further information can be displayed.  SFrame version not
 supported."

In other words, like the rest of the binutils, only the current SFrame
format version, i.e., SFRAME_VERSION_2 is supported by the textual dump
facilities.

bfd/
	* elf-sframe.c (_bfd_elf_merge_section_sframe): Generate an
	output SFrame section with version SFRAME_VERSION_2.  Also,
	error out if the SFrame sections do not all have
	SFRAME_VERSION_2.
	* elfxx-x86.c (_bfd_x86_elf_create_sframe_plt): Generate SFrame
	section for plt entries with version SFRAME_VERSION_2.
gas/
	* gen-sframe.c (sframe_set_version): Update to SFRAME_VERSION_2.
	(output_sframe): Likewise.
gas/testsuite/
	* gas/cfi-sframe/cfi-sframe-aarch64-1.d: Use SFRAME_VERSION_2.
	* gas/cfi-sframe/cfi-sframe-aarch64-2.d: Likewise.
	* gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.d: Likewise.
	* gas/cfi-sframe/cfi-sframe-common-1.d: Likewise.
	* gas/cfi-sframe/cfi-sframe-common-2.d: Likewise.
	* gas/cfi-sframe/cfi-sframe-common-3.d: Likewise.
	* gas/cfi-sframe/cfi-sframe-common-4.d: Likewise.
	* gas/cfi-sframe/cfi-sframe-common-5.d: Likewise.
	* gas/cfi-sframe/cfi-sframe-common-6.d: Likewise.
	* gas/cfi-sframe/cfi-sframe-common-7.d: Likewise.
	* gas/cfi-sframe/cfi-sframe-common-8.d: Likewise.
	* gas/cfi-sframe/cfi-sframe-x86_64-1.d: Likewise.
	* gas/cfi-sframe/common-empty-1.d: Likewise.
	* gas/cfi-sframe/common-empty-2.d: Likewise.
	* gas/cfi-sframe/common-empty-3.d: Likewise.
ld/testsuite/
	* ld-aarch64/sframe-simple-1.d: Adjust for SFRAME_VERSION_2.
	* ld-x86-64/sframe-plt-1.d: Likewise.
	* ld-x86-64/sframe-simple-1.d: Likewise.
libsframe/
	* libsframe.ver: Add the new APIs.
	* sframe.c (sframe_decoder_get_funcdesc_v2): New definition.
	(sframe_encoder_add_funcdesc_v2): Likewise.
	(sframe_header_sanity_check_p): Include SFRAME_VERSION_2.
	(sframe_fre_check_range_p): Get rep_block_size info from SFrame
	FDE.
	* sframe-dump.c (dump_sframe_header): Add support for
	SFRAME_VERSION_2.
	(dump_sframe): Inform user if SFrame section in SFRAME_VERSION_1
	format is seen.
libsframe/testsuite/
	* libsframe.decode/DATA-BE: Regenerated data file.
	* libsframe.decode/DATA1: Likewise.
	* libsframe.decode/DATA2: Likewise.
	* libsframe.find/plt-findfre-1.c: Use new API in the testcase.
include/
	* sframe.h: Add member to encode size of the code block of
	repeating instructions.  Add 2 bytes of padding.
	* sframe-api.h (sframe_decoder_get_funcdesc_v2): New
	declaration.
	(sframe_encoder_add_funcdesc_v2): Likewise.
2023-06-29 16:31:58 -07:00
Indu Bhagat
9f71b60bd4 libsframe: add new APIs to get SFrame version
While the SFrame preamble is guaranteed to not change between versions,
providing these access APIs from the SFrame decoder and encoder APIs is
for convenience only.  The linker may want to use these APIs as the
format evolves.

include/
	* sframe-api.h (sframe_decoder_get_version): New declaration.
	(sframe_encoder_get_version): Likewise.

libsframe/
	* libsframe/libsframe.ver: Add new APIs.
	* libsframe/sframe.c (sframe_decoder_get_version): New
	definition.
	(sframe_encoder_get_version): Likewise.
2023-06-29 16:28:56 -07:00
Indu Bhagat
3169b734cf libsframe: fix sframe_find_fre for pltN entries
For a toy application on x86_64, for example, following is the SFrame
stack trace information for the 3 pltN entries of 16 bytes each:

   func idx [1]: pc = 0x401030, size = 48 bytes
   STARTPC[m]      CFA       FP        RA
   0000000000000000  sp+8      u         u
   000000000000000b  sp+16     u         u

The data in first column is the start_ip_offset.  Also note that the FDE
is of type SFRAME_FDE_TYPE_PCMASK (denoted by the [m] on LHS).

Where each pltN (note: excluding plt0 entry) entry looks like:

  401030: jmp    *0x2fca(%rip)
  401036: push   $0x0
  40103b: jmp    401020<_init+0x20>

  401040: jmp    *0x2fc2(%rip)
  401046: push   $0x1
  40104b: jmp    401020<_init+0x20>

  401050: jmp    *0x2fba(%rip)
  401056: push   $0x2
  40105b: jmp    401020<_init+0x20>

Now, to find SFrame stack trace information from an FDE of type
SFRAME_FDE_TYPE_PCMASK, sframe_find_fre () was doing an operation
like,
  (start_ip_offset & 0xf) >= (pc & 0xf)

This works for pltN entry of size, say, less than 16 bytes.  But if the
pltN entries or similar code stubs (for which SFrame FDE of type
SFRAME_FDE_TYPE_PCMASK may be used), evolve to be of size > 16 bytes,
this will cease to work.

To match the range covered by the SFrame FRE, one should instead perform
a modulo operation.  The constant for the modulo operation must be the
size of the pltN entry.  Further, this constant should ideally be
encoded in the format, as it may be different for each ABI.

In SFrame Version 2 of the format, we will move towards encoding it
explicitly in the SFrame FDE.  For now, fix up the logic to at least
move towards modulo operation.

libsframe/
	* sframe.c (sframe_fre_check_range_p): New definition.
	(sframe_find_fre): Refactor a bit and use the new definition
	above.
include/
	* sframe.h (SFRAME_FDE_TYPE_PCMASK): Update comment.
libsframe/doc/
	* sframe-spec.texi: Fix the text for SFRAME_FDE_TYPE_PCMASK FDE
	type.
2023-06-29 11:03:32 -07:00
mengqinggang
be1ebb6710 LoongArch: Add R_LARCH_64_PCREL relocation support
Gas defaults to emit R_LARCH_ADD64/R_LARCH_SUB64 unless explcitly declared
  to emit R_LARCH_64_PCREL.

  The LoongArch ABI at here:
    https://github.com/loongson/la-abi-specs/blob/release/la-abi.adoc

bfd/ChangeLog:

	* bfd-in2.h (not): Add R_LARCH_64_PCREL
	* elfnn-loongarch.c (perform_relocation): Likewise.
	* elfxx-loongarch.c: Likewise.
	* libbfd.h: Likewise.
	* reloc.c: Likewise.

gas/ChangeLog:

	* config/tc-loongarch.c (loongarch_args_parser_can_match_arg_helper):
	(md_apply_fix): Add R_LARCH_64_PCREL.
	* testsuite/gas/loongarch/64_pcrel.d: New test.
	* testsuite/gas/loongarch/64_pcrel.s: New test.

include/ChangeLog:

	* elf/loongarch.h (RELOC_NUMBER): Add R_LARCH_64_PCREL.

ld/ChangeLog:

	* testsuite/ld-loongarch-elf/ld-loongarch-elf.exp: Add test.
	* testsuite/ld-loongarch-elf/64_pcrel.d: New test.
	* testsuite/ld-loongarch-elf/64_pcrel.s: New test.
2023-06-28 16:14:35 +08:00
Indu Bhagat
df6f1afb6d libsframe: bfd: use uint32_t for return type of get_num_fidx APIs
Keep the data types usage in libsframe look consistent.

bfd/
	* elf-sframe.c (_bfd_elf_merge_section_sframe): Use uint32_t
	type alias.
	* libsframe/sframe.c (sframe_decoder_get_funcdesc_at_index):
	Likewise.
	(sframe_decoder_get_num_fidx): Likewise.
	(sframe_encoder_get_num_fidx): Likewise.
include/
	* sframe-api.h (sframe_decoder_get_num_fidx): Likewise.
	(sframe_encoder_get_num_fidx): Likewise.
2023-06-27 12:01:56 -07:00
Indu Bhagat
3412dcec61 libsframe: use appropriate data types for args of sframe_encode
include/
	* sframe-api.h (sframe_encode): Use of uint8_t is more
	appropriate.
libsframe/
	* sframe.c (sframe_encode): Likewise.
2023-06-27 12:01:56 -07:00
Indu Bhagat
a9f1da26da libsframe: use uint8_t for return type of sframe_fre_get_base_reg_id
Use a more appropriate data type.

include/
	* sframe-api.h (sframe_fre_get_base_reg_id): Use uint8_t as
	return type.
libsframe/
	* sframe-dump.c (dump_sframe_func_with_fres): Use uint8_t type
	for base reg id.
	* sframe.c (sframe_fre_get_base_reg_id): Use uin8_t as return
	type.
2023-06-27 12:01:56 -07:00
Indu Bhagat
de4879feca libsframe: use uint8_t instead of unsigned char for abi_arch
Use uint8_t consistently for identifying ABI/arch in SFrame format.

bfd/
	* elf-sframe.c (_bfd_elf_merge_section_sframe):
libsframe/
	* sframe-dump.c (is_sframe_abi_arch_aarch64): Use uint8_t for
	local variable.
	* sframe.c (sframe_decoder_get_abi_arch): Update return type to
	uint8_t.
	(sframe_encoder_get_abi_arch): Likewise.
include/
	* sframe-api.h (sframe_decoder_get_abi_arch): Likewise.
	(sframe_encoder_get_abi_arch): Likewise.
2023-06-27 12:01:56 -07:00
Indu Bhagat
49e4485cba libsframe: bfd: use uint32_t for return type of sframe_calc_fre_type
Use uint32_t type alias consistently for all APIs in libsframe.

bfd/
	* elfxx-x86.c (_bfd_x86_elf_create_sframe_plt): Adjust for the
	changed return type.
libsframe/
	* sframe.c (sframe_calc_fre_type): Use uint32_t for return type.
include/
	* sframe-api.h (sframe_calc_fre_type): Likewise.
2023-06-27 12:01:56 -07:00
Indu Bhagat
100d405dae libsframe: use uint32_t for fre_type and fde_type function args
The API sframe_fde_create_func_info is provided by libsframe.  Current
users are the bfd linker.  Adjust the argument type for the variables
carrying the SFrame FRE type and SFrame FDE type to consistenly use
uint32_t type alias.

include/
	* sframe-api.h (sframe_fde_create_func_info): Use uint32_t
	instead of unsigned int.
libsframe/
	* sframe.c (sframe_get_fre_type): Likewise.
	(sframe_get_fde_type): Likewise.
	(flip_fre_start_address): Likewise.
	(sframe_fre_start_addr_size): Likewise.
	(sframe_fre_entry_size): Likewise.
	(flip_fre): Likewise.
	(flip_sframe): Likewise.
	(sframe_fde_create_func_info): Likewise.
	(sframe_calc_fre_type): Likewise.
	(sframe_decode_fre_start_address): Likewise.
	(sframe_decode_fre): Likewise.
	(sframe_find_fre): Likewise.
	(sframe_decoder_get_fre): Likewise.
	(sframe_encoder_add_fre): Likewise.
	(sframe_encoder_write_fre_start_addr): Likewise.
	(sframe_encoder_write_fre): Likewise.
	(sframe_encoder_write_sframe): Likewise.
2023-06-27 12:01:56 -07:00
Indu Bhagat
852bb8c10d libsframe: remove sframe_get_funcdesc_with_addr API
This is an incompatible ABI change in libsframe.

The interface provided by this function is not a healthy abstraction to
expose: the return type sframe_func_desc_entry, which is defined in
include/sframe.h (the SFrame binary format definition).  This ties up
the library in a undesirable way.  Most importantly, this function
should technically not be directly necessary for a stack tracer.  A
stack tracer will likely only need to do a sframe_find_fre ().

Rename the API to continue to use the functionality internally in the
library.  bfd/linker does not use this function.

Change the return type of the previous definition and make a note about
its planned deprecation.

include/
	* sframe-api.h:  Change return type of sframe_get_funcdesc_with_addr.
	Add comment for intention to deprecate.
libsframe/
	*sframe.c (sframe_get_funcdesc_with_addr): Change return type
	and set error code. This API is deprecated.
        (sframe_get_funcdesc_with_addr_internal): New definition for
	internal use.
	(sframe_find_fre): Use sframe_get_funcdesc_with_addr_internal
	instead.
2023-06-27 12:01:56 -07:00
Philipp Tomsich
b625eff8a2 RISC-V: Support Zicond extension
This implements the Zicond (conditional integer operations) extension,
    as of version 1.0-rc2.

    The Zicond extension acts as a building block for branchless sequences
    including conditional-arithmetic, conditional-logic and
    conditional-select/move.
    The following instructions constitute Zicond:
      - czero.eqz rd, rs1, rs2  =>  rd = (rs2 == 0) ? 0 : rs1
      - czero.nez rd, rs1, rs2  =>  rd = (rs2 != 0) ? 0 : rs1

    See
      https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1.0-rc2.pdf
    for the proposed specification and usage details.

    bfd/ChangeLog:

            * elfxx-riscv.c (riscv_multi_subset_supports): Recognize
            INSN_CLASS_ZICOND.
            (riscv_multi_subset_supports_ext): Recognize INSN_CLASS_ZICOND.

    gas/ChangeLog:

            * testsuite/gas/riscv/zicond.d: New test.
            * testsuite/gas/riscv/zicond.s: New test.

    include/ChangeLog:

            * opcode/riscv-opc.h (MATCH_CZERO_EQZ): Define.
            (MASK_CZERO_EQZ): Define.
            (MATCH_CZERO_NEZ): Define,
            (MASK_CZERO_NEZ): Define.
            (DECLARE_INSN): Add czero.eqz and czero.nez.
            * opcode/riscv.h (enum riscv_insn_class): Add
            INSN_CLASS_ZICOND.

    opcodes/ChangeLog:

            * riscv-opc.c: Add czero.eqz and czero.nez.

    Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2023-06-27 07:24:43 -06:00
Feiyang Chen
4142b23683 LoongArch: Support referring to FCSRs as $fcsrX
Previously, FCSRs were referred to as $rX, which seemed strange.
We refer to FCSRs as $fcsrX, which ensures compatibility with LLVM
IAS as well.

gas/ChangeLog:

        * config/tc-loongarch.c:
        (loongarch_fc_normal_name): New definition.
        (loongarch_fc_numeric_name): New definition.
        (loongarch_single_float_opcodes): Modify `movgr2fcsr` and
        `movfcsr2gr`.
        testsuite/gas/loongarch/float_op.d: Likewise.
        testsuite/gas/loongarch/float_op.s: Likewise.

include/ChangeLog:

        * opcode/loongarch.h:
        (loongarch_fc_normal_name): New extern.
        (loongarch_fc_numeric_name): New extern.

opcodes/ChangeLog:

        * opcodes/loongarch-dis.c (loongarch_after_parse_args): Support
        referring to FCSRs as $fcsrX.
        * opcodes/loongarch-opc.c (loongarch_args_parser_can_match_arg_helper):
        Likewise.

Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
2023-06-25 15:06:32 +08:00
David Guillen Fandos
df18f71b56 Add MIPS Allegrex CPU as a MIPS2-based CPU
The Allegrex CPU was created by Sony Interactive Entertainment to power
their portable console, the PlayStation Portable.
The pspdev organization maintains all sorts of tools to create software
for said device including documentation.

Signed-off-by: David Guillen Fandos <david@davidgf.net>
2023-06-15 04:45:03 +01:00
Maciej W. Rozycki
0c5c669cef Revert "MIPS: add MT ASE support for micromips32"
This reverts commit acce83dacf.  It was
applied unapproved.
2023-06-15 04:45:03 +01:00
Maciej W. Rozycki
9cfee3962c Revert "MIPS: sync oprand char usage between mips and micromips"
This reverts commit 5b207b9194.  It was
applied unapproved.
2023-06-15 04:45:03 +01:00
Alan Modra
ce3ab55fa7 ecoff find_nearest_line and final link leaks
Freeing ecoff_debug_info "pointers to the unswapped symbolic info"
isn't a simple matter, due to differing allocation strategies.  In
_bfd_ecoff_slurp_symbolic_info the pointers are to objalloc memory.
In the ecoff linker they are to separately malloc'd memory.  In gas we
have most (obj-elf) or all (obj-ecoff) into a single malloc'd buffer.

This patch fixes the leaks for binutils and ld, leaving the gas leaks
for another day.  The mips elf backend already had this covered, and
the ecoff backend had a pointer, raw_syments used as a flag, so most
of the patch is moving these around a little so they are accessible
for both ecoff and elf.

include/
	* coff/ecoff.h (struct ecoff_debug_info): Add alloc_syments.
bfd/
	* libecoff.h (struct ecoff_tdata): Delete raw_syments.
	* elfxx-mips.c (free_ecoff_debug): Delete.  Replace uses with
	_bfd_ecoff_free_ecoff_debug_info.
	(_bfd_mips_elf_final_link): Init debug.alloc_syments.
	* ecofflink.c (_bfd_ecoff_free_ecoff_debug_info): New function.
	* ecoff.c (_bfd_ecoff_bfd_free_cached_info): Call
	_bfd_ecoff_free_ecoff_debug_info.
	(_bfd_ecoff_slurp_symbolic_info): Replace uses of raw_syments
	with alloc_syments.
	(ecoff_final_link_debug_accumulate): Likewise.  Use
	_bfd_ecoff_free_ecoff_debug_info.
	(_bfd_ecoff_bfd_copy_private_bfd_data): Set alloc_syments for
	copied output.
	* elf64-alpha.c (elf64_alpha_read_ecoff_info): Use
	_bfd_ecoff_free_ecoff_debug_info.
	* libbfd-in.h (_bfd_ecoff_free_ecoff_debug_info): Declare.
	* libbfd.h: Regenerate.
gas/
	* config/obj-ecoff.c (ecoff_frob_file): Set alloc_syments.
	* config/obj-elf.c (elf_frob_file_after_relocs): Likewise.
2023-06-09 12:56:12 +09:30
Indu Bhagat
f4af42724b libsframe: fix cosmetic issues and typos
include/
	* sframe-api.h (sframe_decoder_get_num_fidx): Use extern.
libsframe/
	* sframe-dump.c (dump_sframe_func_with_fres): Fix line length.
	* sframe.c (sframe_frame_row_entry_copy): Likewise.
	(sframe_decode_fre_start_address): Use the intended type uint32_t.
2023-06-06 10:50:07 -07:00
YunQiang Su
5b207b9194 MIPS: sync oprand char usage between mips and micromips
We should try our best to make mips32 using the same
oprand char with micromips. So for mips32, we use:

  ^  is added for 5bit sa oprand for some new DSPr2 instructions:
	APPEND, PREPEND, PRECR_SRA[_R].PH.W
	the LSB bit is 11, like RD.
  +t is removed for coprocessor 0 destination register.
	'E' does the samething.
  +t is now used for RX oprand for MFTR/MTTR (MT ASE)
  ?  is added for sel oprand for MFTR/MTTR (MT ASE)
	For mips32, the position of sel in MFTR/MTTR is same with mfc0 etc,
	while for micromips, they are different.

We also add an extesion format of cftc2/cttc2/mftc2/mfthc2/mttc2/mtthc2:
	concatenating rs with rx as the index of control or data.
2023-06-05 11:14:49 +08:00
YunQiang Su
acce83dacf MIPS: add MT ASE support for micromips32
These instructions are descripted in MD00768.

MIPS® Architecture for Programmers
Volume IV-f: The MIPS® MT Module for
the microMIPS32™ Architecture

Document Number: MD00768
Revision 1.12
July 16, 2013

https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00768-1C-microMIPS32MT-AFP-01.12.pdf
2023-06-05 11:14:46 +08:00
Indu Bhagat
d987df5c95 libsframe: avoid using magic number
Define a new constant for the maximum number of stack offsets handled in
libsframe, and use it.  Note that the SFrame format does not define such
a constant (limit).  This is an implmentation-defined constant in
libsframe.

include/
	* sframe-api.h (MAX_NUM_STACK_OFFSETS): New definition.
libsframe/
	* sframe.c (sframe_fre_sanity_check_p): Use it.
2023-06-01 09:41:04 -07:00
Jim Wilson
ec2260af61 RISC-V: PR30449, Add lga assembler macro support.
Originally discussion, https://github.com/riscv/riscv-isa-manual/pull/539

Added new load address pseudo instruction which is always expanded to GOT
access, no matter the .option rvc is set or not.

gas/
	PR 30449
	* config/tc-riscv.c (macro): Add M_LGA support.
	* testsuite/gas/riscv/la-variants.d: New.
	* testsuite/gas/riscv/la-variants.s: New.
include/
	PR 30449
	* opcode/riscv.h (M_LGA): New.
opcodes/
	PR 30449
	* riscv-opc.c (riscv_opcodes): Add lga support.
2023-06-01 12:25:08 +08:00
mengqinggang
57a930e3bf LoongArch: include: Add support for linker relaxation.
Add relocs and gas LARCH_opts.relax option.

include/ChangeLog:

	* elf/loongarch.h: Add relocs.
	* opcode/loongarch.h: Add LARCH_opts.relax and macro LARCH_NOP.
2023-05-30 19:56:40 +08:00
Alan Modra
20c52e689a Define IMAGE_FILE_MACHINE_ARMNT
Same value as ARMV7PEMAGIC.
https://learn.microsoft.com/en-us/windows/win32/sysinfo/image-file-machine-constants

	* coff/pe.h (IMAGE_FILE_MACHINE_ARMNT): Define.
2023-05-30 12:51:57 +09:30
Alan Modra
e193947c3b Delete include/aout/encap.h
This file is unused and as the header comment says, obsolete.
2023-05-30 12:51:22 +09:30
Andreas Schwab
5fd6b60d86 Remove duplicate definition
* coff/pe.h (IMAGE_FILE_MACHINE_AMD64): Remove duplicate
	definition.  Alphabetize.
2023-05-26 13:12:32 +02:00
Alan Modra
bc227f4ccb Re: readelf: Support SHT_RELR/DT_RELR for -r
Revert value of DT_ENCODING to as it was before commit a7fd118627, and
adjust readelf.

include/
	* elf/common.h (DT_ENCODING): Set back to 32.
binutils/
	* readelf.c (struct filedata): Don't size dynamic_info array
	using DT_ENCODING.
2023-05-22 17:25:36 +09:30
Kuan-Lin Chen
f1cd8b94e7 RISC-V: Support subtraction of .uleb128.
96d6e190e9

There are some known limitations for now,

* Do not shrink the length of the uleb128 value, even if the value is reduced
after relaxations.  Also reports error if the length grows up.

* The R_RISCV_SET_ULEB128 needs to be paired with and be placed before the
R_RISCV_SUB_ULEB128.

bfd/
	* bfd-in2.h: Regenerated.
	* elfnn-riscv.c (perform_relocation): Perform R_RISCV_SUB_ULEB128 and
	R_RISCV_SET_ULEB128 relocations.  Do not shrink the length of the
	uleb128 value, and report error if the length grows up.  Called the
	generic functions, _bfd_read_unsigned_leb128 and _bfd_write_unsigned_leb128,
	to encode the uleb128 into the section contents.
	(riscv_elf_relocate_section): Make sure that the R_RISCV_SET_ULEB128
	must be paired with and be placed before the R_RISCV_SUB_ULEB128.
	* elfxx-riscv.c (howto_table): Added R_RISCV_SUB_ULEB128 and
	R_RISCV_SET_ULEB128.
	(riscv_reloc_map): Likewise.
	(riscv_elf_ignore_reloc): New function.
	* libbfd.h: Regenerated.
	* reloc.c (BFD_RELOC_RISCV_SET_ULEB128, BFD_RELOC_RISCV_SUB_ULEB128):
	New relocations to support .uleb128 subtraction.
gas/
	* config/tc-riscv.c (md_apply_fix): Added BFD_RELOC_RISCV_SET_ULEB128
	and BFD_RELOC_RISCV_SUB_ULEB128.
	(s_riscv_leb128): Updated to allow uleb128 subtraction.
	(riscv_insert_uleb128_fixes): New function, scan uleb128 subtraction
	expressions and insert fixups for them.
	(riscv_md_finish): Called riscv_insert_uleb128_fixes for all sections.
include/
	* elf/riscv.h ((R_RISCV_SET_ULEB128, (R_RISCV_SUB_ULEB128): Defined.
ld/
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
	* testsuite/ld-riscv-elf/uleb128*: New testcase for uleb128 subtraction.
binutils/
	* testsuite/binutils-all/nm.exp: Updated since RISCV supports .uleb128.
2023-05-19 16:24:10 +08:00
Alan Modra
80b6c32f23 PR29961, plugin-api.h: "Could not detect architecture endianess"
Found when attempting to build binutils on sparc sunos-5.8 where
sys/byteorder.h defines _BIG_ENDIAN but not any of the BYTE_ORDER
variants.  This patch adds the extra tests to cope with the old
machine, and tidies the header a little.

	PR 29961
	plugin-api.h: When handling non-gcc or gcc < 4.6.0 include
	necessary header files before testing macros.  Make more use
	of #elif.  Test _LITTLE_ENDIAN and _BIG_ENDIAN in final tests.
2023-05-17 11:21:43 +09:30
Alan Modra
3318d80021 gcc-4.5 build fixes
Trying to build binutils with an older gcc currently fails.  Working
around these gcc bugs is not onerous so let's fix them.

bfd/
	* elf32-csky.c (csky_elf_size_dynamic_sections): Don't type-pun
	pointer.
	* elf32-rl78.c (rl78_compute_complex_reloc): Rename "stat"
	variable to "status".
gas/
	* compress-debug.c (compress_finish): Supply all fields in
	ZSTD_inBuffer initialisation.
include/
	* xtensa-dynconfig.h (xtensa_isa_internal): Delete unnecessary
	forward declaration.
opcodes/
	* loongarch-opc.c: Supply all fields of zero struct initialisation
	in various opcode tables.
2023-05-17 11:21:43 +09:30
Joseph Myers
b21318bd2c Add LDPT_REGISTER_CLAIM_FILE_HOOK_V2 linker plugin hook [GCC PR109128]
This is one part of the fix for GCC PR109128, along with a
corresponding GCC change.  Without this patch, what happens in the
linker, when an unused object in a .a file has offload data, is that
elf_link_is_defined_archive_symbol calls bfd_link_plugin_object_p,
which ends up calling the plugin's claim_file_handler, which then
records the object as one with offload data. That is, the linker never
decides to use the object in the first place, but use of this _p
interface (called as part of trying to decide whether to use the
object) results in the plugin deciding to use its offload data (and a
consequent mismatch in the offload data present at runtime).

The new hook allows the linker plugin to distinguish calls to
claim_file_handler that know the object is being used by the linker
(from ldmain.c:add_archive_element), from calls that don't know it's
being used by the linker (from elf_link_is_defined_archive_symbol); in
the latter case, the plugin should avoid recording the object as one
with offload data.

	bfd/
	* plugin.c (struct plugin_list_entry): Add claim_file_v2.
	(register_claim_file_v2): New.
	(try_load_plugin): Use LDPT_REGISTER_CLAIM_FILE_HOOK_V2.
	(ld_plugin_object_p): Take second argument.
	(bfd_link_plugin_object_p): Update call to ld_plugin_object_p.
	(register_ld_plugin_object_p): Update argument prototype.
	(bfd_plugin_object_p): Update call to ld_plugin_object_p.
	* plugin.h (register_ld_plugin_object_p): Update argument
	prototype.

	include/
	* plugin.api.h (ld_plugin_claim_file_handler_v2)
	(ld_plugin_register_claim_file_v2)
	(LDPT_REGISTER_CLAIM_FILE_HOOK_V2): New.
	(struct ld_plugin_tv): Add tv_register_claim_file_v2.

	ld/
	* plugin.c (struct plugin): Add claim_file_handler_v2.
	(LDPT_REGISTER_CLAIM_FILE_HOOK_V2): New.
	(plugin_object_p): Add second argument.  Update call to
	plugin_call_claim_file.
	(register_claim_file_v2): New.
	(set_tv_header): Handle LDPT_REGISTER_CLAIM_FILE_HOOK_V2.
	(plugin_call_claim_file): Add argument known_used.
	(plugin_maybe_claim): Update call to plugin_object_p.
	* testplug.c, testplug2.c, testplug3.c, testplug4.c: Handle
	LDPT_REGISTER_CLAIM_FILE_HOOK_V2.
	* testsuite/ld-plugin/plugin-1.d, testsuite/ld-plugin/plugin-10.d,
	testsuite/ld-plugin/plugin-11.d, testsuite/ld-plugin/plugin-13.d,
	testsuite/ld-plugin/plugin-14.d, testsuite/ld-plugin/plugin-15.d,
	testsuite/ld-plugin/plugin-16.d, testsuite/ld-plugin/plugin-17.d,
	testsuite/ld-plugin/plugin-18.d, testsuite/ld-plugin/plugin-19.d,
	testsuite/ld-plugin/plugin-2.d, testsuite/ld-plugin/plugin-26.d,
	testsuite/ld-plugin/plugin-3.d, testsuite/ld-plugin/plugin-30.d,
	testsuite/ld-plugin/plugin-4.d, testsuite/ld-plugin/plugin-5.d,
	testsuite/ld-plugin/plugin-6.d, testsuite/ld-plugin/plugin-7.d,
	testsuite/ld-plugin/plugin-8.d, testsuite/ld-plugin/plugin-9.d:
	Update test expectations.
2023-05-11 14:31:09 +00:00
Alan Modra
143a12bd5a Re: Keeping track of rs6000-coff archive element pointers
Commit de7b90610e left a hole in the element checking, explained by
the comment added to _bfd_xcoff_openr_next_archived_file.  While
fixing this, tidy some types used to hold unsigned values so that
casts are not needed to avoid signed/unsigned comparison warnings.
Also tidy a few things in xcoff.h.

bfd/
	* coff-rs6000.c (_bfd_xcoff_openr_next_archived_file): Check
	that we aren't pointing back at the last element.  Make
	filestart a ufile_ptr.  Update for xcoff_artdata change.
	(_bfd_strntol, _bfd_strntoll): Return unsigned values.
	(_bfd_xcoff_slurp_armap): Make off a ufile_ptr.
	(add_ranges): Update for xcoff_artdata change.
	* libbfd-in.h (struct artdata): Make first_file_filepos a
	ufile_ptr.
	* libbfd.h: Regenerate.
include/
	* coff/xcoff.h (struct xcoff_artdata): Replace min_elt with
	ar_hdr_size.
	(xcoff_big_format_p): In the !SMALL_ARCHIVE case return true
	for anything but a small archive.
2023-04-28 15:19:59 +09:30
Philipp Tomsich
1656d3f8ef RISC-V: Support XVentanaCondOps extension
Ventana Micro has published the specification for their
    XVentanaCondOps ("conditional ops") extension at
      https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
    which contains two new instructions
      - vt.maskc
      - vt.maskcn
    that can be used in constructing branchless sequences for
    various conditional-arithmetic, conditional-logical, and
    conditional-select operations.

    To support such vendor-defined instructions in the mainline binutils,
    this change also adds a riscv_supported_vendor_x_ext secondary
    dispatch table (but also keeps the behaviour of allowing any unknow
    X-extension to be specified in addition to the known ones from this
    table).

    As discussed, this change already includes the planned/agreed future
    requirements for X-extensions (which are likely to be captured in the
    riscv-toolchain-conventions repository):
      - a public specification document is available (see above) and is
        referenced from the gas-documentation
      - the naming follows chapter 27 of the RISC-V ISA specification
      - instructions are prefixed by a vendor-prefix (vt for Ventana)
        to ensure that they neither conflict with future standard
        extensions nor clash with other vendors

    bfd/ChangeLog:

            * elfxx-riscv.c (riscv_get_default_ext_version): Add riscv_supported_vendor_x_ext.
            (riscv_multi_subset_supports): Recognize INSN_CLASS_XVENTANACONDOPS.

    gas/ChangeLog:

            * doc/c-riscv.texi: Add section to list custom extensions and
              their documentation URLs.
            * testsuite/gas/riscv/x-ventana-condops.d: New test.
            * testsuite/gas/riscv/x-ventana-condops.s: New test.

    include/ChangeLog:

            * opcode/riscv-opc.h Add vt.maskc and vt.maskcn.
            * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_XVENTANACONDOPS.

    opcodes/ChangeLog:

            * riscv-opc.c: Add vt.maskc and vt.maskcn.

    Series-version: 1
    Series-to: binutils@sourceware.org
    Series-cc: Kito Cheng <kito.cheng@sifive.com>
    Series-cc: Nelson Chu <nelson.chu@sifive.com>
    Series-cc: Greg Favor <gfavor@ventanamicro.com>
    Series-cc: Christoph Muellner <cmuellner@gcc.gnu.org>
2023-04-26 14:09:34 -06:00
Alan Modra
de7b90610e Keeping track of rs6000-coff archive element pointers
rs6000-coff archives use a linked list of file offsets, where each
element points to the next element.  The idea is to allow updating of
large archives quickly without rewriting the whole archive.  (binutils
ar does not do this.)  Unfortunately this is an easy target for
fuzzers to create an archive that will cause ar or any other tool
processing archives to hang.  I'd implemented guards against pointing
back to the previous element, but of course that didn't last long.

So this patch implements a scheme to keep track of file offset ranges
used by elements as _bfd_read_ar_hdr is called for each element.  See
the add_range function comment.  I needed a place to stash the list,
so chose the obvious artdata.tdata backend extension to archive's
tdata, already used by xcoff.  That involved a little cleanup, because
while it would be possible to continue using different artdata.tdata
for the big and small archives, it's nicer to use a union.

If anyone is concerned this list of element ranges might grow large
and thus significantly slow down the tools, adjacent ranges are
merged.  In fact something like "ar t" will only ever have one range
on xcoff archives generated by binutils/ar.  I agree there might still
be a problem with ld random element access via the armap.

include/
	* coff/xcoff.h (SIZEOF_AR_FILE_HDR): Use sizeof.
	(SIZEOF_AR_FILE_HDR_BIG, SIZEOF_AR_HDR, SIZEOF_AR_HDR_BIG): Likewise.
	(struct ar_ranges, struct xcoff_artdata): New.
	(x_artdata): Define.
	(xcoff_big_format_p): Rewrite.
	(xcoff_ardata, xcoff_ardata_big): Delete.
bfd/
	* coff-rs6000.c: Replace uses of xcoff_ardata and
	xcoff_ardata_big throughout file.
	(_bfd_xcoff_archive_p): Adjust artdata.tdata allocation.
	(add_range): New function.
	(_bfd_xcoff_read_ar_hdr): Use it here.  Fix memory leak.
	(_bfd_xcoff_openr_next_archived_file): Remove old sanity
	checks.  Set up range for header.
	(xcoff_write_archive_contents_old): Make the temporary
	artdata.tdata used here to pass info down to
	_bfd_compute_and_write_armap a struct xcoff_artdata.
	(xcoff_write_archive_contents_big): Likewise.
	* coff64-rs6000.c: Replace uses of xcoff_ardata and
	xcoff_ardata_big throughout file.
	(xcoff64_archive_p): Adjust artdata.tdata allocation.
2023-04-21 11:51:06 +09:30
Indu Bhagat
8bb878b777 sframe: correct some typos
include/
	* sframe.h: Correct a typo.

libsframe/
	* sframe.c: Likewise.
2023-04-19 14:37:59 -07:00
Richard Sandiford
d056265349 aarch64: Remove stray reglist variable
Sorry for not catching this during testing.  I was using a
host compiler that predated the switch to -fno-common.
2023-03-30 17:01:30 +01:00
Richard Sandiford
8ff429203d aarch64: Add the RPRFM instruction
This patch adds the RPRFM (range prefetch) instruction.
It was introduced as part of SME2, but it belongs to the
prefetch hint space and so doesn't require any specific
ISA flags.

The aarch64_rprfmop_array initialiser (deliberately) only
fills in the leading non-null elements.
2023-03-30 11:09:18 +01:00
Richard Sandiford
dfc12f9f53 aarch64: Add new SVE dot-product instructions
This patch adds the SVE FDOT, SDOT and UDOT instructions,
which are available when FEAT_SME2 is implemented.  The patch
also reorders the existing SVE_Zm3_22_INDEX to keep the
operands numerically sorted.
2023-03-30 11:09:17 +01:00
Richard Sandiford
6efa660124 aarch64: Add the SME2 shift instructions
There are two instruction formats here:

- SQRSHR, SQRSHRU and UQRSHR, which operate on lists of two
  or four registers.

- SQRSHRN, SQRSHRUN and UQRSHRN, which operate on lists of
  four registers.

These are the first SME2 instructions to have immediate operands.
The patch makes sure that, when parsing SME2 instructions with
immediate operands, the new predicate-as-counter registers are
parsed as registers rather than as #-less immediates.
2023-03-30 11:09:16 +01:00
Richard Sandiford
ce623e7aa4 aarch64: Add the SME2 saturating conversion instructions
There are two instruction formats here:

- SQCVT, SQCVTU and UQCVT, which operate on lists of two or
  four registers.

- SQCVTN, SQCVTUN and UQCVTN, which operate on lists of
  four registers.
2023-03-30 11:09:16 +01:00
Richard Sandiford
a8cb21aa06 aarch64: Add the SME2 MLALL and MLSLL instructions
SMLALL, SMLSLL, UMLALL and UMLSLL have the same format.
USMLALL and SUMLALL allow the same operand types as those
instructions, except that SUMLALL does not have the multi-vector
x multi-vector forms (which would be redundant with USMLALL).
2023-03-30 11:09:14 +01:00
Richard Sandiford
ed429b33c1 aarch64: Add the SME2 MLAL and MLSL instructions
The {BF,F,S,U}MLAL and {BF,F,S,U}MLSL instructions share the same
encoding.  They are the first instance of a ZA (as opposed to ZA tile)
operand having a range of offsets.  As with ZA tiles, the expected
range size is encoded in the operand-specific data field.
2023-03-30 11:09:13 +01:00
Richard Sandiford
80752eb098 aarch64: Add the SME2 FMLA and FMLS instructions 2023-03-30 11:09:13 +01:00
Richard Sandiford
27f6a0bd65 aarch64: Add the SME2 maximum/minimum instructions
This patch adds the SME2 multi-register forms of F{MAX,MIN}{,NM}
and {S,U}{MAX,MIN}.  SQDMULH, SRSHL and URSHL have the same form
as SMAX etc., so the patch adds them too.
2023-03-30 11:09:13 +01:00
Richard Sandiford
e87ff6724f aarch64: Add the SME2 ADD and SUB instructions
Add support for the SME2 ADD. SUB, FADD and FSUB instructions.
SUB and FSUB have the same form as ADD and FADD, except that
ADD also has a 2-operand accumulating form.

The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the
64-bit FADD/FSUB instructions require FEAT_SME_F64F64.

These are the first instructions to have tied register list
operands, as opposed to tied single registers.

The parse_operands change prevents unsuffixed Z registers (width==-1)
from being treated as though they had an Advanced SIMD-style suffix
(.4s etc.).  It means that:

  Error: expected element type rather than vector type at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'

becomes:

  Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'
2023-03-30 11:09:13 +01:00
Richard Sandiford
cbd11b8818 aarch64: Add the SME2 ZT0 instructions
SME2 adds lookup table instructions for quantisation.  They use
a new lookup table register called ZT0.

LUTI2 takes an unsuffixed SVE vector index of the form Zn[<imm>],
which is the first time that this syntax has been used.
2023-03-30 11:09:12 +01:00
Richard Sandiford
99e01a66b4 aarch64: Add the SME2 predicate-related instructions
Implementation-wise, the main things to note here are:

- the WHILE* instructions have forms that return a pair of predicate
  registers.  This is the first time that we've had lists of predicate
  registers, and they wrap around after register 15 rather than after
  register 31.

- the predicate-as-counter WHILE* instructions have a fourth operand
  that specifies the vector length.  We can treat this as an enumeration,
  except that immediate values aren't allowed.

- PEXT takes an unsuffixed predicate index of the form PN<n>[<imm>].
  This is the first instance of a vector/predicate index having
  no suffix.
2023-03-30 11:09:12 +01:00
Richard Sandiford
b408ebbf52 aarch64: Add the SME2 multivector LD1 and ST1 instructions
SME2 adds LD1 and ST1 variants for lists of 2 and 4 registers.
The registers can be consecutive or strided.  In the strided case,
2-register lists have a stride of 8, starting at register x0xxx.
4-register lists have a stride of 4, starting at register x00xx.

The instructions are predicated on a predicate-as-counter register in
the range pn8-pn15.  Although we already had register fields with upper
bounds of 7 and 15, this is the first plain register operand to have a
nonzero lower bound.  The patch uses the operand-specific data field
to record the minimum value, rather than having separate inserters
and extractors for each lower bound.  This in turn required adding
an extra bit to the field.
2023-03-30 11:09:12 +01:00
Richard Sandiford
d8773a8a5f aarch64: Add the SME2 MOVA instructions
SME2 defines new MOVA instructions for moving multiple registers
to and from ZA.  As with SME, the instructions are also available
through MOV aliases.

One notable feature of these instructions (and many other SME2
instructions) is that some register lists must start at a multiple
of the list's size.  The patch uses the general error "start register
out of range" when this constraint isn't met, rather than an error
specifically about multiples.  This ensures that the error is
consistent between these simple consecutive lists and later
strided lists, for which the requirements aren't a simple multiple.
2023-03-30 11:09:12 +01:00
Richard Sandiford
503fae1299 aarch64: Add support for predicate-as-counter registers
SME2 adds a new format for the existing SVE predicate registers:
predicates as counters rather than predicates as masks.  In assembly
code, operands that interpret predicates as counters are written
pn<N> rather than p<N>.

This patch adds support for these registers and extends some
existing instructions to support them.  Since the new forms
are just a programmer convenience, there's no need to make them
more restrictive than the earlier predicate-as-mask forms.
2023-03-30 11:09:11 +01:00
Richard Sandiford
586c62819f aarch64; Add support for vector offset ranges
Some SME2 instructions operate on a range of consecutive ZA vectors.
This is indicated by syntax such as:

   za[<Wv>, <imml>:<immh>]

Like with the earlier vgx2 and vgx4 support, we get better error
messages if the parser allows all ZA indices to have a range.
We can then reject invalid cases during constraint checking.
2023-03-30 11:09:11 +01:00
Richard Sandiford
e2dc4040f3 aarch64: Add support for vgx2 and vgx4
Many SME2 instructions operate on groups of 2 or 4 ZA vectors.
This is indicated by adding a "vgx2" or "vgx4" group size to the
ZA index.  The group size is optional in assembly but preferred
for disassembly.

There is not a binary distinction between mnemonics that have
group sizes and mnemonics that don't, nor between mnemonics that
take vgx2 and mnemonics that take vgx4.  We therefore get better
error messages if we allow any ZA index to have a group size
during parsing, and wait until constraint checking to reject
invalid sizes.

A quirk of the way errors are reported means that if an instruction
is wrong both in its qualifiers and its use of a group size, we'll
print suggested alternative instructions that also have an incorrect
group size.  But that's a general property that also applies to
things like out-of-range immediates.  It's also not obviously the
wrong thing to do.  We need to be relatively confident that we're
looking at the right opcode before reporting detailed operand-specific
errors, so doing qualifier checking first seems resonable.
2023-03-30 11:09:11 +01:00
Richard Sandiford
90cd80f8c2 aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array
SME2 adds various new fields that are similar to
AARCH64_OPND_SME_ZA_array, but are distinguished by the size of
their offset fields.  This patch adds _off4 to the name of the
field that we already have.
2023-03-30 11:09:11 +01:00
Richard Sandiford
60336e1965 aarch64: Add +sme2
This patch adds bare-bones support for +sme2.  Later patches
fill in the rest.
2023-03-30 11:09:10 +01:00
Richard Sandiford
f5b57feac2 aarch64: Add support for strided register lists
SME2 has instructions that accept strided register lists,
such as { z0.s, z4.s, z8.s, z12.s }.  The purpose of this
patch is to extend binutils to support such lists.

The parsing code already had (unused) support for strides of 2.
The idea here is instead to accept all strides during parsing
and reject invalid strides during constraint checking.

The SME2 instructions that accept strided operands also have
non-strided forms.  The errors about invalid strides therefore
take a bitmask of acceptable strides, which allows multiple
possibilities to be summed up in a single message.

I've tried to update all code that handles register lists.
2023-03-30 11:09:10 +01:00
Richard Sandiford
199cfcc475 aarch64: Add a aarch64_cpu_supports_inst_p helper
Quite a lot of SME2 instructions have an opcode bit that selects
between 32-bit and 64-bit forms of an instruction, with the 32-bit
forms being part of base SME2 and with the 64-bit forms being part
of an optional extension.  It's nevertheless useful to have a single
opcode entry for both forms since (a) that matches the ISA definition
and (b) it tends to improve error reporting.

This patch therefore adds a libopcodes function called
aarch64_cpu_supports_inst_p that tests whether the target
supports a particular instruction.  In future it will depend
on internal libopcodes routines.
2023-03-30 11:09:09 +01:00
Richard Sandiford
db3c06bf93 aarch64: Add an operand class for SVE register lists
SVE register lists were classified as SVE_REG, since there had been
no particular reason to separate them out.  However, some SME2
instructions have tied register list operands, and so we need to
distinguish registers and register lists when checking whether two
operands match.

Also, the register list operands used a general error message,
even though we already have a dedicated error code for register
lists that are the wrong length.
2023-03-30 11:09:07 +01:00
Richard Sandiford
859f51df4d aarch64: Add an error code for out-of-range registers
libopcodes currently reports out-of-range registers as a general
AARCH64_OPDE_OTHER_ERROR.  However, this means that each register
range needs its own hard-coded string, which is a bit cumbersome
if the range is determined programmatically.  This patch therefore
adds a dedicated error type for out-of-range errors.
2023-03-30 11:09:07 +01:00
Richard Sandiford
36043bcff4 aarch64: Deprioritise AARCH64_OPDE_REG_LIST
SME2 has many instructions that take a list of SVE registers.
There are often multiple forms, with different forms taking
different numbers of registers.

This means that if, after a successful parse and qualifier match,
we find that the number of registers does not match the opcode entry,
the associated error should have a lower priority/severity than other
errors reported at the same stage.  For example, if there are 2-register
and 4-register forms of an instruction, and if the assembly code uses
the 2-register form with an out-of-range value, the out-of-range value
error against the 2-register instruction should have a higher priority
than the "wrong number of registers" error against the 4-register
instruction.

This is tested by the main SME2 patches, but seemed worth splitting out.
2023-03-30 11:09:07 +01:00
Richard Sandiford
c1817dc2ee aarch64: Update operand_mismatch_kind_names
The contents of operand_mismatch_kind_names were out of sync
with the enum.
2023-03-30 11:09:07 +01:00
Richard Sandiford
ff60bcbfbe aarch64: Move ZA range checks to aarch64-opc.c
This patch moves the range checks on ZA vector select offsets from
gas to libopcodes.  Doing the checks there means that the error
messages contain the expected range.  It also fits in better
with the error severity scheme, which becomes important later.
(This is because out-of-range indices are treated as more severe than
syntax errors, on the basis that parsing must have succeeded if we get
to the point of checking the completed opcode.)

The patch also adds a new check_za_access function for checking
ZA accesses.  That's a bit over the top for one offset check, but the
function becomes more complex with later patches.

sme-9-illegal.s checked for an invalid .q suffix using:

  psel p1, p15, p3.q[w15]

but this is doubly invalid because it misses the immediate part
of the index.  The patch keeps that test but adds another with
a zero index, so that .q is the only thing wrong.

The aarch64-tbl.h change includes neatening up the backslash
positions.
2023-03-30 11:09:05 +01:00
Richard Sandiford
c888354c61 aarch64: Make indexed_za use 64-bit immediates
A later patch moves the range checking for ZA vector select
offsets from gas to libopcodes.  That in turn requires the
immediate field to be big enough to support all parsed values.

This shouldn't be a particularly size-sensitive structure,
so there should be no memory problems with doing this.
2023-03-30 11:09:04 +01:00
Richard Sandiford
575c497a4a aarch64: Rename za_tile_vector to za_index
za_tile_vector is also used for indexing ZA as a whole, rather than
just for indexing tiles.  The former is more common than the latter
in SME2, so this patch generalises the name to "indexed_za".

The patch also names the associated structure, so that later patches
can reuse it during parsing.
2023-03-30 11:09:04 +01:00
Richard Sandiford
a5791d5814 aarch64: Make SME instructions use F_STRICT
This patch makes all SME instructions use F_STRICT, so that qualifiers
have to be provided explicitly rather than being inferred from other
operands.  The main change is to move the qualifier setting from the
operand-level decoders to the opcode level.

This is one step towards consolidating the ZA parsing code and
extending it to handle SME2.
2023-03-30 11:09:02 +01:00
Richard Sandiford
78addeae53 aarch64: Add sme-i16i64 and sme-f64f64 aliases
Most extension flags are named after the associated architectural
FEAT_* flags, but sme-i64 and sme-f64 were exceptions.  This patch
adds sme-i16i64 and sme-f64f64 aliases, but keeps the old names too
for compatibility.
2023-03-30 11:09:01 +01:00
Alan Modra
a2c7ca15a5 Use stdint types in coff internal_auxent
long is a poor choice of type to store 32-bit values read from
objects files by H_GET_32.  H_GET_32 doesn't sign extend so tests like
that in gdb/coffread.c for "negative" values won't work if long is
larger than 32 bits.  If long is 32-bit then code needs to be careful
to not accidentally index negative array elements.  (I'd rather see a
segfault on an unmapped 4G array index than silently reading bogus
data.)  long is also a poor choice for x_sect.s_scnlen, which might
have 64-bit values.  It's better to use unsigned exact width types to
avoid surprises.

I decided to change the field names too, which makes most of this
patch simply renaming.  Besides that there are a few places where
casts are no longer needed, and where printf format strings or tests
need adjusting.

include/
	* coff/internal.h (union internal_auxent): Use unsigned stdint
	types.  Rename l fields to u32 and u64 as appropriate.
bfd/
	* coff-bfd.c,
	* coff-rs6000.c,
	* coff64-rs6000.c,
	* coffcode.h,
	* coffgen.c,
	* cofflink.c,
	* coffswap.h,
	* peXXigen.c,
	* xcofflink.c: Adjust to suit internal_auxent changes.
binutils/
	* rdcoff.c: Adjust to suit internal_auxent changes.
gas/
	* config/obj-coff.h,
	* config/tc-ppc.c: Adjust to suit internal_auxent changes.
gdb/
	* coffread.c,
	* xcoffread.c: Adjust to suit internal_auxent changes.
ld/
	* pe-dll.c: Adjust to suit internal_auxent changes.
2023-03-27 21:58:46 +10:30
Frederic Cambus
80251d4185 Add support to readelf for the PT_OPENBSD_MUTABLE segment type.
binutils * readelf.c (get_segment_type): Handle PT_OPENBSD_MUTABLE segment type.
include  * elf/common.h (PT_OPENBSD_MUTABLE): Define.
2023-03-23 15:19:38 +00:00
Clément Chigot
e263a66b01 readelf: add support for QNT_STACK note subsections
QNX provides some .note subsections. QNT_STACK is the one controling
the stack allocation.

bfd/ChangeLog:

	* elf.c (BFD_QNT_CORE_INFO): Delete.
	(BFD_QNT_CORE_STATUS): Likewise.
	(BFD_QNT_CORE_GREG): Likewise.
	(BFD_QNT_CORE_FPREG): Likewise.
	(elfcore_grok_nto_note): Replace BFD_QNT_* by QNT_*.

binutils/ChangeLog:

	* readelf.c (get_qnx_elfcore_note_type): New function.
	(print_qnx_note): New function.
	(process_note): Add support for QNX support.

include/ChangeLog:

	* elf/common.h (QNT_DEBUG_FULLPATH): New define.
	(QNT_DEBUG_RELOC): New define.
	(QNT_STACK): New define.
	(QNT_GENERATOR): New define.
	(QNT_DEFAULT_LIB): New define.
	(QNT_CORE_SYSINFO): New define.
	(QNT_CORE_INFO): New define.
	(QNT_CORE_STATUS): New define.
	(QNT_CORE_GREG): New define.
	(QNT_CORE_FPREG): New define.
	(QNT_LINK_MAP): New define.
2023-03-16 15:01:05 +01:00
Cupertino Miranda
5e4c7a839d BPF relocations review / refactoring
- Removed not needed relocations.
- Renamed relocations to match llvm and linux kernel.

Relocation changes:
  R_BPF_INSN_64 	=> R_BPF_64_64
  R_BPF_INSN_DISP32 	=> R_BPF_64_32
  R_BPF_DATA_32 	=> R_BPF_64_ABS32
  R_BPF_DATA_64 	=> R_BPF_64_ABS64

ChangeLog:

  * bfd/bpf-reloc.def: Created file with BPF_HOWTO macro entries.
  * bfd/reloc.c: Removed non needed relocations.
  * bfd/bfd-in2.h: regenerated.
  * bfd/libbfd.h: regenerated.
  * bfd/elf64-bpf.c: Changed relocations.
  * include/elf/bpf.h: Adapted relocation values/names.
  * gas/config/tc-bpf.c: Changed relocation mapping.
2023-03-16 09:11:09 +00:00
Simon Marchi
ae61525fcf gdbsupport: ignore -Wenum-constexpr-conversion in enum-flags.h
When building with clang 16, we get:

      CXX    gdb.o
    In file included from /home/smarchi/src/binutils-gdb/gdb/gdb.c:19:
    In file included from /home/smarchi/src/binutils-gdb/gdb/defs.h:65:
    /home/smarchi/src/binutils-gdb/gdb/../gdbsupport/enum-flags.h:95:52: error: integer value -1 is outside the valid range of values [0, 15] for this enumeration type [-Wenum-constexpr-conversion]
        integer_for_size<sizeof (T), static_cast<bool>(T (-1) < T (0))>::type
                                                       ^

The error message does not make it clear in the context of which enum
flag this fails (i.e. what is T in this context), but it doesn't really
matter, we have similar warning/errors for many of them, if we let the
build go through.

clang is right that the value -1 is invalid for the enum type we cast -1
to.  However, we do need this expression in order to select an integer
type with the appropriate signedness.  That is, with the same signedness
as the underlying type of the enum.

I first wondered if that was really needed, if we couldn't use
std::underlying_type for that.  It turns out that the comment just above
says:

    /* Note that std::underlying_type<enum_type> is not what we want here,
       since that returns unsigned int even when the enum decays to signed
       int.  */

I was surprised, because std::is_signed<std::underlying_type<enum_type>>
returns the right thing.  So I tried replacing all this with
std::underlying_type, see if that would work.  Doing so causes some
build failures in unittests/enum-flags-selftests.c:

      CXX    unittests/enum-flags-selftests.o
    /home/smarchi/src/binutils-gdb/gdb/unittests/enum-flags-selftests.c:254:1: error: static assertion failed due to requirement 'gdb::is_same<selftests::enum_flags_tests::check_valid_expr254::archetype<enum_flags<s
    elftests::enum_flags_tests::RE>, selftests::enum_flags_tests::RE, enum_flags<selftests::enum_flags_tests::RE2>, selftests::enum_flags_tests::RE2, enum_flags<selftests::enum_flags_tests::URE>, selftests::enum_fla
    gs_tests::URE, int>, selftests::enum_flags_tests::check_valid_expr254::archetype<enum_flags<selftests::enum_flags_tests::RE>, selftests::enum_flags_tests::RE, enum_flags<selftests::enum_flags_tests::RE2>, selfte
    sts::enum_flags_tests::RE2, enum_flags<selftests::enum_flags_tests::URE>, selftests::enum_flags_tests::URE, unsigned int>>::value == true':
    CHECK_VALID (true,  int,  true ? EF () : EF2 ())
    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    /home/smarchi/src/binutils-gdb/gdb/unittests/enum-flags-selftests.c:91:3: note: expanded from macro 'CHECK_VALID'
      CHECK_VALID_EXPR_6 (EF, RE, EF2, RE2, UEF, URE, VALID, EXPR_TYPE, EXPR)
      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    /home/smarchi/src/binutils-gdb/gdb/../gdbsupport/valid-expr.h:105:3: note: expanded from macro 'CHECK_VALID_EXPR_6'
      CHECK_VALID_EXPR_INT (ESC_PARENS (typename T1, typename T2,           \
      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    /home/smarchi/src/binutils-gdb/gdb/../gdbsupport/valid-expr.h:66:3: note: expanded from macro 'CHECK_VALID_EXPR_INT'
      static_assert (gdb::is_detected_exact<archetype<TYPES, EXPR_TYPE>,    \
      ^              ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

This is a bit hard to decode, but basically enumerations have the
following funny property that they decay into a signed int, even if
their implicit underlying type is unsigned.  This code:

    enum A {};
    enum B {};

    int main() {
      std::cout << std::is_signed<std::underlying_type<A>::type>::value
                << std::endl;
      std::cout << std::is_signed<std::underlying_type<B>::type>::value
                << std::endl;
      auto result = true ? A() : B();
      std::cout << std::is_signed<decltype(result)>::value << std::endl;
    }

produces:

    0
    0
    1

So, the "CHECK_VALID" above checks that this property works for enum flags the
same way as it would if you were using their underlying enum types.  And
somehow, changing integer_for_size to use std::underlying_type breaks that.

Since the current code does what we want, and I don't see any way of doing it
differently, ignore -Wenum-constexpr-conversion around it.

Change-Id: Ibc82ae7bbdb812102ae3f1dd099fc859dc6f3cc2
2023-03-06 21:00:52 -05:00
Alan Modra
7ed4ad59e9 Delete PROGRESS macros
I don't see much point in cluttering the source with the PROGRESS
macros, which of course do nothing at all with the definitions in
progress.h.  progress.h is unchanged apart from the copyright comment
since commit d4d4c53c68 in 1994.

binutils/
	* ar.c: Don't include progress.h, or invoke PROGRESS macros.
	* nm.c: Likewise.
	* objcopy.c: Likewise.
	* objdump.c: Likewise.
gas/
	* as.h: Don't include progress.h.
	* as.c: Don't invoke PROGRESS macros.
	* write.c: Likewise.
include/
	* progress.h: Delete.
ld/
	* ldmain.c: Don't include progress.h, or invoke PROGRESS macros.
2023-02-16 21:00:50 +10:30
Alan Modra
8478900290 ppc32 and "LOAD segment with RWX permissions"
When using a bss-plt we'll always trigger the RWX warning, which
disturbs gcc test results.  On the other hand, there may be reason to
want the warning when gcc is configured with --enable-secureplt.
So turning off the warning entirely for powerpc might not be the best
solution.  Instead, we'll turn off the warning whenever a bss-plt is
generated, unless the user explicitly asked for the warning.

bfd/
	* elf32-ppc.c (ppc_elf_select_plt_layout): Set
	no_warn_rwx_segments on generating a bss plt, unless explicity
	enabled by the user.  Also show the bss-plt warning when
	--warn-rwx-segments is given without --bss-plt.
include/
	* bfdlink.h (struct bfd_link_info): Add user_warn_rwx_segments.
ld/
	* lexsup.c (parse_args): Set user_warn_rwx_segments.
	* testsuite/ld-elf/elf.exp: Pass --secure-plt for powerpc to
	the rwx tests.
2023-02-06 23:06:44 +10:30
Guillermo E. Martinez
7f6ebecd56 bpf: fix error conversion from long unsigned int to unsigned int [-Werror=overflow]
Regenerating BPF target using the maintainer mode emits:
.../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow]
  57 |   64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }

The use of a narrow size to handle the mask CGEN in instruction format
is causing this error.  Additionally eBPF `call' instructions
constructed by expressions using symbols (BPF_PSEUDO_CALL) emits
annotations in `src' field of the instruction, used to identify BPF
target endianness.

cpu/
	* bpf.cpu (define-call-insn): Remove `src' field from
	instruction mask.

include/
	*opcode/cge.h (CGEN_IFMT): Adjust mask bit width.

opcodes/
	* bpf-opc.c: Regenerate.
2023-02-03 11:18:50 -06:00
Indu Bhagat
53d8d3f0c1 bfd: use "stack trace" instead of "unwind" for SFrame
SFrame format is meant for generating stack traces only.

bfd/
	* elf-bfd.h: Replace the use of "unwind" with "stack trace".
	* elf-sframe.c: Likewise.
	* elf64-x86-64.c: Likewise.
	* elfxx-x86.c: Likewise.

include/
	* elf/common.h: Likewise.
2023-02-02 00:49:29 -08:00
Indu Bhagat
91def06c4d sframe: use "stack trace" instead of "unwind" for SFrame
SFrame format is meant for generating stack traces only.

include/
	* sframe.h: Fix comments in the header file.
2023-02-02 00:47:38 -08:00
Mike Frysinger
cc67f780ec sim: info: convert verbose field to a bool
The verbose argument has always been an int treated as a bool, so
convert it to an explicit bool.  Further, update the API docs to
match the reality that the verbose value is actually used by some
of the internal modules.
2023-01-18 20:47:55 -05:00
Nick Alcock
5e8b4bbcc8 ctf: fix various dreadful typos in the ctf_archive format comments
When defining a format it helps to a) get the endianness right when you
explicitly state what it is and b) define things in terms of fields that
exist rather than fields that don't.

(A bunch of changes of names during implementation were not reflected in
these comments...)

Thanks to Jose "Eye of the Eagle" Marchesi for spotting these.

include/
	* ctf.h (struct ctf_archive) [ctfa_ctfs]: The size element of
	this is in little-endian byte order, not network byte order.
	(struct ctf_archive_modent): This is positioned right after the
	end fo the struct ctf_archive, not at the offset of a
	nonexistent field.  The number of elements in the array depends
	on ctfa_ndicts, not another nonexistent field.
2023-01-12 14:40:47 +00:00
Mark Harmstone
5093b5a5e7 Fix size of external_reloc for pe-aarch64
This patch series finishes off the work by Jedidiah Thompson, and adds
support for creating aarch64 PE images.

This should be essentially complete: I've used this to create a "hello
world" Windows program in asm, and (with GCC patches) a UEFI program in
C. I think the only things missing are the .secidx relocation, which is
needed for PDBs, and the SEH pseudos used for C++ exceptions.

This first patch fixes the size of RELSZ; I'm not sure why it was 14 in
the first place. This is the size of the "Base Relocation Block" in
https://learn.microsoft.com/en-us/windows/win32/debug/pe-format, and
AFAIK should be 10 for everything.
2023-01-10 23:30:42 +00:00
Indu Bhagat
725a19bfd1 sframe: fix the defined SFRAME_FRE_TYPE_*_LIMIT constants
An earlier commit 3f107464 defined the SFRAME_FRE_TYPE_*_LIMIT
constants.  These constants are used (by gas and libsframe) to pick an
SFrame FRE type based on the function size.  Those constants, however,
were buggy, causing the generated SFrame sections to be bloated as
SFRAME_FRE_TYPE_ADDR2/SFRAME_FRE_TYPE_ADDR4 got chosen more often than
necessary.

gas/
	* sframe-opt.c (sframe_estimate_size_before_relax): Use
	typecast.
	(sframe_convert_frag): Likewise.

libsframe/
	* sframe.c (sframe_calc_fre_type): Use a more appropriate type
	for argument.  Adjust the check for SFRAME_FRE_TYPE_ADDR4_LIMIT
	to keep it warning-free but meaningful.

include/
	* sframe-api.h (sframe_calc_fre_type): Use a more appropriate
	type for the argument.
	* sframe.h (SFRAME_FRE_TYPE_ADDR1_LIMIT): Correct the constant.
	(SFRAME_FRE_TYPE_ADDR2_LIMIT): Likewise.
	(SFRAME_FRE_TYPE_ADDR4_LIMIT): Likewise.
2023-01-06 09:30:56 -08:00
Luis Machado
a8f175d9d0 Add new NT_ARM_ZA and NT_ARM_SSVE register set constants. 2023-01-03 11:15:26 +00:00
Alan Modra
d87bef3a7b Update year range in copyright notice of binutils files
The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2023-01-01 21:50:11 +10:30
Nick Clifton
a72b07181d Add markers for 2.40 branch 2022-12-31 12:05:28 +00:00
Nick Clifton
e3a5d52075 sync libiberty sources with gcc mainline 2022-12-31 12:04:51 +00:00
Christoph Müllner
767e2daed4 RISC-V: Fix T-Head Fmv vendor extension encoding
A recent change in the XTheadFmv spec fixed an encoding bug in the
document. This patch changes the code to follow this bugfix.

Spec patch can be found here:
  https://github.com/T-head-Semi/thead-extension-spec/pull/11

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-12-27 20:43:30 +01:00
Mike Frysinger
11e25f766e sim: drop unused SIM_ADDR type [PR sim/7504]
Now that sim APIs either use 64-bit addresses all the time, or more
appropriate target-specific types, drop this now-unused 32-bit-only
address type.

Bug: https://sourceware.org/PR7504
2022-12-22 20:10:14 -05:00
Mike Frysinger
63fd5b5dda sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]
We've been using SIM_ADDR which has always been 32-bit.  This means
the upper 32-bit address range in 64-bit sims is inaccessible.  Use
64-bit addresses all the time since we want the APIs to be stable
regardless of the active arch backend (which can be 32 or 64-bit).

The length is also 64-bit because it's completely feasible to have
a program that is larger than 4 GiB in size/image/runtime.  Forcing
the caller to manually chunk those accesses up into 4 GiB at a time
doesn't seem useful to anyone.

Bug: https://sourceware.org/PR7504
2022-12-22 19:29:24 -05:00
Indu Bhagat
41eed6e187 sframe.h: add support for .cfi_b_key_frame
ARM 8.3 provides five separate keys that can be used to authenticate
pointers. There are two key for executable (instruction) pointers. The
enum pointer_auth_key in gas/config/tc-aarch64.h currently holds two keys:
  enum pointer_auth_key {
    AARCH64_PAUTH_KEY_A,
    AARCH64_PAUTH_KEY_B
  };

Analogous to the above, in SFrame format V1, a bit is reserved in the SFrame
FDE to indicate which key is used for signing the frame's return addresses:
  - SFRAME_AARCH64_PAUTH_KEY_A has a value of 0
  - SFRAME_AARCH64_PAUTH_KEY_B has a value of 1

Note that the information in this bit will always be used along with the
mangled_ra_p bit, the latter indicates whether the return addresses are
mangled/contain PAC auth bits.

include/ChangeLog:

	* sframe.h (SFRAME_AARCH64_PAUTH_KEY_A): New definition.
	(SFRAME_AARCH64_PAUTH_KEY_B): Likewise.
	(SFRAME_V1_FUNC_INFO): Adjust to accommodate pauth_key.
	(SFRAME_V1_FUNC_PAUTH_KEY): New macro.
	(SFRAME_V1_FUNC_INFO_UPDATE_PAUTH_KEY): Likewise.
2022-12-22 09:57:02 -08:00
Mike Frysinger
d026e67ed4 sim: move register headers into sim/ namespace [PR sim/29869]
These headers define the register numbers for each port to implement
the sim_fetch_register & sim_store_register interfaces.  While gdb
uses these, the APIs are part of the sim, not gdb.  Move the headers
out of the gdb/ include namespace and into sim/ instead.
2022-12-20 21:06:32 -05:00
Indu Bhagat
9c4b163cb5 libsframe: provide new access API for mangled RA bit
include/ChangeLog:

	* sframe-api.h (sframe_fre_get_ra_mangled_p): New declaration.

ChangeLog:

	* libsframe/sframe.c (sframe_get_fre_ra_mangled_p): New
	definition.
	(sframe_fre_get_ra_mangled_p): New static function.
2022-12-16 22:01:57 -08:00
Indu Bhagat
4604c72941 sframe.h: add support for .cfi_negate_ra_state
Use the last remaining bit in the 'SFrame FRE info' word to store whether
the RA is signed/unsigned with PAC authorization code: this bit is named
as the "mangled RA" bit.  This bit is still unused for x86-64.

The behaviour of the mangled-RA info bit in SFrame format closely
follows the behaviour of DW_CFA_AARCH64_negate_ra_state in DWARF.  During
unwinding, whenever an SFrame FRE with non-zero "mangled RA" bit is
encountered, it means the upper bits of the return address contain Pointer
Authentication code.  The unwinder, hence, must use appropriate means to
restore LR correctly in such cases.

include/ChangeLog:

	* sframe.h (SFRAME_V1_FRE_INFO_UPDATE_MANGLED_RA_P): New macro.
	(SFRAME_V1_FRE_MANGLED_RA_P): Likewise.
2022-12-16 22:01:40 -08:00
Indu Bhagat
8c078abdc2 libsframe asan: avoid generating misaligned loads
There are two places where unaligned loads were seen on aarch64:
  - #1. access to the SFrame FRE stack offsets in the in-memory
    representation/abstraction provided by libsframe.
  - #2. access to the SFrame FRE start address in the on-disk representation
    of the frame row entry.

For #1, we can fix this by reordering the struct members of
sframe_frame_row_entry in libsframe/sframe-api.h.

For #2, we need to default to using memcpy instead, and copy out the bytes
to a location for output.

SFrame format is an unaligned on-disk format. As such, there are other blobs
of memory in the on-disk SFrame FRE that are on not on their natural
boundaries.  But that does not pose further problems yet, because the users
are provided access to the on-disk SFrame FRE data via libsframe's
sframe_frame_row_entry, the latter has its' struct members aligned on their
respective natural boundaries (and initialized using memcpy).

PR 29856 libsframe asan: load misaligned at sframe.c:516

ChangeLog:

	PR libsframe/29856
	* bfd/elf64-x86-64.c: Adjust as the struct members have been
	reordered.
	* libsframe/sframe.c (sframe_decode_fre_start_address): Use
	memcpy to perform 16-bit/32-bit reads.
	* libsframe/testsuite/libsframe.encode/encode-1.c: Adjust as the
	struct members have been reordered.

include/ChangeLog:

	PR libsframe/29856
	* sframe-api.h: Reorder fre_offsets for natural alignment.
2022-12-15 13:12:01 -08:00
Indu Bhagat
b659fb3585 libsframe: rename API sframe_fde_func_info to sframe_fde_create_func_info
The new name better reflects the purpose of the function.

ChangeLog:

	* bfd/elfxx-x86.c (_bfd_x86_elf_create_sframe_plt): Use new
	name.
	* libsframe/sframe.c (sframe_fde_create_func_info): Rename
	sframe_fde_func_info to this.
	* libsframe/testsuite/libsframe.encode/encode-1.c: Use new name.

include/ChangeLog:

	* sframe-api.h (sframe_fde_create_func_info): Rename
	sframe_fde_func_info to this.
2022-12-09 10:25:31 -08:00
Indu Bhagat
3f107464e3 sframe: gas: libsframe: define constants and remove magic numbers
Define constants in sframe.h for the various limits associated with the
range of offsets that can be encoded in the start address of an SFrame
FRE. E.g., sframe_frame_row_entry_addr1 is used when start address
offset can be encoded as 1-byte unsigned value.

Update the code in gas to use these defined constants as it checks for
these limits, and remove the usage of magic numbers.

ChangeLog:

	* gas/sframe-opt.c (sframe_estimate_size_before_relax):
	(sframe_convert_frag): Do not use magic numbers.
	* libsframe/sframe.c (sframe_calc_fre_type): Likewise.

include/ChangeLog:

	* sframe.h (SFRAME_FRE_TYPE_ADDR1_LIMIT): New constant.
	(SFRAME_FRE_TYPE_ADDR2_LIMIT): Likewise.
	(SFRAME_FRE_TYPE_ADDR4_LIMIT): Likewise.
2022-12-09 10:23:07 -08:00
Indu Bhagat
70cfae61f4 sframe.h: make some macros more precise
include/ChangeLog:

	* sframe.h (SFRAME_V1_FUNC_INFO): Use specific bits only.
	(SFRAME_V1_FRE_INFO): Likewise.
2022-12-09 10:22:31 -08:00
Alan Modra
c3620d6d56 Compression tidy and fixes
Tidies:
- Move stuff from bfd-in.h and libbfd.c to compress.c
- Delete COMPRESS_DEBUG from enum compressed_debug_section_type
- Move compress_debug field out of link_info to ld_config.
Fixes:
- Correct test in bfd_convert_section_setup to use obfd flags,
  not ibfd.
- Apply bfd_applicable_file_flags to compression bfd flags added
  by gas and ld to the output bfd.

bfd/
	* bfd-in.h (enum compressed_debug_section_type),
	(struct compressed_type_tuple),
	(bfd_get_compression_algorithm),
	(bfd_get_compression_algorithm_name),
	* libbfd.c (compressed_debug_section_names),
	(bfd_get_compression_algorithm),
	(bfd_get_compression_algorithm_name): Move..
	* compress.c: ..to here, deleting COMPRESS_DEBUG from
	enum compressed_debug_section_type.
	(bfd_convert_section_setup): Test obfd flags not ibfd for
	compression flags.
	* elf.c (elf_fake_sections): Replace link_info->compress_debug
	test with abfd->flags test.
	* bfd-in2.h: Regenerate.
binutils/
	* objcopy.c (copy_file): Tidy setting of bfd compress flags.
	Expand comment.
gas/
	* write.c (compress_debug): Test bfd compress flags rather than
	flag_compress_debug.
	(write_object_file): Apply bfd_applicable_file_flags to compress
	debug flags added to output bfd.
include/
	* bfdlink.h (struct bfd_link_info): Delete compress_debug.
ld/
	* ld.h (ld_config_type): Add compress_debug.
	* emultempl/elf.em: Replace references to link_info.compress_debug
	with config.compress_debug.
	* lexsup.c (elf_static_list_options): Likewise.
	* ldmain.c (main): Likewise.  Apply bfd_applicable_file_flags
	to compress debug flags added to output bfd.
2022-12-07 13:15:29 +10:30
Max Filippov
d0a2cfbd31 xtensa: allow dynamic configuration
Import include/xtensa-dynconfig.h that defines XCHAL_* macros as fields
of a structure returned from the xtensa_get_config_v<x> function call.
Define that structure and fill it with default parameter values
specified in the include/xtensa-config.h.
Define reusable function xtensa_load_config that tries to load
configuration and return an address of an exported object from it.
Define functions xtensa_get_config_v{1,2} that use xtensa_load_config
to get structures xtensa_config_v{1,2}, either dynamically configured
or the default.

bfd/
	* Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Append
	xtensa-dynconfig.c.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* configure.ac (xtensa_elf32_be_vec, xtensa_elf32_le_vec): Add
	xtensa-dynconfig.lo to the tb.
	* elf32-xtensa.c (xtensa-config.h): Replace #include with
	xtensa-dynconfig.h.
	(XSHAL_ABI, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): Remove
	definitions.
	* xtensa-dynconfig.c: New file.
	* xtensa-isa.c (xtensa-dynconfig.h): New #include.
	(xtensa_get_modules): New function.
	(xtensa_isa_init): Call xtensa_get_modules instead of taking
	address of global xtensa_modules.

gas/
	* config/tc-xtensa.c (xtensa-config.h): Replace #include with
	xtensa-dynconfig.h.
	(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0, XTENSA_MARCH_EARLIEST):
	Remove definitions.
	* config/tc-xtensa.h (xtensa-config.h): Replace #include with
	xtensa-dynconfig.h.
	* config/xtensa-relax.c (xtensa-config.h): Replace #include with
	xtensa-dynconfig.h.
	(XCHAL_HAVE_WIDE_BRANCHES): Remove definition.

include/
	* xtensa-dynconfig.h: New file.

ld/
	* emultempl/xtensaelf.em (xtensa-config.h): Replace #include
	with xtensa-dynconfig.h.
	(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): Remove definitions.
2022-11-28 18:16:12 -08:00
Christoph Müllner
ac8df5a192 riscv: Add AIA extension support (Smaia, Ssaia)
This commit adds the AIA extensions (Smaia and Ssaia) CSRs.

bfd/ChangeLog:

	* elfxx-riscv.c: Add 'smaia' and 'ssaia' to the list
	of known standard extensions.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class):
	(riscv_csr_address): Add CSR classes for Smaia/Ssaia.
	* testsuite/gas/riscv/csr-dw-regnums.d: Add new CSRs.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/csr.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (CSR_MISELECT): New CSR macro.
	(CSR_MIREG): Likewise.
	(CSR_MTOPEI): Likewise.
	(CSR_MTOPI): Likewise.
	(CSR_MVIEN): Likewise.
	(CSR_MVIP): Likewise.
	(CSR_MIDELEGH): Likewise.
	(CSR_MIEH): Likewise.
	(CSR_MVIENH): Likewise.
	(CSR_MVIPH): Likewise.
	(CSR_MIPH): Likewise.
	(CSR_SISELECT): Likewise.
	(CSR_SIREG): Likewise.
	(CSR_STOPEI): Likewise.
	(CSR_STOPI): Likewise.
	(CSR_SIEH): Likewise.
	(CSR_SIPH): Likewise.
	(CSR_HVIEN): Likewise.
	(CSR_HVICTL): Likewise.
	(CSR_HVIPRIO1): Likewise.
	(CSR_HVIPRIO2): Likewise.
	(CSR_VSISELECT): Likewise.
	(CSR_VSIREG): Likewise.
	(CSR_VSTOPEI): Likewise.
	(CSR_VSTOPI): Likewise.
	(CSR_HIDELEGH): Likewise.
	(CSR_HVIENH): Likewise.
	(CSR_HVIPH): Likewise.
	(CSR_HVIPRIO1H): Likewise.
	(CSR_HVIPRIO2H): Likewise.
	(CSR_VSIEH): Likewise.
	(CSR_VSIPH): Likewise.
	(DECLARE_CSR): Add CSRs for Smaia and Ssaia.

Changes for v3:
- Imply ssaia for smaia
- Imply zicsr for ssaia (and transitively smaia)
- Move hypervisor CSRs to Ssaia+H
- Rebase on upstream/master

Changes for v2:
- Add hypervisor and VS CSRs
- Fix whitespace issue

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-11-25 10:00:06 +08:00
Tsukasa OI
15253318be RISC-V: Add 'Ssstateen' extension and its CSRs
This commit adds 'Ssstateen' extension, which is a supervisor-visible view
of the 'Smstateen' extension.  It means, this extension implements sstateen*
and hstateen* CSRs of the 'Smstateen' extension.

Note that 'Smstateen' extension itself is unchanged but due to
implementation simplicity, it is implemented so that 'Smstateen' implies
'Ssstateen' (just like 'M' implies 'Zmmul').

This is based on the latest version of RISC-V Profiles
(version 0.9-draft, Frozen):
<226b7f6430>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Update implication rules.
	(riscv_supported_std_s_ext) Add 'Ssstateen' extension.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Rename
	CSR_CLASS_SMSTATEEN_AND_H{,_32} to CSR_CLASS_SSSTATEEN_...
	Add CSR_CLASS_SSSTATEEN.
	(riscv_csr_address): Support new/renamed CSR classes.
	* testsuite/gas/riscv/csr.s: Add 'Ssstateen' extension to comment.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Reflect changes to
	error messages.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
	* testsuite/gas/riscv/ssstateen-csr.s: Test for 'Ssstateen' CSRs.
	* testsuite/gas/riscv/ssstateen-csr.d: Likewise.
	* testsuite/gas/riscv/smstateen-csr-s.d: Test to make sure that
	supervisor/hypervisor part of 'Smstateen' CSRs are accessible from
	'RV32IH_Smstateen', not just from 'RV32IH_Ssstateen' that is tested
	in ssstateen-csr.d.

include/ChangeLog:

	* opcode/riscv-opc.h: Update DECLARE_CSR declarations with
	new CSR classes.
2022-11-19 02:57:05 +00:00
Christoph Müllner
01804a098d RISC-V: Add T-Head Int vendor extension
This patch adds the XTheadInt extension, which provides interrupt
stack management instructions.

The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
  https://github.com/riscv-non-isa/riscv-toolchain-conventions

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-11-17 16:43:55 +08:00
Christoph Müllner
4a3bc79bf4 RISC-V: Add T-Head Fmv vendor extension
This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.

The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
  https://github.com/riscv-non-isa/riscv-toolchain-conventions

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-11-17 16:43:49 +08:00
Indu Bhagat
42b6953bba readelf/objdump: support for SFrame section
This patch adds support for SFrame in readelf and objdump. The arguments
of --sframe are optional for both readelf and objdump.

include/ChangeLog:

	* sframe-api.h (dump_sframe): New function declaration.

ChangeLog:

	* binutils/Makefile.am: Add dependency on libsframe for
	readelf and objdump.
	* binutils/Makefile.in: Regenerate.
	* binutils/doc/binutils.texi: Document --sframe=[section].
	* binutils/doc/sframe.options.texi: New file.
	* binutils/objdump.c: Add support for SFrame format.
	* binutils/readelf.c: Likewise.
	* include/sframe-api.h: Add new API for dumping .sframe
	section.
	* libsframe/Makefile.am: Add sframe-dump.c.
	* libsframe/Makefile.in: Regenerate.
	* libsframe/sframe-dump.c: New file.
2022-11-15 15:50:05 -08:00
Indu Bhagat
cf0e0a0ba9 bfd: linker: merge .sframe sections
The linker merges all the input .sframe sections.  When merging, the
linker verifies that all the input .sframe sections have the same
abi/arch.

The linker uses libsframe library to perform key actions on the
.sframe sections - decode, read, and create output data.  This
implies buildsystem changes to make and install libsframe before
libbfd.

The linker places the output .sframe section in a new segment of its
own: PT_GNU_SFRAME.  A new segment is not added, however, if the
generated .sframe section is empty.

When a section is discarded from the final link, the corresponding
entries in the .sframe section for those functions are also deleted.

The linker sorts the SFrame FDEs on start address by default and sets
the SFRAME_F_FDE_SORTED flag in the .sframe section.

This patch also adds support for generation of SFrame unwind
information for the .plt* sections on x86_64.  SFrame unwind info is
generated for IBT enabled PLT, lazy/non-lazy PLT.

The existing linker option --no-ld-generated-unwind-info has been
adapted to include the control of whether .sframe unwind information
will be generated for the linker generated sections like PLT.

Changes to the linker script have been made as necessary.

ChangeLog:

	* Makefile.def: Add install dependency on libsframe for libbfd.
	* Makefile.in: Regenerated.
	* bfd/Makefile.am: Add elf-sframe.c
	* bfd/Makefile.in: Regenerated.
	* bfd/bfd-in2.h (SEC_INFO_TYPE_SFRAME): Regenerated.
	* bfd/configure: Regenerate.
	* bfd/configure.ac: Add elf-sframe.lo.
	* bfd/elf-bfd.h (struct sframe_func_bfdinfo): New struct.
	(struct sframe_dec_info): Likewise.
	(struct sframe_enc_info): Likewise.
	(struct elf_link_hash_table): New member for encoded .sframe
	object.
	(struct output_elf_obj_tdata): New member.
	(elf_sframe): New access macro.
	(_bfd_elf_set_section_sframe): New declaration.
	* bfd/elf.c (get_segment_type): Handle new segment
	PT_GNU_SFRAME.
	(bfd_section_from_phdr): Likewise.
	(get_program_header_size): Likewise.
	(_bfd_elf_map_sections_to_segments): Likewise.
	* bfd/elf64-x86-64.c (elf_x86_64_link_setup_gnu_properties): Add
	contents to the .sframe sections or .plt* entries.
	* bfd/elflink.c (elf_section_ignore_discarded_relocs): Handle
	SEC_INFO_TYPE_SFRAME.
	(_bfd_elf_default_action_discarded): Handle .sframe section.
	(elf_link_input_bfd): Merge .sframe section.
	(bfd_elf_final_link): Write the output .sframe section.
	(bfd_elf_discard_info): Handle discarding .sframe section.
	* bfd/elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Create
	.sframe section for .plt and .plt.sec.
	(_bfd_x86_elf_finish_dynamic_sections): Handle .sframe from
	.plt* sections.
	* bfd/elfxx-x86.h (PLT_SFRAME_FDE_START_OFFSET): New
	definition.
	(SFRAME_PLT0_MAX_NUM_FRES): Likewise.
	(SFRAME_PLTN_MAX_NUM_FRES): Likewise.
	(struct elf_x86_sframe_plt): New structure.
	(struct elf_x86_link_hash_table): New member.
	(struct elf_x86_init_table): New members for .sframe
	creation.
	* bfd/section.c: Add new definition SEC_INFO_TYPE_SFRAME.
	* binutils/readelf.c (get_segment_type): Handle new segment
	PT_GNU_SFRAME.
	* ld/ld.texi: Update documentation for
	--no-ld-generated-unwind-info.
	* ld/scripttempl/elf.sc: Support .sframe sections.
	* ld/Makefile.am (TESTSFRAMELIB): Use it.
	(check-DEJAGNU): Likewise.
	* ld/Makefile.in: Regenerated.
	* ld/configure.ac (TESTSFRAMELIB): Set to the .so or .a like TESTBFDLIB.
	* ld/configure: Regenerated.
	* bfd/elf-sframe.c: New file.

include/ChangeLog:

	* elf/common.h (PT_GNU_SFRAME): New definition.
	* elf/internal.h (struct elf_segment_map): Handle new segment
	type PT_GNU_SFRAME.

ld/testsuite/ChangeLog:

	* ld/testsuite/ld-bootstrap/bootstrap.exp: Add SFRAMELIB.
	* ld/testsuite/ld-aarch64/aarch64-elf.exp: Add new test
	  sframe-simple-1.
	* ld/testsuite/ld-aarch64/sframe-bar.s: New file.
	* ld/testsuite/ld-aarch64/sframe-foo.s: Likewise.
	* ld/testsuite/ld-aarch64/sframe-simple-1.d: Likewise.
	* ld/testsuite/ld-sframe/sframe-empty.d: New test.
	* ld/testsuite/ld-sframe/sframe-empty.s: New file.
	* ld/testsuite/ld-sframe/sframe.exp: New testsuite.
	* ld/testsuite/ld-x86-64/sframe-bar.s: New file.
	* ld/testsuite/ld-x86-64/sframe-foo.s: Likewise.
	* ld/testsuite/ld-x86-64/sframe-simple-1.d: Likewise.
	* ld/testsuite/ld-x86-64/sframe-plt-1.d: Likewise.
	* ld/testsuite/ld-x86-64/sframe-simple-1.d: Likewise.
	* ld/testsuite/ld-x86-64/x86-64.exp: Add new tests -
	  sframe-simple-1, sframe-plt-1.
	* ld/testsuite/lib/ld-lib.exp: Add new proc to check if
	  assembler supports SFrame section.
	* ld/testsuite/ld-sframe/discard.d: New file.
	* ld/testsuite/ld-sframe/discard.ld: Likewise.
	* ld/testsuite/ld-sframe/discard.s: Likewise.
2022-11-15 15:49:47 -08:00
Weimin Pan
19e559f1c9 libsframe: add the SFrame library
libsframe is a library that allows you to:
- decode a .sframe section
- probe and inspect a .sframe section
- encode (and eventually write) a .sframe section.

This library is currently being used by the linker, readelf, objdump.
This library will also be used by the SFrame unwinder which is still
to be upstream'd.

The file include/sframe-api.h defines the user-facing APIs for decoding,
encoding and probing .sframe sections. A set of error codes together
with their error message strings are also defined.

Endian flipping is performed automatically at read and write time, if
cross-endianness is detected.

ChangeLog:

	* Makefile.def: Add libsframe as new module with its
	dependencies.
	* Makefile.in: Regenerated.
	* binutils/Makefile.am: Add libsframe.
	* binutils/Makefile.in: Regenerated.
	* configure: Regenerated
	* configure.ac: Add libsframe to host_libs.
	* libsframe/Makefile.am: New file.
	* libsframe/Makefile.in: New file.
	* libsframe/aclocal.m4: New file.
	* libsframe/config.h.in: New file.
	* libsframe/configure: New file.
	* libsframe/configure.ac: New file.
	* libsframe/sframe-error.c: New file.
	* libsframe/sframe-impl.h: New file.
	* libsframe/sframe.c: New file.

include/ChangeLog:

	* sframe-api.h: New file.

testsuite/ChangeLog:

	* libsframe/testsuite/Makefile.am: New file.
	* libsframe/testsuite/Makefile.in: Regenerated.
	* libsframe/testsuite/libsframe.decode/Makefile.am: New
	  file.
	* libsframe/testsuite/libsframe.decode/Makefile.in:
	  Regenerated.
	* libsframe/testsuite/libsframe.decode/decode.exp: New file.
	* libsframe/testsuite/libsframe.encode/Makefile.am:
	  Likewise.
	* libsframe/testsuite/libsframe.encode/Makefile.in:
	  Regenerated.
	* libsframe/testsuite/libsframe.encode/encode.exp: New file.
	* libsframe/testsuite/libsframe.encode/encode-1.c: Likewise.
	* libsframe/testsuite/libsframe.decode/be-flipping.c: Likewise.
	* libsframe/testsuite/libsframe.decode/frecnt-1.c: Likewise.
	* libsframe/testsuite/libsframe.decode/frecnt-2.c: Likewise.
	* libsframe/testsuite/libsframe.decode/DATA-BE: New file.
	* libsframe/testsuite/libsframe.decode/DATA1: Likewise.
	* libsframe/testsuite/libsframe.decode/DATA2: Likewise.
2022-11-15 15:24:29 -08:00
Indu Bhagat
972d23ddbd sframe.h: Add SFrame format definition
The header sframe.h defines the SFrame format.

The SFrame format is the Simple Frame format.  It can be used to
represent the minimal necessary unwind information required for
backtracing.  The current version supports AMD64 and AARCH64.

More details of the SFrame format are included in the documentation
of the header file in this patch.

include/ChangeLog:
	* sframe.h: New file.
2022-11-15 15:23:44 -08:00
Andre Vieira
1f7b42d52a aarch64: Add support for Common Short Sequence Compression extension
This patch adds support for the CSSC extension and its corresponding
instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN.

gas/ChangeLog:

        * config/tc-aarch64.c (parse_operands): Handle new operand types.
        * doc/c-aarch64.texi: Document new extension.
        * testsuite/gas/aarch64/cssc.d: New test.
        * testsuite/gas/aarch64/cssc.s: New test.

include/ChangeLog:

        * opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro.
        (enum aarch64_opnd): New operand types.
        (enum aarch64_insn_class): New instruction class.

opcodes/ChangeLog:

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (operand_general_constraint_met_p): Update for new
	operand types.
	(aarch64_print_operand): Likewise.
	* aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field.
	* aarch64-tbl.h (aarch64_feature_cssc): Define new feature set.
	(CSSC): Define new feature set Macro.
	(CSSC_INSN): Define new instruction type.
	(aarch64_opcode_table): Add new instructions.
2022-11-14 16:47:22 +00:00
Mike Frysinger
195064c8da sim: drop unused CORE_ADDR_TYPE
This hasn't been used by gdb in decades, and doesn't make sense with
a standalone sim program/library where the ABI is fixed.  So punt it
to simplify the code.
2022-11-08 14:09:06 +07:00
Mike Frysinger
ee1cffd388 sim: common: change sim_{fetch,store}_register helpers to use void* buffers
When reading/writing arbitrary data to the system's memory, the unsigned
char pointer type doesn't make that much sense.  Switch it to void so we
align a bit with standard C library read/write functions, and to avoid
having to sprinkle casts everywhere.
2022-11-02 20:31:10 +05:45
Mike Frysinger
5bab16fdf1 sim: reg: constify store helper
These functions only read from memory, so mark the pointer as const.
2022-10-31 21:24:39 +05:45
Mike Frysinger
5b94c38081 sim: common: change sim_read & sim_write to use void* buffers
When reading/writing arbitrary data to the system's memory, the unsigned
char pointer type doesn't make that much sense.  Switch it to void so we
align a bit with standard C library read/write functions, and to avoid
having to sprinkle casts everywhere.
2022-10-31 21:24:39 +05:45
Tsukasa OI
56d4450bdf include: Define macro to ignore -Wdeprecated-declarations on GCC
"-Wdeprecated-declarations" warning option can be helpful to track
deprecated function delarations but sometimes we need to disable this
warning for a good reason.

DIAGNOSTIC_IGNORE_DEPRECATED_DECLARATIONS is an existing macro but only
defined on Clang.  Since "-Wdeprecated-declarations" is also available on
GCC (>= 3.4.0), this commit adds equivalent definition as Clang.

__GNUC__ and __GNUC_MINOR__ are not checked because this header file seems
to assume GCC >= 4.6 (with "GCC diagnostic push/pop").

include/ChangeLog:

	* diagnostics.h (DIAGNOSTIC_IGNORE_DEPRECATED_DECLARATIONS):
	Define also on GCC.
2022-10-28 05:32:11 +00:00
Peter Bergner
79e24d0a6c PowerPC: Add support for RFC02653 - Dense Math Facility
gas/
	* config/tc-ppc.c (pre_defined_registers): Add dense math registers.
	(md_assemble): Check dmr specified in correct operand.
	* testsuite/gas/ppc/outerprod.s <dmsetaccz, dmxvbf16ger2,
	dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp,
	dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp,
	dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp,
	dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp,
	dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8,
	dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxmfacc,
	dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np,
	pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn,
	pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger,
	pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp,
	pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn,
	pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s,
	pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4,
	pmdmxvi8ger4pp, pmdmxvi8ger4spp>: Add new tests.
	* testsuite/gas/ppc/outerprod.d: Likewise.
	* testsuite/gas/ppc/rfc02653.s: New test.
	* testsuite/gas/ppc/rfc02653.d: Likewise.
	* testsuite/gas/ppc/ppc.exp: Run it.

include/
	* opcode/ppc.h (PPC_OPERAND_DMR): Define.  Renumber following
	PPC_OPERAND defines.

opcodes/
	* ppc-dis.c (print_insn_powerpc): Prepend 'dm' when printing DMR regs.
	* ppc-opc.c (insert_p2, (extract_p2, (insert_xa5, (extract_xa5,
	insert_xb5, (extract_xb5): New functions.
	(insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): Disallow
	operand overlap only on Power10.
	(DMR, DMRAB, P1, P2, XA5p, XB5p, XDMR_MASK, XDMRDMR_MASK, XX2ACC_MASK,
	XX2DMR_MASK, XX3DMR_MASK): New defines.
	(powerpc_opcodes): Add dmmr, dmsetaccz, dmsetdmrz, dmxor, dmxvbf16ger2,
	dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp,
	dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp,
	dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp,
	dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp,
	dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8,
	dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxextfdmr256,
	dmxxextfdmr512, dmxxinstdmr256, dmxxinstdmr512, dmxxmfacc, dmxxmtacc,
	pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn,
	pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np,
	pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn,
	pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger,
	pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp,
	pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp,
	pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp,
	pmdmxvi8ger4spp.
2022-10-27 19:23:00 -05:00
Jedidiah Thompson
c60b380679 aarch64-pe support for LD, GAS and BFD
Allows aarch64-pe to be targeted natively, not having to use objcopy to convert it from ELF to PE.
Based on initial work by Jedidiah Thompson

Co-authored-by: Jedidiah Thompson <wej22007@outlook.com>
Co-authored-by: Zac Walker <zac.walker@linaro.org>
2022-10-19 10:57:12 +02:00
Alan Modra
61a457e5da e200 LSP support
It has bothered me for a long time that we have disabled LSP (and SPE)
tests.  Also the LSP test comment indicating there is something wrong
with get_powerpc_dialect.  I don't think there is.  Decoding of a VLE
instruction depends on whether the processor is in VLE mode (some
processors support both VLE and standard PPC) which we flag per
section with SHF_PPC_VLE for decoding when disassembling.

Background: Some versions of powerpc e200 have "Lightweight Signal
Processing" support, examples being e200z215 and e200z425.  As far as
I can tell, LSP and SPE are mutually exclusive.  This seems to be
borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw"
have the same encoding.  So none of the processor descriptions in
ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we
want disassembly to work.  I also could not find anything to suggest
that the LSP insns are enabled only in VLE mode, which means the LSP
insns should not be in vle_opcodes.

Fix all this by moving the LSP insns to their own table, and add a new
e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from
-mvle.  (Yes, I know, as I said above some of the e200z4 processors
have LSP.  Others have SPE.  It's hard to choose good options.  Think
of z2 as meaning earlier, z4 as later.)  Also add -mlsp to allow
adding the LSP insn set.

include/
	* opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare.
	(LSP_OP_TO_SEG): Define.
binutils/
	* doc/binutils.texi: Update ppc docs.
gas/
	* config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash.
	* doc/c-ppc.texi: Document e200 and lsp.
	* testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2.
	* testsuite/gas/ppc/lsp.d: Likewise, disassembly too.
	* testsuite/gas/ppc/ppc.exp: Don't xfail lsp test.
opcodes/
	* ppc-dis.c (ppc_opts): Add e200z2 and lsp.  Don't set
	PPC_OPCODE_LSP for e200z4 or vle.
	(ppc_parse_cpu): Mutually exclude LSP and SPE.
	(LSP_OPCD_SEGS): Define.
	(lsp_opcd_indices): New array.
	(disassemble_init_powerpc): Init lsp_opcd_indices.
	(lookup_lsp): New function.
	(print_insn_powerpc): Call it.
	* ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout.
	(vle_opcodes): Move LSP opcodes to..
	(lsp_opcodes): ..here, and sort.
	(lsp_num_opcodes): New.
2022-10-14 22:07:18 +10:30
Tsukasa OI
3d9d92c22f RISC-V: Move certain arrays to riscv-opc.c
This is a part of small tidying (declare tables in riscv-opc.c).

include/ChangeLog:

	* opcode/riscv.h (riscv_rm, riscv_pred_succ): Move declarations to
	opcodes/riscv-opc.c.  New non-static definitions.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_rm, riscv_pred_succ): Move from
	include/opcode/riscv.h.  Add description.
2022-10-14 05:21:38 +00:00
Tsukasa OI
73e30e726c RISC-V: Fix buffer overflow on print_insn_riscv
Because riscv_insn_length started to support instructions up to 176-bit,
we need to increase packet buffer size to 176-bit in size.

include/ChangeLog:

	* opcode/riscv.h (RISCV_MAX_INSN_LEN): Max instruction length for
	use in buffer size.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_riscv): Increase buffer size for max
	176-bit length instructions.
2022-10-04 13:21:41 +00:00
Nelson Chu
136ea87420 RISC-V: Renamed INSN_CLASS for floating point in integer extensions.
Just added suffix _INX for those INSN_CLASS should be enough to represent
their fpr can be replaced by gpr.
2022-10-04 21:15:51 +08:00
Jan Beulich
bb996692bd RISC-V/gas: allow generating up to 176-bit instructions with .insn
For the time being simply utilize O_big to avoid widening other fields,
bypassing append_insn() etc.
2022-10-04 09:46:11 +02:00
Jan-Benedict Glaw
aef1974a66 Fix self-move warning check for GCC 13+
GCC 13 got the self-move warning (0abb78dda084a14b3d955757c6431fff71c263f3),
but that warning is only checked for clang, resulting in:

/usr/lib/gcc-snapshot/bin/g++ -x c++    -I. -I. -I./config -DLOCALEDIR="\"/tmp/gdb-m68k-linux/share/locale\"" -DHAVE_CONFIG_H -I./../include/opcode -I./../readline/readline/.. -I./../zlib  -I../bfd -I./../bfd -I./../include -I../libdecnumber -I./../libdecnumber  -I./../gnulib/import -I../gnulib/import -I./.. -I.. -I./../libbacktrace/ -I../libbacktrace/  -DTUI=1    -I./.. -pthread  -Wall -Wpointer-arith -Wno-unused -Wunused-value -Wunused-variable -Wunused-function -Wno-switch -Wno-char-subscripts -Wempty-body -Wunused-but-set-parameter -Wunused-but-set-variable -Wno-sign-compare -Wno-error=maybe-uninitialized -Wno-mismatched-tags -Wsuggest-override -Wimplicit-fallthrough=3 -Wduplicated-cond -Wshadow=local -Wdeprecated-copy -Wdeprecated-copy-dtor -Wredundant-move -Wmissing-declarations -Wstrict-null-sentinel -Wformat -Wformat-nonliteral -Werror -g -O2   -c -o unittests/environ-selftests.o -MT unittests/environ-selftests.o -MMD -MP -MF unittests/.deps/environ-selftests.Tpo unittests/environ-selftests.c
unittests/environ-selftests.c: In function 'void selftests::gdb_environ_tests::test_self_move()':
unittests/environ-selftests.c:228:7: error: moving 'env' of type 'gdb_environ' to itself [-Werror=self-move]
  228 |   env = std::move (env);
      |   ~~~~^~~~~~~~~~~~~~~~~
unittests/environ-selftests.c:228:7: note: remove 'std::move' call
cc1plus: all warnings being treated as errors
make[1]: *** [Makefile:1896: unittests/environ-selftests.o] Error 1
make[1]: Leaving directory '/var/lib/laminar/run/gdb-m68k-linux/3/binutils-gdb/gdb'
make: *** [Makefile:13193: all-gdb] Error 2
2022-10-03 16:56:24 +02:00
liuzhensong
c4a7e6b562 LoongArch: Update ELF e_flags handling according to specification.
Update handling of e_flags according to the documentation
  update [1] (discussions [2][3]).

  Object file bitness is now represented in the EI_CLASS byte.
  The e_flags field is now interpreted as follows:

  e_flags[2:0]: Base ABI modifier

  - 0x1: soft-float
  - 0x2: single-precision hard-float
  - 0x3: double-precision hard-float

  e_flags[7:6]: ELF object ABI version

  - 0x0: v0
  - 0x1: v1

  [1]: https://github.com/loongson/LoongArch-Documentation/blob/main/docs/LoongArch-ELF-ABI-EN.adoc#e_flags-identifies-abi-type-and-version
  [2]: https://github.com/loongson/LoongArch-Documentation/pull/61
  [3]: https://github.com/loongson/LoongArch-Documentation/pull/47
2022-09-30 14:00:47 +08:00
John Baldwin
4f60f82104 Support AT_USRSTACKBASE and AT_USRSTACKLIM.
FreeBSD's kernel has recently added two new ELF auxiliary vector
entries to describe the location of the user stack for the initial
thread in a process.

This change displays the proper name and description of these entries
in 'info auxv'.
2022-09-23 15:36:10 -07:00
Christoph Müllner
eb668e5003 RISC-V: Add Zawrs ISA extension support
This patch adds support for the Zawrs ISA extension
("wrs.nto" and "wrs.sto" instructions).

The specification can be found here:
https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-23 19:51:29 +02:00
Christoph Müllner
6e17ae6255 RISC-V: Add T-Head MemPair vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadMemPair extension, a collection of T-Head specific
two-GP-register memory operations.
The 'th' prefix and the "XTheadMemPair" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22 18:06:09 +02:00
Christoph Müllner
27cfd142d0 RISC-V: Add T-Head MemIdx vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadMemIdx extension, a collection of T-Head specific
GPR memory access instructions.
The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).

In total XTheadCmo introduces the following 44 instructions
(BU,HU,WU only for loads (zero-extend instead of sign-extend)):

* {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2
* {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
* {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22 18:06:09 +02:00
Christoph Müllner
f511f80fa3 RISC-V: Add T-Head FMemIdx vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadFMemIdx extension, a collection of
T-Head-specific floating-point memory access instructions.
The 'th' prefix and the "XTheadFMemIdx" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22 18:06:09 +02:00
Christoph Müllner
4041e11db3 RISC-V: Add T-Head MAC vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadMac extension, a collection of
T-Head-specific multiply-accumulate instructions.
The 'th' prefix and the "XTheadMac" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22 18:06:09 +02:00
Christoph Müllner
7344223096 RISC-V: Add T-Head CondMov vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadCondMov extension, a collection of
T-Head-specific conditional move instructions.
The 'th' prefix and the "XTheadCondMov" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22 18:06:09 +02:00
Christoph Müllner
8254c3d2c9 RISC-V: Add T-Head Bitmanip vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XThead{Ba,Bb,Bs} extensions, a collection of
T-Head-specific bitmanipulation instructions.
The 'th' prefix and the "XThead{Ba,Bb,Bs}" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22 18:06:09 +02:00
Christoph Müllner
8b7419c429 RISC-V: Add support for arbitrary immediate encoding formats
This patch introduces support for arbitrary signed or unsigned immediate
encoding formats. The formats have the form "XsN@S" and "XuN@S" with N
being the number of bits and S the LSB position.

For example an immediate field of 5 bytes that encodes a signed value
and is stored in the bits 24-20 of the instruction word can use the
format specifier "Xs5@20".

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22 18:06:09 +02:00
Christoph Müllner
547c18d9bb RISC-V: Add T-Head SYNC vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadSync extension, a collection of
T-Head-specific multi-processor synchronization instructions.
The 'th' prefix and the "XTheadSync" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22 18:06:09 +02:00
Christoph Müllner
a9ba8bc2d3 RISC-V: Add T-Head CMO vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadCmo extension, a collection of T-Head specific
cache management operations.
The 'th' prefix and the "XTheadCmo" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).

In total XTheadCmo introduces the following 21 instructions:

* DCACHE.{C,CI,I}ALL
* DCACHE.{C,CI,I}{PA,VA,SW} rs1
* DCACHE.C{PAL1,VAL1} rs1
* ICACHE.I{ALL,ALLS}
* ICACHE.I{PA,VA} rs1
* L2CACHE.{C,CI,I}ALL

Contrary to Zicbom, the XTheadCmo instructions don't have a constant
displacement, therefore we have a different syntax for the arguments.
To clarify this is intended behaviour, there is a set of negative test
for Zicbom-style arguments in x-thead-cmo-fail.s.

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

v2:
- Add missing DECLARE_INSN() list
- Fix ordering

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22 18:06:09 +02:00
Tsukasa OI
d9fa9b7c33 include: Add macro to ignore -Wunused-but-set-variable
"-Wunused-but-set-variable" warning option can be helpful to track variables
that are written but not read thereafter.  But it can be harmful if some of
the code is auto-generated and we have no ways to deal with it.

The particular example is Bison-generated code.

The new DIAGNOSTIC_IGNORE_UNUSED_BUT_SET_VARIABLE macro can be helpful on
such cases. A typical use of this macro is to place this macro before the
end of user prologues on Bison (.y) files.

include/ChangeLog:

    * diagnostics.h (DIAGNOSTIC_IGNORE_UNUSED_BUT_SET_VARIABLE): New.
2022-09-22 10:53:24 +00:00
Tsukasa OI
c59ea02cc3 include: Add macro to ignore -Wuser-defined-warnings
User-defined warnings (on Clang, "-Wuser-defined-warnings") can be harmful
if we have specified "-Werror" and we have no control to disable the warning
ourself.  The particular example is Gnulib.

Gnulib generates a warning if the system version of certain functions
are used (to redirect the developer to use Gnulib version).  However,
it can be harmful if we cannot easily replace them (e.g. the target is in
the standard C++ library).

The new DIAGNOSTIC_IGNORE_USER_DEFINED_WARNINGS macro can be helpful on such
cases.  A typical use of this macro is to place this macro before including
certain system headers.

include/ChangeLog:

	* diagnostics.h (DIAGNOSTIC_IGNORE_USER_DEFINED_WARNINGS): New.
2022-09-22 10:53:24 +00:00
Simon Marchi
198f946ffe gdbsupport: move include/gdb/fileio.h contents to fileio.h
I don't see why include/gdb/fileio.h is placed there.  It's not
installed by "make install", and it's not included by anything outside
of gdb/gdbserver/gdbsupport.

Move its content back to gdbsupport/fileio.h.  I have omitted the bits
inside an `#if 0`, since it's obviously not used, as well as the
"limits" constants, which are also unused.

Change-Id: I6fbc2ea10fbe4cfcf15f9f76006b31b99c20e5a9
2022-09-21 14:11:03 -04:00
Shihua
96462b0129 RISC-V: Implement Ztso extension
This patch support ZTSO extension. It will turn on the tso flag for elf_flags
once we have enabled Ztso extension.  This is intended to implement v0.1 of
the proposed specification which can be found in Chapter 25 of,
https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf.

bfd\ChangeLog:

        * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag.
        * elfxx-riscv.c: Add Ztso's arch.

binutils\ChangeLog:

        * readelf.c (get_machine_flags): Set TSO flag.

gas\ChangeLog:

        * config/tc-riscv.c (riscv_set_tso): Ditto.
        (riscv_set_arch): Ditto.
        * testsuite/gas/riscv/ztso.d: New test.

include\ChangeLog:

        * elf/riscv.h (EF_RISCV_TSO): Ditto.
2022-09-21 11:43:35 +08:00
Peter Bergner
29a6701e53 ppc: Document the -mfuture and -Mfuture options and make them usable
The -mfuture and -Mfuture options which are used for adding potential
new ISA instructions were not documented.  They also lacked a bitmask
so new instructions could not be enabled by those options.  Fixed.

binutils/
	* doc/binutils.texi: Document -Mfuture.

gas/
	* config/tc-ppc.c: Document -mfuture
	* doc/c-ppc.texi: Likewise.

include/
	* opcode/ppc.h (PPC_OPCODE_FUTURE): Define.

opcodes/
	* ppc-dis.c (ppc_opts) <future>: Use it.
	* ppc-opc.c (FUTURE): Define.
2022-09-12 14:56:20 -05:00
Tsukasa OI
9869e2e5c7 opcodes: Add non-enum disassembler options
This is paired with "gdb: Add non-enum disassembler options".

There is a portable mechanism for disassembler options and used on some
architectures:

-   ARC
-   Arm
-   MIPS
-   PowerPC
-   RISC-V
-   S/390

However, it only supports following forms:

-   [NAME]
-   [NAME]=[ENUM_VALUE]

Valid values for [ENUM_VALUE] must be predefined in
disasm_option_arg_t.values. For instance, for -M cpu=[CPU] in ARC
architecture, opcodes/arc-dis.c builds valid CPU model list from
include/elf/arc-cpu.def.

In this commit, it adds following format:

-   [NAME]=[ARBITRARY_VALUE] (cannot contain "," though)

This is identified by NULL value of disasm_option_arg_t.values
(normally, this is a non-NULL pointer to a NULL-terminated list).

include/ChangeLog:

	* dis-asm.h (disasm_option_arg_t): Update comment of values
	to allow non-enum disassembler options.

opcodes/ChangeLog:

	* riscv-dis.c (print_riscv_disassembler_options): Support
	non-enum disassembler options on printing disassembler help.
	* arc-dis.c (print_arc_disassembler_options): Likewise.
	* mips-dis.c (print_mips_disassembler_options): Likewise.
2022-09-06 02:23:21 +00:00
Tsukasa OI
0938b032da RISC-V: Add 'Zmmul' extension in assembler.
Three-part patch set from Tsukasa OI to support zmmul in assembler.

The 'Zmmul' is a RISC-V extension consisting of only multiply instructions
(a subset of 'M' which has multiply and divide instructions).

bfd/
	* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'.
	(riscv_supported_std_z_ext): Add 'Zmmul' extension.
	(riscv_multi_subset_supports): Add handling for new instruction class.
gas/
	* testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'.
	* testsuite/gas/riscv/option-arch-02.d: Likewise.
	* testsuite/gas/riscv/m-ext.s: New test.
	* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
	* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
	* testsuite/gas/riscv/zmmul-32.d: New expected output.
	* testsuite/gas/riscv/zmmul-64.d: Likewise.
	* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
	by using RV64-only instructions in RV32).
	* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
	* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test
	(RV32 + Zmmul but with no M).
	* testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise.
	* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test
	(RV64 + Zmmul but with no M).
	* testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise.
	* testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test
	(no Zmmul or M).
	* testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise.
include/
	* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL.
ld/
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in
	these testcases, so just replaced m by a.
	* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed.
	* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed.
opcodes/
	* riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
2022-08-30 17:46:11 +08:00
Dmitry Selyutin
59f08271dd ppc/svp64: introduce non-zero operand flag
svstep and svshape instructions subtract 1 before encoding some of the
operands. Obviously zero is not supported for these operands. Whilst
PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be
incremented, there is no flag which marks the fact that zero values are
not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this
purpose.
2022-08-11 18:38:29 +09:30
Dmitry Selyutin
33ae8a3ae3 ppc/svp64: support LibreSOC architecture
This patch adds support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.

For more details, visit https://libre-soc.org.
2022-08-11 18:38:29 +09:30
Fangrui Song
453595283c RISC-V: Remove R_RISCV_GNU_VTINHERIT/R_RISCV_GNU_VTENTRY
They were legacy relocation types copied from other ports.  The related
-fvtable-gc was removed from GCC in 2003.

The associated assembler directives (.vtable_inherit and .vtable_entry)
have never been supported by the RISC-V port.  Remove related ld code.

Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/323
2022-08-10 22:01:41 -07:00
Youling Tang
31f6009538 bfd: Add support for LoongArch64 EFI (efi-*-loongarch64).
This adds support for efi-loongarch64 by virtue of adding a new PEI target
pei-loongarch64.  This is not a full target and only exists to support EFI at
this time.

This means that this target does not support relocation processing and is mostly
a container format.  This format has been added to elf based loongarch64 targets
such that efi images can be made natively on Linux.

However this target is not valid for use with gas but only with objcopy.

We should't limit addresses to 32-bits for 64-bit vma, otherwise there will be
"RVA truncated" error when using objcopy on loongarch64.

With these changes the resulting file is recognized as an efi image.

Any magic number is based on the Microsoft PE specification [1].

The test results are as follows:
$ make check-binutils RUNTESTFLAGS='loongarch64.exp'
  PASS: Check if efi app format is recognized

$ objdump -h -f tmpdir/loongarch64copy.o
  tmpdir/loongarch64copy.o:     file format pei-loongarch64
  architecture: Loongarch64, flags 0x00000132:
  EXEC_P, HAS_SYMS, HAS_LOCALS, D_PAGED
  start address 0x0000000000000000

  Sections:
  Idx Name          Size      VMA               LMA               File off  Algn
    0 .text         0000003c  00000000200000b0  00000000200000b0  00000200  2**2
                    CONTENTS, ALLOC, LOAD, READONLY, CODE

[1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format

bfd:
  * .gitignore (pe-loongarch64igen.c): New.
  * Makefile.am (pei-loongarch64.lo, pe-loongarch64igen.lo, pei-loongarch64.c,
  pe-loongarch64igen.c): Add support.
  * Makefile.in: Likewise.
  * bfd.c (bfd_get_sign_extend_vma): Add pei-loongarch64.
  * coff-loongarch64.c: New file.
  * coffcode.h (coff_set_arch_mach_hook, coff_set_flags,
  coff_write_object_contents) Add loongarch64 (loongarch64_pei_vec) support.
  * config.bfd: Likewise.
  * configure: Likewise.
  * configure.ac: Likewise.
  * libpei.h (GET_OPTHDR_IMAGE_BASE, PUT_OPTHDR_IMAGE_BASE,
  GET_OPTHDR_SIZE_OF_STACK_RESERVE, PUT_OPTHDR_SIZE_OF_STACK_RESERVE,
  GET_OPTHDR_SIZE_OF_STACK_COMMIT, PUT_OPTHDR_SIZE_OF_STACK_COMMIT,
  GET_OPTHDR_SIZE_OF_HEAP_RESERVE, PUT_OPTHDR_SIZE_OF_HEAP_RESERVE,
  GET_OPTHDR_SIZE_OF_HEAP_COMMIT, PUT_OPTHDR_SIZE_OF_HEAP_COMMIT,
  GET_PDATA_ENTRY, _bfd_peLoongArch64_bfd_copy_private_bfd_data_common,
  _bfd_peLoongArch64_bfd_copy_private_section_data,
  _bfd_peLoongArch64_get_symbol_info, _bfd_peLoongArch64_only_swap_filehdr_out,
  _bfd_peLoongArch64_print_private_bfd_data_common,
  _bfd_peLoongArch64i_final_link_postscript,
  _bfd_peLoongArch64i_only_swap_filehdr_out, _bfd_peLoongArch64i_swap_aouthdr_in,
  _bfd_peLoongArch64i_swap_aouthdr_out, _bfd_peLoongArch64i_swap_aux_in,
  _bfd_peLoongArch64i_swap_aux_out, _bfd_peLoongArch64i_swap_lineno_in,
  _bfd_peLoongArch64i_swap_lineno_out, _bfd_peLoongArch64i_swap_scnhdr_out,
  _bfd_peLoongArch64i_swap_sym_in, _bfd_peLoongArch64i_swap_sym_out,
  _bfd_peLoongArch64i_swap_debugdir_in, _bfd_peLoongArch64i_swap_debugdir_out,
  _bfd_peLoongArch64i_write_codeview_record,
  _bfd_peLoongArch64i_slurp_codeview_record,
  _bfd_peLoongArch64_print_ce_compressed_pdata): New.
  * peXXigen.c (_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out,
  _bfd_XXi_swap_scnhdr_out, pe_print_pdata, _bfd_XX_print_private_bfd_data_common,
  _bfd_XX_bfd_copy_private_section_data, _bfd_XXi_final_link_postscript):
  Support COFF_WITH_peLoongArch64,
  * pei-loongarch64.c: New file.
  * peicode.h (coff_swap_scnhdr_in, pe_ILF_build_a_bfd, pe_ILF_object_p):
  Support COFF_WITH_peLoongArch64.
  (jtab): Add dummy entry that traps.
  * targets.c (loongarch64_pei_vec): New.

binutils
  * testsuite/binutils-all/loongarch64/loongarch64.exp: New file.
  * testsuite/binutils-all/loongarch64/pei-loongarch64.d: New test.
  * testsuite/binutils-all/loongarch64/pei-loongarch64.s: New test.

include
  * coff/loongarch64.h: New file.
  * coff/pe.h (IMAGE_FILE_MACHINE_LOONGARCH64): New.

Signed-off-by: Youling Tang <tangyouling@loongson.cn>
2022-08-10 09:26:25 +08:00
Cary Coutant
03d0ae791f Add ELFCOMPRESS_ZSTD.
include/elf/
	* common.h: Add ELFCOMPRESS_ZSTD.
2022-08-02 16:19:43 -07:00
Andrew Burgess
76a4c1e063 libopcodes/aarch64: add support for disassembler styling
This commit enables disassembler styling for AArch64.  After this
commit it is possible to have objdump style AArch64 disassembler
output (using --disassembler-color option).  Once the required GDB
patches are merged, GDB will also style the disassembler output.

The changes to support styling are mostly split between two files
opcodes/aarch64-dis.c and opcodes/aarch64-opc.c.

The entry point for the AArch64 disassembler can be found in
aarch64-dis.c, this file handles printing the instruction mnemonics,
and assembler directives (e.g. '.byte', '.word', etc).  Some operands,
mostly relating to assembler directives are also printed from this
file.  This commit changes all of this to pass through suitable
styling information.

However, for most "normal" instructions, the instruction operands are
printed using a two step process.  From aarch64-dis.c, in the
print_operands function, the function aarch64_print_operand is called,
this function is in aarch64-opc.c, and converts an instruction operand
into a string.  Then, back in print_operands (aarch64-dis.c), the
operand string is printed.

Unfortunately, the string returned by aarch64_print_operand can be
quite complex, it will include syntax elements, like '[' and ']', in
addition to register names and immediate values.  In some cases, a
single operand will expand into what will appear (to the user) as
multiple operands separated with a ','.

This makes the task of styling more complex, all these different
components need to by styled differently, so we need to get the
styling information out of aarch64_print_operand in some way.

The solution that I propose here is similar to the solution that I
used for the i386 disassembler.

Currently, aarch64_print_operand uses snprintf to write the operand
text into a buffer provided by the caller.

What I propose is that we pass an extra argument to the
aarch64_print_operand function, this argument will be a structure, the
structure contains a callback function and some state.

When aarch64_print_operand needs to format part of its output this can
be done by using the callback function within the new structure, this
callback returns a string with special embedded markers that indicate
which mode should be used for each piece of text.  Back in
aarch64-dis.c we can spot these special style markers and use this to
split the disassembler output up and apply the correct style to each
piece.

To make aarch64-opc.c clearer a series of new static functions have
been added, e.g. 'style_reg', 'style_imm', etc.  Each of these
functions formats a piece of text in a different style, 'register' and
'immediate' in this case.

Here's an example taken from aarch64-opc.c of the new functions in
use:

    snprintf (buf, size, "[%s, %s]!",
              style_reg (styler, base),
              style_imm (styler, "#%d", opnd->addr.offset.imm));

The aarch64_print_operand function is also called from the assembler
to aid in printing diagnostic messages.  Right now I have no plans to
add styling to the assembler output, and so, the callback function
used in the assembler ignores the styling information and just returns
an plain string.

I've used the source files in gas/testsuite/gas/aarch64/ for testing,
and have manually gone through and checked that the styling looks
reasonable, however, I'm not an AArch64 expert, so it is possible that
the odd piece is styled incorrectly.  Please point out any mistakes
I've made.

With objdump disassembler color turned off, there should be no change
in the output after this commit.
2022-07-29 13:58:32 +01:00
Andrew Burgess
4f46c0bc36 opcodes: add new sub-mnemonic disassembler style
When adding libopcodes disassembler styling support for AArch64, it
feels like the results would be improved by having a new sub-mnemonic
style.  This will be used in cases like:

  add    w16, w7, w1, uxtb #2
                      ^^^^----- Here

And:

  cinc   w0, w1, ne
                 ^^----- Here

This commit just adds the new style, and prepares objdump to handle
the style.  A later commit will add AArch64 styling, and will actually
make use of the style.

As this style is currently unused, there should be no user visible
changes after this commit.
2022-07-25 14:02:30 +01:00
liuzhensong
9801120721 bfd: Delete R_LARCH_NONE from dyn info of LoongArch.
Some R_LARCH_64 in section .eh_frame will to generate
  R_LARCH_NONE, we change relocation to R_LARCH_32_PCREL
  from R_LARCH_64 in setction .eh_frame and not generate
  dynamic relocation for R_LARCH_32_PCREL.

  Add New relocate type R_LARCH_32_PCREL for .eh_frame.

  include/elf/
    loongarch.h

  bfd/
    bfd/bfd-in2.h
    libbfd.h
    reloc.c
    elfxx-loongarch.c
    elfnn-loongarch.c

  gas/config/
    tc-loongarch.c

  binutils/
    readelf.c

  ld/testsuite/ld-elf/
    eh5.d
2022-07-25 09:59:08 +08:00
liuzhensong
6d13722a97 bfd: Add supported for LoongArch new relocations.
Define new reloc types according to linker needs.

  include/elf/
    loongarch.h

  bfd/
    bfd-in2.h
    libbfd.h
    reloc.c
    elfnn-loongarch.c
    elfxx-loongarch.c
    elfxx-loongarch.h
2022-07-25 09:59:08 +08:00
Luis Machado
d0ff5ca959 [AArch64] Support AArch64 MTE memory tag dumps in core files
The Linux kernel can dump memory tag segments to a core file, one segment
per mapped range. The format and documentation can be found in the Linux
kernel tree [1].

The following patch adjusts bfd and binutils so they can handle this new
segment type and display it accordingly. It also adds code required so GDB
can properly read/dump core file data containing memory tags.

Upon reading, each segment that contains memory tags gets mapped to a
section named "memtag". These sections will be used by GDB to lookup the tag
data. There can be multiple such sections with the same name, and they are not
numbered to simplify GDB's handling and lookup.

There is another patch for GDB that enables both reading
and dumping of memory tag segments.

Tested on aarch64-linux Ubuntu 20.04.

[1] Documentation/arm64/memory-tagging-extension.rst (Core Dump Support)
2022-07-19 15:24:27 +01:00
Martin Liska
98f49277b5 LTO plugin: sync header file with GCC
include/ChangeLog:

	* plugin-api.h (enum ld_plugin_tag): Sync with GCC.
2022-07-12 15:35:00 +02:00
Nick Clifton
0bd0932314 Add markers for 2.39 branch 2022-07-08 10:41:07 +01:00
Tsukasa OI
045f385d9a RISC-V: Added Zfhmin and Zhinxmin.
This commit adds Zfhmin and Zhinxmin extensions (subsets of Zfh and
Zhinx extensions, respectively).  In the process supporting Zfhmin and
Zhinxmin extension, this commit also changes how instructions are
categorized considering Zfhmin, Zhinx and Zhinxmin extensions.

Detailed changes,

* From INSN_CLASS_ZFH to INSN_CLASS_ZFHMIN:

flh, fsh, fmv.x.h and fmv.h.x.

* From INSN_CLASS_ZFH to INSN_CLASS_ZFH_OR_ZHINX:

fmv.h.

* From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFH_OR_ZHINX:

fneg.h, fabs.h, fsgnj.h, fsgnjn.h, fsgnjx.h,
fadd.h, fsub.h, fmul.h, fdiv.h, fsqrt.h, fmin.h, fmax.h,
fmadd.h, fnmadd.h, fmsub.h, fnmsub.h,
fcvt.w.h, fcvt.wu.h, fcvt.h.w, fcvt.h.wu,
fcvt.l.h, fcvt.lu.h, fcvt.h.l, fcvt.h.lu,
feq.h, flt.h, fle.h, fgt.h, fge.h,
fclass.h.

* From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFHMIN_OR_ZHINXMIN:

fcvt.s.h and fcvt.h.s.

* From INSN_CLASS_D_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_D:

fcvt.d.h and fcvt.h.d.

* From INSN_CLASS_Q_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_Q:

fcvt.q.h and fcvt.h.q.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Change implicit
	subsets.  Zfh->Zicsr is not needed and Zfh->F is replaced with
	Zfh->Zfhmin and Zfhmin->F.  Zhinx->Zicsr is not needed and
	Zhinx->Zfinx is replaced with Zhinx->Zhinxmin and
	Zhinxmin->Zfinx.
	(riscv_supported_std_z_ext): Added zfhmin and zhinxmin.
	(riscv_multi_subset_supports):  Rewrite handling for new
	instruction classes.
	(riscv_multi_subset_supports_ext): Updated.
	(riscv_parse_check_conflicts): Change error message to include
	zfh and zfhmin extensions.

gas/ChangeLog:

	* testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: New complex
	error handling test.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Likewise.
	* testsuite/gas/riscv/zhinx.d: Renamed from fp-zhinx-insns.d
	and refactored.
	* testsuite/gas/riscv/zhinx.s: Likewise.

include/ChangeLog:

	* opcode/riscv.h (enum riscv_insn_class): Removed INSN_CLASS_ZFH,
	INSN_CLASS_D_AND_ZFH_INX and INSN_CLASS_Q_AND_ZFH_INX.  Added
	INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN,
	INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Change instruction classes for
	Zfh and Zfhmin instructions.  Fix `fcvt.h.lu' instruction
	(two operand variant) mask.
2022-07-07 16:23:54 +08:00
Andrew Burgess
6837a663c5 opcodes/aarch64: split off creation of comment text in disassembler
The function aarch64_print_operand (aarch64-opc.c) is responsible for
converting an instruction operand into the textual representation of
that operand.

In some cases, a comment is included in the operand representation,
though this (currently) only happens for the last operand of the
instruction.

In a future commit I would like to enable the new libopcodes styling
for AArch64, this will allow objdump and GDB[1] to syntax highlight
the disassembler output, however, having operands and comments
combined in a single string like this makes such styling harder.

In this commit, I propose to extend aarch64_print_operand to take a
second buffer.  Any comments for the instruction are written into this
extra buffer.  The two callers of aarch64_print_operand are then
updated to pass an extra buffer, and print any resulting comment.

In this commit no styling is added, that will come later.  However, I
have adjusted the output slightly.  Before this commit some comments
would be separated from the instruction operands with a tab character,
while in other cases the comment was separated with two single spaces.

After this commit I use a single tab character in all cases.  This
means a few test cases needed updated.  If people would prefer me to
move everyone to use the two spaces, then just let me know.  Or maybe
there was a good reason why we used a mix of styles, I could probably
figure out a way to maintain the old output exactly if that is
critical.

Other than that, there should be no user visible changes after this
commit.

[1] GDB patches have not been merged yet, but have been posted to the
GDB mailing list:
https://sourceware.org/pipermail/gdb-patches/2022-June/190142.html
2022-06-29 12:03:22 +01:00
Tsukasa OI
766077c173 RISC-V: Add 'Sstc' extension and its CSRs
This commit adds "stimecmp / vstimecmp" Extension (Sstc) and its CSRs.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sstc'
	extension to valid 'S' extension list.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for
	'Sstc' extension. (riscv_csr_address): Add handling for new CSR
	classes.
	* testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr.s: Add new CSRs.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (CSR_STIMECMP, CSR_STIMECMPH,
	CSR_VSTIMECMP, CSR_VSTIMECMPH): New CSR macros.
2022-06-28 09:08:42 +08:00
Tsukasa OI
713f370809 RISC-V: Add 'Sscofpmf' extension with its CSRs
This commit adds Count Overflow and Mode-Based Filtering Extension
(Sscofpmf) and its CSRs.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sscofpmf'
	extension to valid 'S' extension list.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for
	'Sscofpmf' extension. (riscv_csr_address): Add handling for new
	CSR classes.
	* testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr.s: Add new CSRs.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (CSR_SCOUNTOVF, CSR_MHPMEVENT3H,
	CSR_MHPMEVENT4H, CSR_MHPMEVENT5H, CSR_MHPMEVENT6H,
	CSR_MHPMEVENT7H, CSR_MHPMEVENT8H, CSR_MHPMEVENT9H,
	CSR_MHPMEVENT10H, CSR_MHPMEVENT11H, CSR_MHPMEVENT12H,
	CSR_MHPMEVENT13H, CSR_MHPMEVENT14H, CSR_MHPMEVENT15H,
	CSR_MHPMEVENT16H, CSR_MHPMEVENT17H, CSR_MHPMEVENT18H,
	CSR_MHPMEVENT19H, CSR_MHPMEVENT20H, CSR_MHPMEVENT21H,
	CSR_MHPMEVENT22H, CSR_MHPMEVENT23H, CSR_MHPMEVENT24H,
	CSR_MHPMEVENT25H, CSR_MHPMEVENT26H, CSR_MHPMEVENT27H,
	CSR_MHPMEVENT28H, CSR_MHPMEVENT29H, CSR_MHPMEVENT30H,
	CSR_MHPMEVENT31H): New CSR macros.
2022-06-28 09:08:06 +08:00
Tsukasa OI
6af47b081e RISC-V: Add 'Smstateen' extension and its CSRs
This commit adds State Enable Extension (Smstateen) and its CSRs.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Smstateen'
	extension to valid 'S' extension list.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for
	'Smstateen' extension. (riscv_csr_address): Add handling for
	new CSR classes.
	* testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr.s: Add new CSRs.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (CSR_MSTATEEN0, CSR_MSTATEEN1,
	CSR_MSTATEEN2, CSR_MSTATEEN3, CSR_SSTATEEN0, CSR_SSTATEEN1,
	CSR_SSTATEEN2, CSR_SSTATEEN3, CSR_HSTATEEN0, CSR_HSTATEEN1,
	CSR_HSTATEEN2, CSR_HSTATEEN3, CSR_MSTATEEN0H, CSR_MSTATEEN1H,
	CSR_MSTATEEN2H, CSR_MSTATEEN3H, CSR_HSTATEEN0H, CSR_HSTATEEN1H,
	CSR_HSTATEEN2H, CSR_HSTATEEN3H): New CSR macros.
2022-06-28 09:07:25 +08:00
Jan Beulich
ddd7bf3e28 drop XC16x bits
Commit 04f096fb9e ("Move the xc16x target to the obsolete list") moved
the architecture from the "obsolete but still available" to the
"obsolete / support removed" list in config.bfd, making the architecture
impossible to enable (except maybe via "enable everything" options").

Note that I didn't touch */po/*.po{,t} on the assumption that these
would be updated by some (half)automatic means.
2022-06-27 11:11:46 +02:00
Nelson Chu
c625f4ed05 RISC-V: Use single h extension to control hypervisor CSRs and instructions.
According to the picture 28.1 in the current ISA spec, h is no larger the
multi-letter extension, it is a single extension after v.  Therefore, this
patch fix the implementation, and use the single h to control hypervisor
CSRs and instructions, which we promised to do before.

bfd/
    * elfxx-riscv.c (riscv_supported_std_ext): Added h with version 1.0 after v.
    (riscv_supported_std_h_ext): Removed.
    (riscv_all_supported_ext): Updated since riscv_supported_std_h_ext is removed.
    (riscv_prefix_ext_class): Removed RV_ISA_CLASS_H.
    (parse_config): Updated since riscv_prefix_ext_class is removed.
    (riscv_recognized_prefixed_ext): Likewise.
    (riscv_get_default_ext_version): Likewise.
    (riscv_multi_subset_supports): Handle INSN_CLASS_H for hypervisor instructions.
    (riscv_multi_subset_supports_ext): Likewise.
gas/
    * config/tc-riscv.c (riscv_csr_class): Added CSR_CLASS_H and CSR_CLASS_H_32 for
    hypervisor CSRs.
    (riscv_csr_address): Likewise.
    * testsuite/gas/riscv/csr-version-1p10.d: Updated since hypervisor CSRs are
    controlled by single h extension for now.
    * testsuite/gas/riscv/csr-version-1p10.l: Likewise.
    * testsuite/gas/riscv/csr-version-1p11.d: Likewise.
    * testsuite/gas/riscv/csr-version-1p11.l: Likewise.
    * testsuite/gas/riscv/csr-version-1p12.d: Likewise.
    * testsuite/gas/riscv/csr-version-1p12.l: Likewise.
    * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
    * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
    * testsuite/gas/riscv/h-ext-32.d: Added h to architecture string.
    * testsuite/gas/riscv/h-ext-64.d: Likewise.
    * testsuite/gas/riscv/march-fail-single-prefix-h: Removed since h is no
    longer multi-letter extension.
    * testsuite/gas/riscv/march-fail-unknown-h.d: Likewise.
include/
    * opcode/riscv-opc.h: Control hypervisor CSRs by h extension, rather than
    the privileged spec verisons.
    * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_H.
opcodes/
    * riscv-opc.c (riscv_opcodes): Control hypervisor instructions by h extension.
2022-06-22 18:13:37 +08:00