Commit Graph

3089 Commits

Author SHA1 Message Date
Jim Wilson
4e2b18982a RISC-V: bge[u] should get higher priority than ble[u].
2018-09-17  Kito Cheng  <kito@andestech.com>
gas/
	* testsuite/gas/riscv/bge.d: New.
	* testsuite/gas/riscv/bge.s: Likewise.
opcodes/
	* riscv-opc.c (riscv_opcodes): Adjust the order of ble and
	  bleu.
2018-09-17 11:43:08 -07:00
H.J. Lu
04e2a1829e x86: Set EVex=2 on EVEX.128 only vmovd and vmovq
EVEX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64",
"VMOVD r64/m64, xmm2", "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2"
can only be encoded with EVEX.128.  Set EVex=2 on EVEX.128 only vmovd and
vmovq.

gas/

	PR gas/23670
	* testsuite/gas/i386/evex-lig-2.d: New file.
	* testsuite/gas/i386/evex-lig-2.s: Likewise.
	* testsuite/gas/i386/x86-64-evex-lig-2.d: Likewise.
	* testsuite/gas/i386/x86-64-evex-lig-2.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run evex-lig-2 and
	x86-64-evex-lig-2.

opcodes/

	PR gas/23670
	* i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
	EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
	(EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
	(EVEX_LEN_0F7E_P_1): Likewise.
	(EVEX_LEN_0F7E_P_2): Likewise.
	(EVEX_LEN_0FD6_P_2): Likewise.
	* i386-dis.c (USE_EVEX_LEN_TABLE): New.
	(EVEX_LEN_TABLE): Likewise.
	(EVEX_LEN_0F6E_P_2): New enum.
	(EVEX_LEN_0F7E_P_1): Likewise.
	(EVEX_LEN_0F7E_P_2): Likewise.
	(EVEX_LEN_0FD6_P_2): Likewise.
	(evex_len_table): New.
	(get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
	* i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
	* i386-tbl.h: Regenerated.
2018-09-17 09:33:35 -07:00
H.J. Lu
d5f787c2bc x86: Set Vex=1 on VEX.128 only vmovd and vmovq
AVX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64"
and "VMOVD r64/m64, xmm2" can only be encoded with VEX.128.  Set Vex=1
on VEX.128 only vmovd and vmovq.

gas/

	PR gas/23665
	* testsuite/gas/i386/avx-scalar.s: Remove vmovq and vmovd tests.
	* testsuite/gas/i386/x86-64-avx-scalar.s: Likewise.
	* testsuite/gas/i386/avx-scalar-intel.d: Updated.
	* testsuite/gas/i386/avx-scalar.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-scalar.d: Likewise.
	* testsuite/gas/i386/i386.exp: Run avx-scalar2 and
	x86-64-avx-scalar2.
	* testsuite/gas/i386/avx-scalar-2.d: New file.
	* testsuite/gas/i386/avx-scalar-2.s: Likewise.
	* testsuite/gas/i386/x86-64-avx-scalar-2.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-scalar-2.s: Likewise.

opcodes/

	PR gas/23665
	* i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
	VEX_LEN_0F7E_P_2 entries.
	* i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
	* i386-tbl.h: Regenerated.
2018-09-17 09:31:17 -07:00
H.J. Lu
ec6f095abc x86: Update disassembler for VexWIG
The VEX.W bit is ignored by some VEX instructions, aka WIG instructions.
Update x86 disassembler to handle VEX WIG instructions.

	* i386-dis.c (VZERO_Fixup): Removed.
	(VZERO): Likewise.
	(VEX_LEN_0F10_P_1): Likewise.
	(VEX_LEN_0F10_P_3): Likewise.
	(VEX_LEN_0F11_P_1): Likewise.
	(VEX_LEN_0F11_P_3): Likewise.
	(VEX_LEN_0F2E_P_0): Likewise.
	(VEX_LEN_0F2E_P_2): Likewise.
	(VEX_LEN_0F2F_P_0): Likewise.
	(VEX_LEN_0F2F_P_2): Likewise.
	(VEX_LEN_0F51_P_1): Likewise.
	(VEX_LEN_0F51_P_3): Likewise.
	(VEX_LEN_0F52_P_1): Likewise.
	(VEX_LEN_0F53_P_1): Likewise.
	(VEX_LEN_0F58_P_1): Likewise.
	(VEX_LEN_0F58_P_3): Likewise.
	(VEX_LEN_0F59_P_1): Likewise.
	(VEX_LEN_0F59_P_3): Likewise.
	(VEX_LEN_0F5A_P_1): Likewise.
	(VEX_LEN_0F5A_P_3): Likewise.
	(VEX_LEN_0F5C_P_1): Likewise.
	(VEX_LEN_0F5C_P_3): Likewise.
	(VEX_LEN_0F5D_P_1): Likewise.
	(VEX_LEN_0F5D_P_3): Likewise.
	(VEX_LEN_0F5E_P_1): Likewise.
	(VEX_LEN_0F5E_P_3): Likewise.
	(VEX_LEN_0F5F_P_1): Likewise.
	(VEX_LEN_0F5F_P_3): Likewise.
	(VEX_LEN_0FC2_P_1): Likewise.
	(VEX_LEN_0FC2_P_3): Likewise.
	(VEX_LEN_0F3A0A_P_2): Likewise.
	(VEX_LEN_0F3A0B_P_2): Likewise.
	(VEX_W_0F10_P_0): Likewise.
	(VEX_W_0F10_P_1): Likewise.
	(VEX_W_0F10_P_2): Likewise.
	(VEX_W_0F10_P_3): Likewise.
	(VEX_W_0F11_P_0): Likewise.
	(VEX_W_0F11_P_1): Likewise.
	(VEX_W_0F11_P_2): Likewise.
	(VEX_W_0F11_P_3): Likewise.
	(VEX_W_0F12_P_0_M_0): Likewise.
	(VEX_W_0F12_P_0_M_1): Likewise.
	(VEX_W_0F12_P_1): Likewise.
	(VEX_W_0F12_P_2): Likewise.
	(VEX_W_0F12_P_3): Likewise.
	(VEX_W_0F13_M_0): Likewise.
	(VEX_W_0F14): Likewise.
	(VEX_W_0F15): Likewise.
	(VEX_W_0F16_P_0_M_0): Likewise.
	(VEX_W_0F16_P_0_M_1): Likewise.
	(VEX_W_0F16_P_1): Likewise.
	(VEX_W_0F16_P_2): Likewise.
	(VEX_W_0F17_M_0): Likewise.
	(VEX_W_0F28): Likewise.
	(VEX_W_0F29): Likewise.
	(VEX_W_0F2B_M_0): Likewise.
	(VEX_W_0F2E_P_0): Likewise.
	(VEX_W_0F2E_P_2): Likewise.
	(VEX_W_0F2F_P_0): Likewise.
	(VEX_W_0F2F_P_2): Likewise.
	(VEX_W_0F50_M_0): Likewise.
	(VEX_W_0F51_P_0): Likewise.
	(VEX_W_0F51_P_1): Likewise.
	(VEX_W_0F51_P_2): Likewise.
	(VEX_W_0F51_P_3): Likewise.
	(VEX_W_0F52_P_0): Likewise.
	(VEX_W_0F52_P_1): Likewise.
	(VEX_W_0F53_P_0): Likewise.
	(VEX_W_0F53_P_1): Likewise.
	(VEX_W_0F58_P_0): Likewise.
	(VEX_W_0F58_P_1): Likewise.
	(VEX_W_0F58_P_2): Likewise.
	(VEX_W_0F58_P_3): Likewise.
	(VEX_W_0F59_P_0): Likewise.
	(VEX_W_0F59_P_1): Likewise.
	(VEX_W_0F59_P_2): Likewise.
	(VEX_W_0F59_P_3): Likewise.
	(VEX_W_0F5A_P_0): Likewise.
	(VEX_W_0F5A_P_1): Likewise.
	(VEX_W_0F5A_P_3): Likewise.
	(VEX_W_0F5B_P_0): Likewise.
	(VEX_W_0F5B_P_1): Likewise.
	(VEX_W_0F5B_P_2): Likewise.
	(VEX_W_0F5C_P_0): Likewise.
	(VEX_W_0F5C_P_1): Likewise.
	(VEX_W_0F5C_P_2): Likewise.
	(VEX_W_0F5C_P_3): Likewise.
	(VEX_W_0F5D_P_0): Likewise.
	(VEX_W_0F5D_P_1): Likewise.
	(VEX_W_0F5D_P_2): Likewise.
	(VEX_W_0F5D_P_3): Likewise.
	(VEX_W_0F5E_P_0): Likewise.
	(VEX_W_0F5E_P_1): Likewise.
	(VEX_W_0F5E_P_2): Likewise.
	(VEX_W_0F5E_P_3): Likewise.
	(VEX_W_0F5F_P_0): Likewise.
	(VEX_W_0F5F_P_1): Likewise.
	(VEX_W_0F5F_P_2): Likewise.
	(VEX_W_0F5F_P_3): Likewise.
	(VEX_W_0F60_P_2): Likewise.
	(VEX_W_0F61_P_2): Likewise.
	(VEX_W_0F62_P_2): Likewise.
	(VEX_W_0F63_P_2): Likewise.
	(VEX_W_0F64_P_2): Likewise.
	(VEX_W_0F65_P_2): Likewise.
	(VEX_W_0F66_P_2): Likewise.
	(VEX_W_0F67_P_2): Likewise.
	(VEX_W_0F68_P_2): Likewise.
	(VEX_W_0F69_P_2): Likewise.
	(VEX_W_0F6A_P_2): Likewise.
	(VEX_W_0F6B_P_2): Likewise.
	(VEX_W_0F6C_P_2): Likewise.
	(VEX_W_0F6D_P_2): Likewise.
	(VEX_W_0F6F_P_1): Likewise.
	(VEX_W_0F6F_P_2): Likewise.
	(VEX_W_0F70_P_1): Likewise.
	(VEX_W_0F70_P_2): Likewise.
	(VEX_W_0F70_P_3): Likewise.
	(VEX_W_0F71_R_2_P_2): Likewise.
	(VEX_W_0F71_R_4_P_2): Likewise.
	(VEX_W_0F71_R_6_P_2): Likewise.
	(VEX_W_0F72_R_2_P_2): Likewise.
	(VEX_W_0F72_R_4_P_2): Likewise.
	(VEX_W_0F72_R_6_P_2): Likewise.
	(VEX_W_0F73_R_2_P_2): Likewise.
	(VEX_W_0F73_R_3_P_2): Likewise.
	(VEX_W_0F73_R_6_P_2): Likewise.
	(VEX_W_0F73_R_7_P_2): Likewise.
	(VEX_W_0F74_P_2): Likewise.
	(VEX_W_0F75_P_2): Likewise.
	(VEX_W_0F76_P_2): Likewise.
	(VEX_W_0F77_P_0): Likewise.
	(VEX_W_0F7C_P_2): Likewise.
	(VEX_W_0F7C_P_3): Likewise.
	(VEX_W_0F7D_P_2): Likewise.
	(VEX_W_0F7D_P_3): Likewise.
	(VEX_W_0F7E_P_1): Likewise.
	(VEX_W_0F7F_P_1): Likewise.
	(VEX_W_0F7F_P_2): Likewise.
	(VEX_W_0FAE_R_2_M_0): Likewise.
	(VEX_W_0FAE_R_3_M_0): Likewise.
	(VEX_W_0FC2_P_0): Likewise.
	(VEX_W_0FC2_P_1): Likewise.
	(VEX_W_0FC2_P_2): Likewise.
	(VEX_W_0FC2_P_3): Likewise.
	(VEX_W_0FD0_P_2): Likewise.
	(VEX_W_0FD0_P_3): Likewise.
	(VEX_W_0FD1_P_2): Likewise.
	(VEX_W_0FD2_P_2): Likewise.
	(VEX_W_0FD3_P_2): Likewise.
	(VEX_W_0FD4_P_2): Likewise.
	(VEX_W_0FD5_P_2): Likewise.
	(VEX_W_0FD6_P_2): Likewise.
	(VEX_W_0FD7_P_2_M_1): Likewise.
	(VEX_W_0FD8_P_2): Likewise.
	(VEX_W_0FD9_P_2): Likewise.
	(VEX_W_0FDA_P_2): Likewise.
	(VEX_W_0FDB_P_2): Likewise.
	(VEX_W_0FDC_P_2): Likewise.
	(VEX_W_0FDD_P_2): Likewise.
	(VEX_W_0FDE_P_2): Likewise.
	(VEX_W_0FDF_P_2): Likewise.
	(VEX_W_0FE0_P_2): Likewise.
	(VEX_W_0FE1_P_2): Likewise.
	(VEX_W_0FE2_P_2): Likewise.
	(VEX_W_0FE3_P_2): Likewise.
	(VEX_W_0FE4_P_2): Likewise.
	(VEX_W_0FE5_P_2): Likewise.
	(VEX_W_0FE6_P_1): Likewise.
	(VEX_W_0FE6_P_2): Likewise.
	(VEX_W_0FE6_P_3): Likewise.
	(VEX_W_0FE7_P_2_M_0): Likewise.
	(VEX_W_0FE8_P_2): Likewise.
	(VEX_W_0FE9_P_2): Likewise.
	(VEX_W_0FEA_P_2): Likewise.
	(VEX_W_0FEB_P_2): Likewise.
	(VEX_W_0FEC_P_2): Likewise.
	(VEX_W_0FED_P_2): Likewise.
	(VEX_W_0FEE_P_2): Likewise.
	(VEX_W_0FEF_P_2): Likewise.
	(VEX_W_0FF0_P_3_M_0): Likewise.
	(VEX_W_0FF1_P_2): Likewise.
	(VEX_W_0FF2_P_2): Likewise.
	(VEX_W_0FF3_P_2): Likewise.
	(VEX_W_0FF4_P_2): Likewise.
	(VEX_W_0FF5_P_2): Likewise.
	(VEX_W_0FF6_P_2): Likewise.
	(VEX_W_0FF7_P_2): Likewise.
	(VEX_W_0FF8_P_2): Likewise.
	(VEX_W_0FF9_P_2): Likewise.
	(VEX_W_0FFA_P_2): Likewise.
	(VEX_W_0FFB_P_2): Likewise.
	(VEX_W_0FFC_P_2): Likewise.
	(VEX_W_0FFD_P_2): Likewise.
	(VEX_W_0FFE_P_2): Likewise.
	(VEX_W_0F3800_P_2): Likewise.
	(VEX_W_0F3801_P_2): Likewise.
	(VEX_W_0F3802_P_2): Likewise.
	(VEX_W_0F3803_P_2): Likewise.
	(VEX_W_0F3804_P_2): Likewise.
	(VEX_W_0F3805_P_2): Likewise.
	(VEX_W_0F3806_P_2): Likewise.
	(VEX_W_0F3807_P_2): Likewise.
	(VEX_W_0F3808_P_2): Likewise.
	(VEX_W_0F3809_P_2): Likewise.
	(VEX_W_0F380A_P_2): Likewise.
	(VEX_W_0F380B_P_2): Likewise.
	(VEX_W_0F3817_P_2): Likewise.
	(VEX_W_0F381C_P_2): Likewise.
	(VEX_W_0F381D_P_2): Likewise.
	(VEX_W_0F381E_P_2): Likewise.
	(VEX_W_0F3820_P_2): Likewise.
	(VEX_W_0F3821_P_2): Likewise.
	(VEX_W_0F3822_P_2): Likewise.
	(VEX_W_0F3823_P_2): Likewise.
	(VEX_W_0F3824_P_2): Likewise.
	(VEX_W_0F3825_P_2): Likewise.
	(VEX_W_0F3828_P_2): Likewise.
	(VEX_W_0F3829_P_2): Likewise.
	(VEX_W_0F382A_P_2_M_0): Likewise.
	(VEX_W_0F382B_P_2): Likewise.
	(VEX_W_0F3830_P_2): Likewise.
	(VEX_W_0F3831_P_2): Likewise.
	(VEX_W_0F3832_P_2): Likewise.
	(VEX_W_0F3833_P_2): Likewise.
	(VEX_W_0F3834_P_2): Likewise.
	(VEX_W_0F3835_P_2): Likewise.
	(VEX_W_0F3837_P_2): Likewise.
	(VEX_W_0F3838_P_2): Likewise.
	(VEX_W_0F3839_P_2): Likewise.
	(VEX_W_0F383A_P_2): Likewise.
	(VEX_W_0F383B_P_2): Likewise.
	(VEX_W_0F383C_P_2): Likewise.
	(VEX_W_0F383D_P_2): Likewise.
	(VEX_W_0F383E_P_2): Likewise.
	(VEX_W_0F383F_P_2): Likewise.
	(VEX_W_0F3840_P_2): Likewise.
	(VEX_W_0F3841_P_2): Likewise.
	(VEX_W_0F38DB_P_2): Likewise.
	(VEX_W_0F3A08_P_2): Likewise.
	(VEX_W_0F3A09_P_2): Likewise.
	(VEX_W_0F3A0A_P_2): Likewise.
	(VEX_W_0F3A0B_P_2): Likewise.
	(VEX_W_0F3A0C_P_2): Likewise.
	(VEX_W_0F3A0D_P_2): Likewise.
	(VEX_W_0F3A0E_P_2): Likewise.
	(VEX_W_0F3A0F_P_2): Likewise.
	(VEX_W_0F3A21_P_2): Likewise.
	(VEX_W_0F3A40_P_2): Likewise.
	(VEX_W_0F3A41_P_2): Likewise.
	(VEX_W_0F3A42_P_2): Likewise.
	(VEX_W_0F3A62_P_2): Likewise.
	(VEX_W_0F3A63_P_2): Likewise.
	(VEX_W_0F3ADF_P_2): Likewise.
	(VEX_LEN_0F77_P_0): New.
	(prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
	PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
	PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
	PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
	PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
	PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
	PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
	PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
	PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
	PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
	PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
	PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
	PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
	PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
	PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
	PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
	PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
	PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
	PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
	PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
	PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
	PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
	PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
	PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
	PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
	PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
	PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
	PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
	PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
	PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
	PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
	PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
	PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
	PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
	PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
	PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
	PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
	PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
	PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
	PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
	PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
	PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
	PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
	PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
	PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
	PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
	PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
	PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
	PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
	(vex_table): Update VEX 0F28 and 0F29 entries.
	(vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
	VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
	VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
	VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
	VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
	VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
	VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
	VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
	VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
	VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
	VEX_LEN_0F3A0B_P_2 entries.
	(vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
	VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
	VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
	VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
	VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
	VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
	VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
	VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
	VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
	VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
	VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
	VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
	VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
	VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
	VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
	VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
	VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
	VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
	VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
	VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
	VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
	VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
	VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
	VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
	VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
	VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
	VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
	VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
	VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
	VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
	VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
	VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
	VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
	VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
	VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
	VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
	VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
	VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
	VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
	VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
	VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
	VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
	VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
	VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
	VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
	VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
	VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
	VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
	VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
	VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
	VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
	VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
	VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
	VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
	VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
	VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
	VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
	VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
	VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
	VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
	VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
	VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
	VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
	VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
	VEX_W_0F3ADF_P_2 entries.
	(mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
	MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
	MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
2018-09-17 09:24:26 -07:00
H.J. Lu
6fa52824c3 x86: Replace VexW=3 with VexWIG
* i386-opc.tbl (VexWIG): New.
	Replace VexW=3 with VexWIG.
2018-09-17 06:12:06 -07:00
H.J. Lu
db4cc66567 x86: Set VexW=3 on AVX vrsqrtss
AVX vrsqrtss is a VEX WIG instruction.

	* i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
	* i386-tbl.h: Regenerated.
2018-09-15 17:10:17 -07:00
H.J. Lu
3c3741435f x86: Set Vex=1 on VEX.128 only vmovq
AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be
encoded with VEX.128.  Set Vex=1 on VEX.128 only vmovq and update
assembler tests.

gas/

	PR gas/23665
	* testsuite/gas/i386/avx-scalar-intel.d: Updated.
	* testsuite/gas/i386/avx-scalar.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-scalar.d: Likewise.

opcodes/

	PR gas/23665
	* i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
	VEX_LEN_0FD6_P_2 entries.
	* i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
	* i386-tbl.h: Regenerated.
2018-09-15 14:50:40 -07:00
H.J. Lu
6865c0435a x86: Support VEX/EVEX WIG encoding
Add VEXWIG, defined as 3, to indicate that the VEX.W/EVEX.W bit is
ignored by such VEX/EVEX instructions, aka WIG instructions.  Set
VexW=3 on VEX/EVEX WIG instructions.  Update assembler to check
VEXWIG when setting the VEX.W bit.

gas/

	PR gas/23642
	* config/tc-i386.c (build_vex_prefix): Check VEXWIG when setting
	the VEX.W bit.
	(build_evex_prefix): Check VEXWIG when setting the EVEX.W bit.

opcodes/

	PR gas/23642
	* i386-opc.h (VEXWIG): New.
	* i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
	* i386-tbl.h: Regenerated.
2018-09-14 12:20:10 -07:00
H.J. Lu
70df6fc9bc x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit mode
Update x86 disassembler to handle the unsupported static rounding in
vcvt[u]si2sd in 32-bit mode.

gas/

	PR binutils/23655
	* testsuite/gas/i386/evex.d: Updated.

opcodes/

	PR binutils/23655
	* i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
	vcvtsi2sd%LQ and vcvtusi2sd%LQ.
	* i386-dis.c (EXxEVexR64): New.
	(evex_rounding_64_mode): Likewise.
	(OP_Rounding): Handle evex_rounding_64_mode.
2018-09-14 11:25:13 -07:00
H.J. Lu
d20dee9efa x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit mode
Update x86 disassembler to ignore the EVEX.W bit in EVEX vcvt[u]si2s[sd]
instructions in 32-bit mode.

gas/

	PR binutils/23655
	* testsuite/gas/i386/evex.d: New file.
	* testsuite/gas/i386/evex.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run evex.

opcodes/

	PR binutils/23655
	* i386-dis-evex.h (evex_table): Replace Eq with Edqa for
	vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
	* i386-dis.c (Edqa): New.
	(dqa_mode): Likewise.
	(intel_operand_size): Handle dqa_mode as m_mode.
	(OP_E_register): Handle dqa_mode as dq_mode.
	(OP_E_memory): Set shift for dqa_mode based on address_mode.
2018-09-14 10:49:53 -07:00
H.J. Lu
5074ad8a66 i386: Reformat OP_E_memory
* i386-dis.c (OP_E_memory): Reformat.
2018-09-14 06:53:48 -07:00
Jan Beulich
556059dd13 x86: fold CRC32 templates
Just like other insns having byte and word forms, these can also make
use of the W modifier, which at the same time allows simplifying some
other code a little bit.
2018-09-14 11:21:15 +02:00
H.J. Lu
5be12fc1ad x86: Remove VexW=1 from WIG VEX movq and vmovq
Put back changes lost in commit 41d1ab6a6d.
2018-09-13 07:38:45 -07:00
H.J. Lu
41d1ab6a6d i386: Update VexW field for VEX instructions
1. Mark VEX.W0 VEX instructions with VexW=1.
2. Mark VEX.W1 VEX instructions with VexW=2.
3. Remove VexW=1 from WIG VEX instructions.

	* i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
	pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
	Add VexW=2 to VEX.W1 VEX movd, movq, pextrq, pinsrq, vmod, vmovq,
	vpextrq and vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
	* i386-tbl.h: Regenerated.
2018-09-13 06:21:19 -07:00
Jan Beulich
57f6375ec1 x86: drop bogus IgnoreSize from a few further insns 2018-09-13 11:26:06 +02:00
Jan Beulich
2589a7e59b x86: drop bogus IgnoreSize from AVX512_4* insns 2018-09-13 11:25:30 +02:00
Jan Beulich
a760eb41aa x86: drop bogus IgnoreSize from AVX512DQ insns 2018-09-13 11:24:53 +02:00
Jan Beulich
e90426589d x86: drop bogus IgnoreSize from AVX512BW insns 2018-09-13 11:24:23 +02:00
Jan Beulich
9caa306f80 x86: drop bogus IgnoreSize from AVX512VL insns 2018-09-13 11:23:50 +02:00
Jan Beulich
fb6ce599e0 x86: drop bogus IgnoreSize from AVX512ER insns 2018-09-13 11:23:17 +02:00
Jan Beulich
6a8da88669 x86: drop bogus IgnoreSize from AVX512F insns 2018-09-13 11:22:49 +02:00
Jan Beulich
c7f279191f x86: drop bogus IgnoreSize from SHA insns 2018-09-13 11:22:03 +02:00
Jan Beulich
0f407ee9f4 x86: drop bogus IgnoreSize from XOP and SSE4a insns 2018-09-13 11:21:36 +02:00
Jan Beulich
2fbbbee5e7 x86: drop bogus IgnoreSize from AVX2 insns 2018-09-13 11:19:21 +02:00
Jan Beulich
2b02b9a2ab x86: drop bogus IgnoreSize from AVX insns 2018-09-13 11:18:52 +02:00
Jan Beulich
963c68aa4a x86: drop bogus IgnoreSize from GNFI insns 2018-09-13 11:16:49 +02:00
Jan Beulich
64e025c3a1 x86: drop bogus IgnoreSize from PCLMUL/VPCLMUL insns 2018-09-13 11:16:19 +02:00
Jan Beulich
47603f888d x86: drop bogus IgnoreSize from AES/VAES insns 2018-09-13 11:15:38 +02:00
Jan Beulich
0001cfd00c x86: drop bogus IgnoreSize from SSE4.2 insns 2018-09-13 11:15:01 +02:00
Jan Beulich
be4b452e28 x86: drop bogus IgnoreSize from SSE4.1 insns 2018-09-13 11:14:32 +02:00
Jan Beulich
d09a13943b x86: drop bogus IgnoreSize from SSSE3 insns 2018-09-13 11:13:46 +02:00
Jan Beulich
07599e13ac x86: drop bogus IgnoreSize from SSE3 insns 2018-09-13 11:12:23 +02:00
Jan Beulich
1ee3e48715 x86: drop bogus IgnoreSize from SSE2 insns 2018-09-13 11:11:55 +02:00
Jan Beulich
a5f580e51a x86: drop bogus IgnoreSize from SSE insns 2018-09-13 11:11:26 +02:00
Jan Beulich
49d5d12d0e x86: drop unnecessary {,No}Rex64 2018-09-13 11:08:37 +02:00
Jan Beulich
f5eb1d70fb x86: also allow D on 3-operand insns
For now this is just for VMOVS{D,S}.
2018-09-13 11:07:55 +02:00
Jan Beulich
dbbc8b7e62 x86: use D attribute also for SIMD templates
Various moves come in load and store forms, and just like on the GPR
and FPU sides there would better be only one pattern. In some cases this
is not feasible because the opcodes are too different, but quite a few
cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and
Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse
operand handling there simply needs to match "straight" operand one),
and fix a long standing, but so far only latent bug with when to zap
found_reverse_match.

Also once again drop IgnoreSize where pointlessly applied to templates
touched anyway as well as *word when redundant with Reg*.
2018-09-13 11:07:07 +02:00
Jan Beulich
d276ec695e x86-64: bndmk, bndldx, and bndstx don't allow RIP-relative addressing 2018-09-13 11:03:35 +02:00
John Darrington
9da4dfd681 S12Z: Make disassebler work for --enable-targets=all config.
opcodes/
    * disassemble.c (ARCH_s12z): Define if ARCH_all.
2018-09-08 10:32:35 +02:00
Jim Wilson
be192bc284 RISC-V: Correct the requirement of compressed floating point instructions
2018-08-31  Kito Cheng  <kito@andestech.com>
gas/
	* testsuite/gas/riscv/c-fld-fsd-fail.d: New.
	* testsuite/gas/riscv/c-fld-fsd-fail.l: Likewise.
	* testsuite/gas/riscv/c-fld-fsd-fail.s: Likewise.
opcodes/
	* riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
	compressed floating point instructions.
2018-08-31 12:23:05 -07:00
Jim Wilson
43135d3b15 RISC-V: Allow instruction require more than one extension
2018-08-29  Kito Cheng  <kito@andestech.com>

gas/
	* config/tc-riscv.c (riscv_subset_supports): New argument:
	xlen_required.
	(riscv_multi_subset_supports): New function, able to check more
	than one extension.
	(riscv_ip): Use riscv_multi_subset_supports instead of
	riscv_subset_supports.
	(riscv_set_arch): Update call-site for riscv_subset_supports.
	(riscv_after_parse_args): Likewise.

include/
	*opcode/riscv.h (MAX_SUBSET_NUM): New.
	(riscv_opcode): Add xlen_requirement field and change type of
	subset.

opcodes/
	* riscv-dis.c (riscv_disassemble_insn): Check XLEN by
	riscv_opcode.xlen_requirement.
	* riscv-opc.c (riscv_opcodes): Update for struct change.
2018-08-30 13:23:12 -07:00
Martin Aberg
df28970fcc sparc/leon: add support for partial write psr instruction
Partial write %PSR (PWRPSR) is a SPARC V8e option that allows the WRPSR
instruction to only affect the %PSR.ET field. When available it is enabled
by setting the rd field of the WRPSR instruction to a value other than 0.
For Leon processors with support for partial write %PSR (currently GR740
and GR716) the rd value must be 1.

opcodes/ChangeLog:

2018-08-29  Martin Aberg  <maberg@gaisler.com>

        * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
        psr (PWRPSR) instruction.

gas/ChangeLog:

2018-08-29  Daniel Cederman  <cederman@gaisler.com>

        * testsuite/gas/sparc/leon.d: New test.
        * testsuite/gas/sparc/leon.s: New test.
        * testsuite/gas/sparc/sparc.exp: Execute the pwrpsr test.
2018-08-29 20:52:28 +02:00
Chenghua Xu
9108bc33b1 [MIPS] Add Loongson 2K1000 proccessor support.
bfd/
	* archures.c (bfd_architecture): New machine
	bfd_mach_mips_gs264e.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle
	E_MIPS_MACH_GS264E.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Map bfd_mach_mips_gs264e to
	bfd_mach_mips_gs464e extension.

binutils/
	* NEWS: Mention Loongson 2K1000 proccessor support.
	* readelf.c (get_machine_flags): Handle gs264e.

elfcpp/
	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
	(mips_cpu_info_table): Add gs264e descriptors.
	* doc/as.texi (march table): Add gs264e.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
	* opcode/mips.h (CPU_XXX): New CPU_GS264E.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
	gs264e and gs464e.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
2018-08-29 20:55:25 +08:00
Chenghua Xu
bd782c07b9 [MIPS] Add Loongson 3A2000/3A3000 proccessor support.
bfd/
	* archures.c (bfd_architecture): New machine
	bfd_mach_mips_gs464e.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle
	E_MIPS_MACH_GS464E.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Map bfd_mach_mips_gs464e to
	bfd_mach_mips_gs464 extension.

binutils/
	* NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
	* readelf.c (get_machine_flags): Handle gs464e.

elfcpp/
	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
	(mips_cpu_info_table): Add gs464e descriptors.
	* doc/as.texi (march table): Add gs464e.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
	* opcode/mips.h (CPU_XXX): New CPU_GS464E.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
	gs464e and gs464.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
2018-08-29 20:43:19 +08:00
Chenghua Xu
ac8cb70f36 [MIPS] Add Loongson 3A1000 proccessor support.
bfd/
	* archures.c (bfd_architecture): Rename
	bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Likewise.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Likewise.
	(bfd_mips_isa_ext_mach): Likewise.
	(bfd_mips_isa_ext): Likewise.
	(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.

binutils/
	* NEWS: Mention Loongson 3A1000 proccessor support.
	* readelf.c (get_machine_flags): Rename loongson-3a to gs464.
	(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.

elfcpp/
	* mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to
	E_MIPS_MACH_GS464.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename
	CPU_LOONGSON_3A to CPU_GS464.
	(mips_cpu_info_table): Add gs464 descriptors, Keep
	loongson3a as an alias of gs464 for compatibility.
	* doc/as.texi (march table): Rename loongson3a to gs464.
	* testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension"
	flag to None.

gold/
	* mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach):
	Rename loongson3a to gs464.
	(mips_isa_ext_mach, mips_isa_ext): Delete loongson3a.
	(infer_abiflags): Use ases instead of isa_ext for infer ABI
flags.
	(elf_mips_mach_name): Rename loongson3a to gs464.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
	E_MIPS_MACH_GS464.
	(AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
	* opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
	(CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
	* opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a
	to gs464.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
	loongson3a as an alias of gs464 for compatibility.
	* mips-opc.c (mips_opcodes): Change Comments.
2018-08-29 20:32:30 +08:00
Chenghua Xu
a693765e23 [MIPS/GAS] Add Loongson EXT2 Instructions support.
bfd/
	* elfxx-mips.c (print_mips_ases): Add Loongson EXT2 extension.

binutils/
	* readelf.c (print_mips_ases): Add Loongson EXT2 extension.

gas/
	* NEWS: Mention Loongson EXTensions R2 (EXT2) support.
	* config/tc-mips.c (options): Add OPTION_LOONGSON_EXT2 and
	OPTION_NO_LOONGSON_EXT2.
	(md_longopts): Likewise.
	(mips_ases): Define availability for EXT.
	(mips_convert_ase_flags): Map ASE_LOONGSON_EXT2 to
	AFL_ASE_LOONGSON_EXT2.
	(md_show_usage): Add help for -mloongson-ext2 and
	-mno-loongson-ext2.
	* doc/as.texi: Document -mloongson-ext2, -mno-loongson-ext2.
	* doc/c-mips.texi: Document -mloongson-ext2, -mno-loongson-ext2,
	.set loongson-ext2 and .set noloongson-ext2.
	* testsuite/gas/mips/loongson-ext2.d: New test.
	* testsuite/gas/mips/loongson-ext2.s: New test.
	* testsuite/gas/mips/mips.exp: Run loongson-ext2 test.

include/
	* elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
	* opcode/mips.h (ASE_LOONGSON_EXT2): New macro.

opcodes/
	* mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
	option.
	(print_mips_disassembler_options): Document -M loongson-ext.
	* mips-opc.c (LEXT2): New macro.
	(mips_opcodes): Add cto, ctz, dcto, dctz instructions.
2018-08-29 20:08:58 +08:00
Chenghua Xu
bdc6c06e3b [MIPS/GAS] Split Loongson EXT Instructions from loongson3a.
bfd/
	 * elfxx-mips.c (infer_mips_abiflags): Use ases instead of
	 isa_ext for infer ABI flags.
	 (print_mips_ases): Add Loongson EXT extension.

binutils/
	 * readelf.c (print_mips_ases): Add Loongson EXT extension.

elfcpp/
	 * mips.h (AFL_ASE_LOONGSON_EXT): New enum.

gas/
	 * NEWS: Mention Loongson EXTensions (EXT) support.
	 * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and
	 OPTION_NO_LOONGSON_EXT.
	 (md_longopts): Likewise.
	 (mips_ases): Define availability for EXT.
	 (mips_convert_ase_flags): Map ASE_LOONGSON_EXT to
	 AFL_ASE_LOONGSON_EXT.
	 (mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a.
	 (md_show_usage): Add help for -mloongson-ext and
	 -mno-loongson-ext.
	 * doc/as.texi: Document -mloongson-ext, -mno-loongson-ext.
	 * doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext,
	 .set loongson-ext and .set noloongson-ext.
	 * testsuite/gas/mips/loongson-mmi.d: Add ASE flag.

include/
	 * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
	 (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
	 * opcode/mips.h (ASE_LOONGSON_EXT): New macro.

opcodes/
	 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
	 descriptors.
	 (parse_mips_ase_option): Handle -M loongson-ext option.
	 (print_mips_disassembler_options): Document -M loongson-ext.
	 * mips-opc.c (IL3A): Delete.
	 * mips-opc.c (LEXT): New macro.
	 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
	 instructions.
2018-08-29 19:57:39 +08:00
Chenghua Xu
716c08de28 [MIPS/GAS] Split Loongson CAM Instructions from loongson3a
bfd/
	* elfxx-mips.c (print_mips_ases): Add CAM extension.

binutils/
	* readelf.c (print_mips_ases): Add CAM extension.

gas/
	* NEWS: Mention Loongson Content Address Memory (CAM)
	support.
	* config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and
	OPTION_NO_LOONGSON_CAM.
	(md_longopts): Likewise.
	(mips_ases): Define availability for CAM.
	(mips_convert_ase_flags): Map ASE_LOONGSON_CAM to
	AFL_ASE_LOONGSON_CAM.
	(mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a.
	(md_show_usage): Add help for -mloongson-cam and
	-mno-loongson-cam.
	* doc/as.texi: Document -mloongson-cam, -mno-loongson-cam.
	* doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam,
	.set loongson-cam and .set noloongson-cam.
	* testsuite/gas/mips/loongson-3a-2.d: Move cam test to ...
	* testsuite/gas/mips/loongson-cam.d: Here.  Add ISA/ASE
	flag verification.
	* testsuite/gas/mips/loongson-3a-2.s: Move cam test to ...
	* testsuite/gas/mips/loongson-cam.s: Here.
	* testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag.
	* testsuite/gas/mips/mips.exp: Run loongson-cam test.

include/
	* elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
	* opcode/mips.h (ASE_LOONGSON_CAM): New macro.

opcodes/
	* mips-dis.c (mips_arch_choices): Add CAM to loongson3a
	descriptors.
	(parse_mips_ase_option): Handle -M loongson-cam option.
	(print_mips_disassembler_options): Document -M loongson-cam.
	* mips-opc.c (LCAM): New macro.
	(mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
	instructions.
2018-08-29 19:33:09 +08:00
Alan Modra
9cf7e5687f Use operand->extract to provide defaults for optional PowerPC operands
Most optional operands to powerpc instructions use a default value of
zero, but there are a few exceptions.  Those have been handled by
PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table
for the default value, smuggled in the shift field.  This patch
changes that to using the operand extract function to provide non-zero
defaults.

I've also moved the code determining whether optional operands are
provided or omitted, to the point the first optional operand is seen,
and allowed for the possibility of optional base register operands
in a future patch.

The patch does change the error you get on invalid assembly like

  ld 3,4

You'll now see "missing operand" rather than
"syntax error; end of line, expected `('".

gas/
	* config/tc-ppc.c (md_assemble): Delay counting of optional
	operands until one is encountered.  Allow for the possibility
	of optional base regs, ie. PPC_OPERAND_PARENS.  Call
	ppc_optional_operand_value with extra args.
include/
	* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
	Mention use of "extract" function to provide default value.
	(PPC_OPERAND_OPTIONAL_VALUE): Delete.
	(ppc_optional_operand_value): Rewrite to use extract function.
opcodes/
	* ppc-dis.c (operand_value_powerpc): Init "invalid".
	(skip_optional_operands): Count optional operands, and update
	ppc_optional_operand_value call.
	* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
	(extract_vlensi): Likewise.
	(extract_fxm): Return default value for missing optional operand.
	(extract_ls, extract_raq, extract_tbr): Likewise.
	(insert_sxl, extract_sxl): New functions.
	(insert_esync, extract_esync): Remove Power9 handling and simplify.
	(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
	flag and extra entry.
	(powerpc_operands <SXL>): Likewise, and use insert_sxl and
	extract_sxl.
2018-08-21 16:05:36 +09:30
Alan Modra
08a8fe2ffd Fix s12z test regexps
Fixes
ERROR: tcl error sourcing .../gas/testsuite/gas/s12z/s12z.exp.
ERROR: couldn't compile regular expression pattern: quantifier operand invalid

run_dump_test expected output lines are regexps.

	* testsuite/gas/s12z/bit-manip-invalid.d: Correct regexps.
2018-08-21 14:59:53 +09:30