This adds software single step support that is needed by the linux native port.
This is modeled after equivalent code in the MIPS port.
This also fixes a few bugs in the compressed instruction decode support. Some
instructions are RV32/RV64 specific, and this wasn't being checked. Also, a
few instructions were accidentally using the non-compressed is_* function.
This has been tested on a HiFive Unleashed running Fedora, by putting a
breakpoint on start, typing stepi, and then holding down the return key until
it finishes, and observing that I see everything I expect to see along the way.
There is a problem in _dl_addr where I get into an infinite loop, but it seems
to be some synchronization code that doesn't agree with single step, so I have
to find the end of the loop, put a breakpoint there, continue, and then single
step again until the end.
gdb/
* riscv-tdep.c (enum opcode): Add jump, branch, lr, and sc opcodes.
(decode_register_index_short): New.
(decode_j_type_insn, decode_cj_type_insn): New.
(decode_b_type_insn, decode_cb_type_insn): New.
(riscv_insn::decode): Add support for jumps, branches, lr, and sc. New
local xlen. Check xlen when decoding ambiguous compressed insns. In
compressed decode, use is_c_lui_insn instead of is_lui_insn, and
is_c_sw_insn instead of is_sw_insn.
(riscv_next_pc, riscv_next_pc_atomic_sequence): New.
(riscv_software_single_step): New.
* riscv-tdep.h (riscv_software_single_step): Declare.
This allows the function to be used from riscv OS files, which also need to
depend on XLEN size.
gdb/
* riscv-tdep.c (riscv_isa_xlen): Drop static.
* riscv-tdep.h (riscv_isa_xlen): Add extern declaration.
gdb/
* riscv-tdep.c (riscv_has_feature): Delete comment that refers to
set_gdbarch_decr_pc_after_break. Call riscv_read_misa_reg always.
(riscv_gdbarch_init): Delete local has_compressed_isa. Delete now
unecessary braces after EF_RISCV_RVC test. Delete call to
set_gdbarch_decr_pc_after_break.
An assertion when setting up arguments for an inferior call checks the
size of the argument against xlen. However, if xlen and flen are
different sizes, and the argument is being placed into a floating
pointer register then we should be comparing against flen not xlen.
This issue shows up as an assertion failure when running on an rv32g
target with a binary compiled using the rv32f abi and making an
inferior call involving large floating point arguments, for example
the test gdb.base/infcall-nested-structs.exp.
gdb/ChangeLog:
* riscv-tdep.c (riscv_is_fp_regno_p): New function.
(riscv_register_reggroup_p): Use new function, remove unneeded
parenthesis.
(riscv_push_dummy_call): Extend assert to compare against xlen or
flen based on register type.
In debug printing, use TYPE_SAFE_NAME instead of replicating the
functionality using TYPE_NAME and a null check.
gdb/ChangeLog:
* riscv-tdep.c (riscv_print_arg_location): Use TYPE_SAFE_NAME.
The "fp" register name is an alias for "s0" which is an alias for "x8".
The "fp" name is only understood by very recent Binutils and thus not
used by GCC. GCC does not emit a frame pointer with common optimization
options such as -Og or -O2.
It is still possible to use the "fp" register name, e.g.
(gdb) p/x $fp
$1 = 0x800367c8
works.
However, in the register dump you see now:
(gdb) info registers
...
t2 0xffffffffffffffff 18446744073709551615
s0 0x800367c8 0x800367c8
s1 0x80033280 2147693184
...
gdb/
* riscv-tdep.c (riscv_register_aliases): Swap "fp" and "s0"
entries.
This patch fixes the subset of -Wimplicit-fallthrough warnings that I
considered obvious. In most cases it was obvious from context that
falling through was desired; here I added the appropriate comment. In
a couple of cases it seemed clear that a "break" was missing.
ChangeLog
2018-05-04 Tom Tromey <tom@tromey.com>
* riscv-tdep.c (riscv_isa_xlen): Add fall-through comment.
* utils.c (can_dump_core) <LIMIT_CUR>: Add fall-through comment.
* eval.c (fetch_subexp_value) <MEMORY_ERROR>: Add fall-through
comment.
* d-valprint.c (d_val_print) <TYPE_CODE_STRUCT>: Add fall-through
comment.
* coffread.c (coff_symtab_read) <C_LABEL>: Add fall-through
comment.
This converts observers from using a special source-generating script
to be plain C++. This version of the patch takes advantage of C++11
by using std::function and variadic templates; incorporates Pedro's
patches; and renames the header file to "observable.h" (this change
eliminates the need for a clean rebuild).
Note that Pedro's patches used a template lambda in tui-hooks.c, but
this failed to compile on some buildbot instances (presumably due to
differing C++ versions); I replaced this with an ordinary template
function.
Regression tested on the buildbot.
gdb/ChangeLog
2018-03-19 Pedro Alves <palves@redhat.com>
Tom Tromey <tom@tromey.com>
* unittests/observable-selftests.c: New file.
* common/observable.h: New file.
* observable.h: New file.
* ada-lang.c, ada-tasks.c, agent.c, aix-thread.c, annotate.c,
arm-tdep.c, auto-load.c, auxv.c, break-catch-syscall.c,
breakpoint.c, bsd-uthread.c, cli/cli-interp.c, cli/cli-setshow.c,
corefile.c, dummy-frame.c, event-loop.c, event-top.c, exec.c,
extension.c, frame.c, gdbarch.c, guile/scm-breakpoint.c,
infcall.c, infcmd.c, inferior.c, inflow.c, infrun.c, jit.c,
linux-tdep.c, linux-thread-db.c, m68klinux-tdep.c,
mi/mi-cmd-break.c, mi/mi-interp.c, mi/mi-main.c, objfiles.c,
ppc-linux-nat.c, ppc-linux-tdep.c, printcmd.c, procfs.c,
python/py-breakpoint.c, python/py-finishbreakpoint.c,
python/py-inferior.c, python/py-unwind.c, ravenscar-thread.c,
record-btrace.c, record-full.c, record.c, regcache.c, remote.c,
riscv-tdep.c, sol-thread.c, solib-aix.c, solib-spu.c, solib.c,
spu-multiarch.c, spu-tdep.c, stack.c, symfile-mem.c, symfile.c,
symtab.c, thread.c, top.c, tracepoint.c, tui/tui-hooks.c,
tui/tui-interp.c, valops.c: Update all users.
* tui/tui-hooks.c (tui_bp_created_observer)
(tui_bp_deleted_observer, tui_bp_modified_observer)
(tui_inferior_exit_observer, tui_before_prompt_observer)
(tui_normal_stop_observer, tui_register_changed_observer):
Remove.
(tui_observers_token): New global.
(attach_or_detach, tui_attach_detach_observers): New functions.
(tui_install_hooks, tui_remove_hooks): Use
tui_attach_detach_observers.
* record-btrace.c (record_btrace_thread_observer): Remove.
(record_btrace_thread_observer_token): New global.
* observer.sh: Remove.
* observer.c: Rename to observable.c.
* observable.c (namespace gdb_observers): Define new objects.
(observer_debug): Move into gdb_observers namespace.
(struct observer, struct observer_list, xalloc_observer_list_node)
(xfree_observer_list_node, generic_observer_attach)
(generic_observer_detach, generic_observer_notify): Remove.
(_initialize_observer): Update.
Don't include observer.inc.
* Makefile.in (generated_files): Remove observer.h, observer.inc.
(clean mostlyclean): Likewise.
(observer.h, observer.inc): Remove targets.
(SUBDIR_UNITTESTS_SRCS): Add observable-selftests.c.
(COMMON_SFILES): Use observable.c, not observer.c.
* .gitignore: Remove observer.h.
gdb/doc/ChangeLog
2018-03-19 Tom Tromey <tom@tromey.com>
* observer.texi: Remove.
gdb/testsuite/ChangeLog
2018-03-19 Tom Tromey <tom@tromey.com>
* gdb.gdb/observer.exp: Remove.
Fix some ARI issues in recently added riscv code, the ARI email is:
https://sourceware.org/ml/gdb-patches/2018-03/msg00156.html
gdb/ChangeLog:
* riscv-tdep.c (riscv_sw_breakpoint_from_kind): Add localization
to error message string.
(riscv_register_name): Use xsnprintf instead of sprintf.
(riscv_insn::fetch_instruction): Use gdb_assert instead of
internal_error.
(riscv_print_arg_location): Use gdb_assert_not_reached instead of
error.
(riscv_push_dummy_call): Likewise.
Some parts of the target description support were committed with the
initial riscv patch. As target descriptions are not currently supported
on riscv this commit removes the two pieces for code that relate to
target description support.
It is expected that target description support will be added in the
future, at which point this, or similar code will be added back.
gdb/ChangeLog:
* riscv-tdep.c (riscv_register_name): Remove target description
support.
(riscv_gdbarch_init): Remove target description check.
The GDB coding standard states these lines should never have been
added.
gdb/ChangeLog:
* riscv-tdep.c: Remove 'Contributed by ...' lines from header
comment.
* riscv-tdep.h: Likewise.
The code making use of pseudo registers was initially intended to
support running 32-bit ABI files on 64-bit riscv targets. However, the
implementation was incomplete, and broken.
For now I've removed all reference to pseudo registers from the riscv
target, we've not lost any functionality, and this cleans up failures in
the selftests.
Once the riscv target has matured a little we'll probably end up
bringing back some of the use of pseudo registers in order to better
support running 32-bit executables on a 64-bit target.
gdb/ChangeLog:
* riscv-tdep.c (riscv_pseudo_register_read): Delete.
(riscv_pseudo_register_write): Delete.
(riscv_gdbarch_init): Remove all use of pseudo registers.
Should use a ULONGEST when reading from the regcache.
gdb/ChangeLog:
* riscv-tdep.c (riscv_return_value): Change type to ULONGEST for
reading values from registers.
Some of the format strings used in the new riscv target were incorrect,
resulting in build failures on some hosts. This commit does the
following:
1. Uses core_addr_to_string for formatting CORE_ADDR types.
2. Fixes legacy use of stderr for logging in one place that got
missed, instead gdb_stdlog is used.
3. Re-indent a few printf related lines that were wrong.
This should resolve some (but not all) of the build failures the new
riscv target introduced.
gdb/ChangeLog:
* riscv-tdep.c (riscv_print_arg_location): Add header comment,
change parameter type. Use GDB's print functions, and use
core_addr_to_string where appropriate.
(riscv_push_dummy_call): Use core_addr_to_string where
appropriate, update call to riscv_print_arg_location, and reindent
a few lines.
(riscv_return_value): Update call to riscv_print_arg_location.
This commit introduces basic support for baremetal RiscV as a GDB
target. This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit. The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.
Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.
The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing. The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature. As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
(HFILES_NO_SRCDIR): Add riscv-tdep.h.
(ALLDEPFILES): Add riscv-tdep.c
* configure.tgt: Add riscv support.
* riscv-tdep.c: New file.
* riscv-tdep.h: New file.
* NEWS: Mention new target.
* MAINTAINERS: Add entry for riscv.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: New file.
* gdb.base/infcall-nested-structs.c: New file.
* gdb.base/float.exp: Add riscv support.
